TW202111542A - Memory chip, memory module and method for pseudo-accessing memory bbank thereof - Google Patents

Abstract

The present invention provides a memory chip includes a plurality of memory banks, a plurality of address pins, and a pseudo-address determining circuit. The plurality of address pins is arranged for receiving a plurality of address signals corresponding to the plurality of memory banks, respectively. The pseudo-address determining circuit has a plurality of input terminals coupled to the plurality of address pins, respectively, and a plurality of output terminals coupled to the plurality of memory banks. The pseudo-address determining circuit generates a pseudo-address table for the plurality of memory banks when the memory chip is powered-up. The pseudo-address table has a plurality of pseudo-addresses corresponding to the plurality of memory banks, respectively. The present invention also provides a memory module that incorporates said memory chip and a method for pseudo-accessing memory banks of said memory chip.

Description

Memory chip, memory module and method for false access to its memory bank

The present invention relates to a memory chip, in particular to a memory chip that can falsely access its memory bank.

Random Access Memory (RAM) is a form of computer data storage used to store currently used data and machine code. The random access memory device can allow data to be read or written in almost the same time regardless of the physical location of the data in the memory.

RAM contains multiplexing and demultiplexing circuits for connecting data to address memory to read or write entries. Usually, the same address can access more than one bit of storage area.

In order to be useful, the memory cell must be readable and writable. In RAM devices, multiplexing and demultiplexing circuits are used to select memory cells. Generally, a RAM device has a set of address lines A0...An, and for each bit combination that can be applied to these address lines, a set of corresponding memory cells can be activated. Due to this addressing method, RAM devices almost always have a power-of-two memory capacity.

Many RAM systems have a hierarchical structure composed of memory cells, memory banks, memory rows, memory modules, and memory channels. Please refer to FIG. 1, which shows a block diagram of the hierarchical structure of the RAM system. A central processing unit (CPU) 1 is coupled to one or more memory channels 2a~2b. Each of the memory channels 2a to 2b may include a plurality of memory modules 3. Each memory module 3 can have one or two memory banks 4, which include several memory chips 5. Each memory chip 5 includes several memory banks 6. The memory bank 6 is formed by a number of memory cells 7 arranged in an array.

Memory device manufacturers are accustomed to guaranteeing that their products have a certain service life or even a lifetime warranty. The warranty years are usually estimated based on the following concept: the memory device can evenly distribute the total number of access operations that can be performed among all the memory banks of the memory device. In some over-simplified implementations, an application may have very low memory requirements (much smaller than the memory capacity of the system it is equipped with), but it needs to access the memory very frequently. The application of may access certain memory banks more frequently than other memory banks. Ultimately, this will lead to premature deterioration of heavily accessed memory banks.

Therefore, the object of the present invention is to provide a memory chip which can falsely access its memory bank, so as to prevent the premature deterioration of the memory bank.

In order to achieve the above objective, according to one aspect of the present invention, a memory chip is provided. The memory chip includes: Multiple memory banks; A plurality of address pins are used to receive a plurality of address signals corresponding to the memory banks; and A virtual address determination circuit, which has a plurality of input pins and a plurality of output pins, wherein the input pins are respectively coupled to the address pins, and the output pins are coupled to the memory banks , When the memory chip is powered on, the virtual address determining circuit generates a virtual address table for the memory banks, The virtual address table has a plurality of virtual addresses corresponding to the memory banks, and each of the memory banks is set to be accessed according to the corresponding virtual address.

In order to achieve the above objective, according to another aspect of the present invention, a memory module is provided. The memory module includes: A printed circuit board; A control circuit arranged on the printed circuit board; and A plurality of memory chips are disposed on the printed circuit board and coupled to the control circuit, wherein each of the memory chips includes: Multiple memory banks; A plurality of address pins are used to receive a plurality of address signals corresponding to the memory banks; and A virtual address determining circuit has a plurality of input pins and a plurality of output pins, wherein the input pins are respectively coupled to the address pins, and the output pins are coupled to the memory banks , When the memory chip is powered on, the virtual address determining circuit generates a virtual address table for the memory banks, The virtual address table has a plurality of virtual addresses corresponding to the memory banks, and each of the memory banks is set to be accessed according to the corresponding virtual address.

In order to achieve the above objective, according to another aspect of the present invention, a method for falsely accessing a plurality of memory banks of a memory chip is proposed. The method includes: When the memory chip is powered on, a virtual address table is generated for the memory banks. The virtual address table is stored in a memory, and each of the memory banks corresponds to the virtual address table. A virtual address in the address table; Receiving a control signal with an address signal, the address signal indicating the destination memory bank to which the control signal will be sent; Determine a virtual address according to the address signal indicating the destination memory bank and the virtual address table; and The control signal is redirected to a pseudo memory bank indicated by the virtual address.

Through these settings, the memory chip, the memory module, and the method for falsely accessing the memory banks of a memory chip can change the virtual location of the memory bank every time the memory chip is powered on Address table. In this way, regardless of the design or implementation of the application, the frequency of accessing each memory bank will be evenly distributed among all the memory banks. In other words, the present invention can prevent the premature deterioration of the memory bank due to heavy access.

The present invention will now be described through some preferred embodiments of the present invention and with reference to the drawings.

Please refer to FIG. 2, which shows a block diagram of a memory chip according to an embodiment of the present invention. In FIG. 2, the memory chip 10 includes a plurality of memory banks 11 to 14, a plurality of address pins P1 to P2 and a virtual address determination circuit 15.

The address pins P1 to P2 are used to receive the address signals S11 to S14 corresponding to the memory banks 11 to 14 respectively. In other words, the address signals S11~S14 will constitute 4 possible results of the voltage levels of the address pins P1~P2. Please refer to FIG. 3, which is an address table of the memory chip 10 according to an embodiment of the present invention. In Figure 3, the address signal S11 makes the voltage levels of the position pins P1 and P2 relatively high (represented by the number "1"), and the address signal S12 makes the voltage levels of the address pin P1 relatively high High and the voltage level of the address pin P2 is relatively low (indicated by the number "0"). The address signal S13 makes the voltage level of the address pin P1 relatively low and the voltage level of the address pin P2 relatively low High, the address signal S14 makes the voltage levels of both the position pins P1 and P2 relatively low. In this embodiment, if an address signal is received and the voltage levels of both the address pins P1 to P2 are relatively high, it means that the address signal S11 is received. Then the memory chip 10 will determine that the memory bank 11 is a target memory bank for the upcoming operation. In the previous embodiment, it is also helpful to regard the location pin P1 as a row address and the address pin P2 as a column location pin. In other words, the address pin P1 is set to receive the voltage level used to determine which row of the memory banks 11-14 is the target memory bank, and the address pin P2 is set In order to receive the voltage level used to determine which row of the memory banks 11-14 the target memory bank is located. Please note that the number of address pins in this embodiment is only for illustrative purposes, and is not meant to limit the present invention. Without departing from the spirit of the present invention, those skilled in the art can make modifications and changes according to the actual design and requirements of the application.

Please refer to FIG. 2 again. In FIG. 2, the virtual address determining circuit 15 has a plurality of input pins and a plurality of output pins. The input pins of the virtual address determining circuit 15 are respectively coupled to the address pins P1~P2. The output pins of the virtual address determining circuit 15 are coupled to the memory banks 11-14. In another design, the output pins of the virtual address determining circuit 15 can be coupled to the memory banks 11-14 through a row address controller and a column address controller. In this way, the output pin coupled to the row address controller will send a row selection signal to the row address controller to determine which row of the array of the memory banks 11-14 the target memory bank is located. And the output pin coupled to the column address controller will send a column selection signal to the column address controller to determine which row of the array of the memory banks 11-14 the target memory bank is located . In any of the above designs, the signal output from the output interface of the virtual address determining circuit 15 will determine the address of the memory bank to be operated on.

In addition, whenever the memory chip 10 is powered on, the virtual address determining circuit 15 will generate a virtual address table for the memory banks 11-14. Then the virtual address table can be stored in a register and the virtual address table can be searched in the register. For example, please refer to Figure 3, Figure 4, and Figure 5 at the same time. 4 and 5 show virtual address tables of the memory chip 10 according to different embodiments of the present invention. In the virtual address table of FIG. 4, the virtual address table is generated so that the memory banks 11 to 14 correspond to the address signals S11 to S14, and the address signals S11 to S14 are relative to the bits of FIG. 3. The address table is the addresses of different rows in the memory banks 11-14 that are represented by shifting. In Figure 4, the address signal S11 now corresponds to the memory bank 12, the address signal S12 now corresponds to the memory bank 13, the address signal S13 now corresponds to the memory bank 14, and the address signal S14 now corresponds to the memory bank 14. Library 11. To be precise, the corresponding positions of the memory banks 11-14 in FIG. 4 are the corresponding positions of the memory banks 11-14 in FIG. 3 that are "cyclically shifted" one step downward. In other words, in the embodiment of FIG. 4, the memory bank 12 can only be accessed through the address signal S13. When the developer intends to access the memory bank 13, he will change to "fake access" to the memory bank 12. In applications where the memory bank 13 is severely over-accessed, the virtual address table determination circuit 15 generated by the virtual address will secretly transfer some of the operational burden of the memory bank 13 to the memory bank 12 without any further The configuration of this method can prevent the memory bank 13 from decay in advance. Whenever the memory chip 10 is powered on, the virtual address determining circuit 15 generates a new virtual address table. This will distribute the load of the memory bank 13 that should have been heavily accessed to another memory bank.

In FIG. 5, the virtual address table is randomly generated by the virtual address determining circuit 15. For example, the virtual address is generated by first copying the address table and then replacing the column addresses of the memory banks 11-14 of the address table to be copied with the randomly sorted column addresses of the memory banks 11-14 table. Statistically speaking, if a virtual address is randomly generated during the iterative increase of the virtual address, the reliability of the memory chip 10 will increase.

Please refer to FIG. 6, which shows a block diagram of a memory chip and an exemplary virtual address table according to another embodiment of the present invention. Please note that the memory chip 20 and the memory chip 10 share some components. If the components in the memory chip 20 are substantially the same as those in the memory chip 10, they will be represented by the same symbols to avoid confusion. In FIG. 6, the memory chip 20 further includes a controller 26. The controller 26 is coupled to the virtual address determination circuit 15 and is used to send a control signal S_C, which has an address signal indicating the destination memory bank to which the control signal S_C is to be sent. For example, the controller 26 is about to write data to the memory bank 11. The controller 26 issues a control signal S_C indicating a write operation and the address signal S11 indicating that the target memory bank is the memory bank 11. In this embodiment, the virtual address determining circuit 15 then determines the virtual address of the memory bank 11, that is, the memory bank 13 according to the position signal S11 and the virtual address table of FIG. 6. The virtual address determination circuit 15 then redirects the control signal S_C to the memory bank 13.

Please refer to FIG. 7, which shows a block diagram of a memory chip and an exemplary virtual address table according to another embodiment of the present invention. Please note that a memory chip 30 shares some components with the memory chip 10 and the memory chip 20. If the components in the memory chip 30 are substantially the same as the components in the memory chip 10 and the memory chip 20, they are represented by the same symbols to avoid confusion. In FIG. 7, the memory chip 30 also includes a controller 36. The controller 36 is coupled to the virtual address determining circuit 15 and the memory banks 11-14. The controller 36 is used to send a control signal S_C, which has an address signal indicating the destination memory bank to which the control signal S_C will be sent. In this embodiment, the address signal indicating the destination memory bank is sent to the virtual address determining circuit 15. The virtual address determining circuit 15 determines a virtual address according to the received address signal and the virtual address table, and sends the address signal corresponding to the virtual address back to the controller 36. The controller 36 then redirects the control signal S_C to the pseudo memory bank indicated by the virtual address. For example, the controller 26 is about to write data to the memory bank 11. The controller 36 issues a control signal S_C indicating a write operation and the address signal S11 indicating that the target memory bank is the memory bank 11. In this embodiment, the virtual address determining circuit 15 then determines the virtual address of the memory bank 11, that is, the memory bank 14 according to the position signal S11 and the virtual address table of FIG. The virtual address determining circuit 15 then sends the address signal S14 back to the controller 36. The controller 36 then redirects the control signal S_C to the memory bank 14.

The aforementioned memory chips 10, 20, and 30 can be further integrated into a memory module. Please refer to FIG. 8, which shows a memory module according to an embodiment of the present invention. In FIG. 8, the memory module 40 includes a printed circuit board 41, a control circuit 42 and a plurality of memory chips 10. The control circuit 42 is arranged on the printed circuit board 41 and used to select a target memory chip 10. The memory chips 10 are arranged on the printed circuit board 41 and connected to the control circuit 42. For the structure and operation of the memory chips 10, please refer to the above paragraphs. For brevity, detailed description will be omitted here.

Please refer to FIG. 9, which shows a memory module according to an embodiment of the present invention. Please note that the memory module 50 and the memory module 40 share some components. If the components in the memory module 40 are substantially the same as the components in the memory module 50, they will be represented by the same symbols to avoid confusion. In FIG. 9, the memory module 50 includes a printed circuit board 41, a control circuit 42 and a plurality of memory chips 20. For the structure and operation of the memory chips 20, please refer to the above paragraphs. For brevity, detailed description will be omitted here.

Please refer to FIG. 10, which shows a memory module according to an embodiment of the present invention. Please note that the memory module 60 shares some components with the memory module 40 and the memory module 50. If the components in the memory module 60 are substantially the same as the components in the memory module 40 and the memory module 50, they will be represented by the same symbols to avoid confusion. In FIG. 10, the memory module 60 includes a printed circuit board 41, a control circuit 42 and a plurality of memory chips 30. For the structure and operation of the memory chips 30, please refer to the above paragraphs. For brevity, detailed description will be omitted here.

The virtual address determination circuit 15 can also be disabled by a test mode enable signal. When testing the reliability of the memory chip 10, it is very important that the tester can test the actual target memory bank without false access. Using the test mode enable signal to disable the virtual address determination circuit 15 will provide flexibility in the application of the memory chip 10, 20, or 30.

Please refer to FIG. 11, which is a flowchart of a method for falsely accessing a memory bank of a memory chip according to an exemplary embodiment of the present invention. If the results are substantially the same, there is no need to perform the steps in the exact order shown in FIG. 11. The exemplary method can be composed of the memory chip 10 shown in FIG. 2, the memory chip 20 shown in FIG. 6, the memory chip 30 shown in FIG. 7, and the memory module 40 shown in FIG. , The module 50 in FIG. 9 and the memory module 60 in FIG. 10 are implemented. The steps of the method can be summarized as follows.

Step 1101: When the memory chip is powered on, generate a virtual address table for the memory.

Step 1102: Receive a control signal, which has an address signal indicating the destination memory bank to which the control signal will be sent.

Step 1104: Determine a virtual address according to the address signal, which indicates the target memory bank and the virtual address table.

Step 1106: Redirect the control signal to the pseudo memory bank indicated by the virtual address.

In the method 1100, the virtual address table is stored in a memory, and each of the memory banks corresponds to a virtual address in the virtual address table. Step 1101 can be performed by the virtual address determining circuit 15 of the memory chip 10, 20 or 30. Step 1102 can be executed by the virtual address determination circuit 15. The address signal is sent by the controller 26, or step 1104 can be executed by the virtual address determination circuit 15 of the memory chip 10, 20, or 30. Step 1106 can be executed by the virtual address determining circuit 15 or the controller 26 or 36.

The present invention has been described above with some preferred embodiments of the present invention, and it should be understood that the preferred embodiments are only illustrative and are not intended to limit the present invention in any way, and may Many changes and modifications are made in the case of the embodiment. The scope and spirit of the present invention are intended to be limited only by the scope of the attached patent application.

1: CPU 2a, 2b: memory channel 3: Memory module 4: Memory row 5: Memory chip 6: Memory Bank 7: Memory unit 10: Memory chip 11, 12, 13, 14: memory bank 15: Virtual address determining circuit 26, 36: Controller 20, 30: memory chip 40, 50, 60: memory module 41: Printed Circuit Board 42: control circuit P1, P2: pins S11, S12, S13, S14, S_C: signal 1100: Method 1101, 1102, 1104, 1106: steps

By referring to the detailed description and drawings of the following preferred embodiments, one can best understand the structure and technical means adopted by the present invention to achieve the above or other objectives. Figure 1 is a block diagram of the traditional RAM system hierarchy. FIG. 2 is a block diagram of a memory chip according to an embodiment of the invention. FIG. 3 is an address table of a memory chip according to an embodiment of the invention. FIG. 4 is a virtual address table of a memory chip according to different embodiments of the present invention. FIG. 5 is a virtual address table of a memory chip according to different embodiments of the present invention. FIG. 6 is a block diagram and exemplary virtual address table of a memory chip according to another embodiment of the present invention. FIG. 7 is a block diagram and exemplary virtual address table of a memory chip according to another embodiment of the present invention. FIG. 8 shows a memory module according to different embodiments of the present invention. FIG. 9 is a memory module according to different embodiments of the present invention. FIG. 10 shows a memory module according to different embodiments of the present invention. FIG. 11 is a flowchart of a method for falsely accessing a memory bank of a memory chip according to an exemplary embodiment of the present invention.

10: Memory chip

11, 12, 13, 14: memory bank

15: Virtual address determining circuit

P1, P2: pins

S11, S12, S13, S14: signal

Claims (12)

A memory chip, including: Multiple memory banks; A plurality of address pins are used to receive a plurality of address signals corresponding to the memory banks; and A virtual address determination circuit, which has a plurality of input pins and a plurality of output pins, wherein the input pins are respectively coupled to the address pins, and the output pins are coupled to the memory banks , When the memory chip is powered on, the virtual address determining circuit generates a virtual address table for the memory banks, The virtual address table has a plurality of virtual addresses corresponding to the memory banks, and each of the memory banks is set to be accessed according to the corresponding virtual address. The memory chip according to claim 1, wherein the virtual address determining circuit randomly generates the virtual address table for the memory banks. The memory chip described in claim 2 further includes: A controller is coupled to the virtual address determining circuit and used to send a control signal with an address signal, the bit signal indicating the target memory bank to which the control signal is to be sent, The virtual address determination circuit determines the virtual address according to the address signal of the indicated destination memory bank and the virtual address table, and the virtual address determination circuit redirects the control signal to the virtual address instruction Of a pseudo memory bank. The memory chip described in claim 2 further includes: A controller is coupled to the virtual address determining circuit and used to send a control signal with an address signal, the bit signal indicating the target memory bank to which the control signal is to be sent, The virtual address determination circuit determines the virtual address according to the address signal indicating the target memory and the virtual address table, and the controller redirects the control signal to a pseudo-address indicated by the virtual address. Memory bank. The memory chip according to claim 1, wherein the virtual address determination circuit is disabled in response to a test mode enable signal. A memory module, including: A printed circuit board; A control circuit arranged on the printed circuit board; and A plurality of memory chips are disposed on the printed circuit board and coupled to the control circuit, wherein each of the memory chips includes: Multiple memory banks; A plurality of address pins are used to receive a plurality of address signals corresponding to the memory banks; and A virtual address determining circuit has a plurality of input pins and a plurality of output pins, wherein the input pins are respectively coupled to the address pins, and the output pins are coupled to the memory banks , When the memory chip is powered on, the virtual address determining circuit generates a virtual address table for the memory banks, The virtual address table has a plurality of virtual addresses corresponding to the memory banks, and each of the memory banks is set to be accessed according to the corresponding virtual address. The memory module according to claim 6, wherein the virtual address determining circuit randomly generates the virtual address table for the memory banks. The memory module according to claim 7, wherein each of the memory chips further includes: A controller is coupled to the virtual address determining circuit and used to send a control signal with an address signal, the bit signal indicating the target memory bank to which the control signal is to be sent, The virtual address determination circuit determines the virtual address according to the address signal of the indicated destination memory bank and the virtual address table, and the virtual address determination circuit redirects the control signal to the virtual address instruction Of a pseudo memory bank. The memory module according to claim 7, wherein each of the memory chips further includes: A controller is coupled to the virtual address determining circuit and used to send a control signal with an address signal, the bit signal indicating the target memory bank to which the control signal is to be sent, The virtual address determination circuit determines the virtual address according to the address signal indicating the target memory and the virtual address table, and the controller redirects the control signal to a pseudo-address indicated by the virtual address. Memory bank. The memory module according to claim 6, wherein the virtual address determination circuit is disabled in response to a test mode enable signal. A method for falsely accessing a plurality of memory banks of a memory chip includes: When the memory chip is powered on, a virtual address table is generated for the memory banks. The virtual address table is stored in a memory, and each of the memory banks corresponds to the virtual address table. A virtual address in the address table; Receiving a control signal with an address signal, the address signal indicating the destination memory bank to which the control signal will be sent; Determine a virtual address according to the address signal indicating the destination memory bank and the virtual address table; and The control signal is redirected to a pseudo memory bank indicated by the virtual address. The method according to claim 11, wherein the step of generating the virtual address table for the memory banks is performed by randomly generating the virtual address table for the memory banks.

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