TW201916182A - Electronic package - Google Patents
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- TW201916182A TW201916182A TW106131573A TW106131573A TW201916182A TW 201916182 A TW201916182 A TW 201916182A TW 106131573 A TW106131573 A TW 106131573A TW 106131573 A TW106131573 A TW 106131573A TW 201916182 A TW201916182 A TW 201916182A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
一種電子封裝件,係於承載結構之表面上定義出複數個設有接地接點之接地區域,使該電子元件可依其功能規格選擇性電性連接至少一個接地區域之接地接點,以滿足該電子元件所需之較大或較小的接地電位。 An electronic package defines a plurality of grounding regions provided with ground contacts on a surface of the supporting structure, so that the electronic component can be selectively electrically connected to the grounding contact of at least one grounding region according to the functional specifications thereof. The larger or smaller ground potential required for the electronic component.
Description
本發明係有關一種封裝技術,尤指一種能提升電性功能之電子封裝件。 The invention relates to a packaging technology, in particular to an electronic package capable of improving electrical functions.
隨著半導體技術的演進,半導體產品已開發出不同封裝產品型態,而為提升電性品質,多種半導體產品具有屏蔽之功能,以防止電磁干擾(Electromagnetic Interference,簡稱EMI)產生。 With the evolution of semiconductor technology, semiconductor products have developed different package product types, and in order to improve electrical quality, a variety of semiconductor products have a shielding function to prevent electromagnetic interference (Electromagnetic Interference, referred to as EMI).
如第1A及1B圖所示,習知半導體封裝件1係將一半導體晶片11設在一封裝基板10上,再以封裝膠體12包覆該半導體晶片11,之後於該封裝膠體12及該封裝基板10之側面10c上形成一金屬屏蔽層13,以藉由該金屬屏蔽層13電性連接外露於該封裝基板10之側面10c之接地部102,再與外部系統接地,藉以保護該半導體晶片11免受外界EMI影響而受損。 As shown in FIGS. 1A and 1B, the conventional semiconductor package 1 is provided with a semiconductor wafer 11 on a package substrate 10, and then the semiconductor wafer 11 is covered with an encapsulant 12, after which the encapsulant 12 and the package are encapsulated. A metal shielding layer 13 is formed on the side surface 10c of the substrate 10 to electrically connect the grounding portion 102 exposed on the side surface 10c of the package substrate 10 to the grounding portion 102 of the package substrate 10, and then grounded to the external system, thereby protecting the semiconductor wafer 11. Protected from external EMI and damaged.
習知封裝基板10通常具有複數線路層100,各該線路層100之間由絕緣層相互隔離,且於該絕緣層內形成複數導電盲孔以電性連接於各該線路層100之間。下側線路層100亦具有複數植球墊101以供該半導體封裝件1外接至 印刷電路板(圖略),且上側線路層100係包含有一接地區G與一訊號區S,以令該接地區G之接地接點103電性連接該線路層100之接地部102且藉由複數銲線14電性連接該半導體晶片11之接地墊110,且令該訊號區S之訊號接點104藉由複數銲線14電性連接該半導體晶片11之訊號墊111。 The conventional package substrate 10 generally has a plurality of circuit layers 100. The circuit layers 100 are separated from each other by an insulating layer, and a plurality of conductive via holes are formed in the insulating layer to be electrically connected between the circuit layers 100. The lower circuit layer 100 also has a plurality of ball pads 101 for external connection of the semiconductor package 1 to the printed circuit board (not shown), and the upper circuit layer 100 includes a connection region G and a signal region S for the connection. The grounding contact 103 of the region G is electrically connected to the grounding portion 102 of the circuit layer 100, and is electrically connected to the grounding pad 110 of the semiconductor wafer 11 by a plurality of bonding wires 14, and the signal contact 104 of the signal region S is made by The plurality of bonding wires 14 are electrically connected to the signal pads 111 of the semiconductor wafer 11.
惟,習知半導體封裝件1中,該半導體晶片11所需之功能越來越多,使得該半導體晶片11需傳遞/接收更多訊號,故經由該訊號墊111通過該半導體晶片11之電流增加,致使該半導體晶片11所需之接地電位隨之增加,導致該封裝基板10之單一接地區G已無法滿足該半導體晶片11之接地電位之需求。 However, in the conventional semiconductor package 1, the semiconductor wafer 11 requires more and more functions, so that the semiconductor wafer 11 needs to transmit/receive more signals, so the current through the semiconductor wafer 11 via the signal pad 111 increases. As a result, the ground potential required for the semiconductor wafer 11 is increased, resulting in the single-connected region G of the package substrate 10 failing to meet the ground potential of the semiconductor wafer 11.
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。 Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.
鑒於上述習知技術之缺失,本發明提供一種電子封裝件,係包括:承載結構,係定義有第一接地區域與第二接地區域,其中,該第一接地區域設有至少一第一接地接點,且該第二接地區域設有至少一第二接地接點;以及電子元件,係設於該承載結構上並電性連接該第一及/或第二接地接點,且該電子元件係位於該第一接地區域中,令部分該第一接地區域位於該第二接地區域與該電子元件之間。 In view of the above-mentioned deficiencies of the prior art, the present invention provides an electronic package comprising: a load-bearing structure defining a first grounding area and a second grounding area, wherein the first grounding area is provided with at least one first grounding connection And the second grounding area is provided with at least one second grounding contact; and the electronic component is disposed on the supporting structure and electrically connected to the first and/or second grounding contact, and the electronic component is Located in the first grounding region, a portion of the first grounding region is located between the second grounding region and the electronic component.
前述之電子封裝件中,該第一接地區域之分佈面積係大於或等於該第二接地區域之分佈面積。 In the above electronic package, the distribution area of the first grounding region is greater than or equal to the distribution area of the second grounding region.
前述之電子封裝件中,該承載結構係設有複數個該第一接地接點及複數個該第二接地接點。 In the above electronic package, the carrying structure is provided with a plurality of the first ground contacts and a plurality of the second ground contacts.
前述之電子封裝件中,該電子元件具有銲墊,以藉由第一導電元件電性連接該銲墊與該第一接地接點。例如,該第一導電元件係為銲線。進一步地,該第一接地接點藉由第二導電元件電性連接第二接地接點,例如,該第二導電元件係為銲線。 In the above electronic package, the electronic component has a solder pad to electrically connect the pad to the first ground contact by the first conductive component. For example, the first conductive element is a wire bond. Further, the first ground contact is electrically connected to the second ground contact by the second conductive element, for example, the second conductive element is a bonding wire.
前述之電子封裝件中,該第二接地區域復設有至少一訊號接點,其藉由第三導電元件電性連接該訊號接點與該電子元件。例如,該第三導電元件係為銲線。進一步地,該電子元件具有用以電性連接該第三導電元件之電極墊,且該電極墊與該訊號接點排列於同一直線上。 In the above electronic package, the second grounding region is provided with at least one signal contact, and the third conductive component is electrically connected to the signal contact and the electronic component. For example, the third conductive element is a wire bond. Further, the electronic component has an electrode pad for electrically connecting the third conductive component, and the electrode pad is aligned with the signal contact on the same line.
前述之電子封裝件中,該電子元件具有用以電性連接該第一及/或第二接地接點之銲墊,且該銲墊與該第一接地接點及該第二接地接點係排列於同一直線上。 In the above electronic package, the electronic component has a pad for electrically connecting the first and/or second ground contacts, and the pad and the first ground contact and the second ground contact are Arrange on the same line.
前述之電子封裝件中,復包括形成於該承載結構上且包覆該電子元件之封裝層。 In the foregoing electronic package, an encapsulation layer formed on the carrier structure and covering the electronic component is further included.
前述之電子封裝件中,該第一接地區域與該第二接地區域之間形成有訊號線。 In the above electronic package, a signal line is formed between the first ground region and the second ground region.
前述之電子封裝件中,該電子元件具有銲墊,且該銲墊以第四導電元件電性連接該第二接地接點。 In the above electronic package, the electronic component has a solder pad, and the solder pad is electrically connected to the second ground contact by a fourth conductive component.
由上可知,本發明之電子封裝件,主要藉由該承載結構定義有複數接地區域(即第一接地區域與第二接地區域),使該電子元件可選擇性電性連接該第一及/或第二接 地接點,故相較於習知技術,當通過具多功能之電子元件之電流增加時,可將該電子元件電性連接該第一及第二接地接點,以滿足該電子元件之接地電位之需求。 As can be seen from the above, the electronic package of the present invention mainly defines a plurality of grounding regions (ie, a first grounding region and a second grounding region) by the supporting structure, so that the electronic component can be selectively electrically connected to the first and/or Or a second ground contact, so that the electronic component can be electrically connected to the first and second ground contacts to meet the electron when the current through the multi-function electronic component is increased compared with the prior art. The requirement of the ground potential of the component.
1‧‧‧半導體封裝件 1‧‧‧Semiconductor package
10‧‧‧封裝基板 10‧‧‧Package substrate
10c‧‧‧側面 10c‧‧‧ side
100‧‧‧線路層 100‧‧‧Line layer
101‧‧‧植球墊 101‧‧‧Ball mat
102‧‧‧接地部 102‧‧‧ Grounding Department
103‧‧‧接地接點 103‧‧‧ Grounding contacts
104,200b‧‧‧訊號接點 104,200b‧‧‧Signal contacts
11‧‧‧半導體晶片 11‧‧‧Semiconductor wafer
110‧‧‧接地墊 110‧‧‧Grounding mat
111‧‧‧訊號墊 111‧‧‧Signal pad
12‧‧‧封裝膠體 12‧‧‧Package colloid
13‧‧‧金屬屏蔽層 13‧‧‧Metal shield
14‧‧‧銲線 14‧‧‧welding line
2,3‧‧‧電子封裝件 2,3‧‧‧Electronic package
20‧‧‧承載結構 20‧‧‧bearing structure
20a‧‧‧表面 20a‧‧‧ surface
200‧‧‧線路 200‧‧‧ lines
200a‧‧‧導電跡線 200a‧‧‧conductive traces
200c‧‧‧電性端點 200c‧‧‧Electrical endpoint
201‧‧‧第一接地接點 201‧‧‧First ground contact
202‧‧‧第二接地接點 202‧‧‧Second grounding contact
21,51‧‧‧第一導電元件 21,51‧‧‧First conductive element
22‧‧‧第二導電元件 22‧‧‧Second conductive element
23‧‧‧第三導電元件 23‧‧‧ Third conductive element
24‧‧‧電子元件 24‧‧‧Electronic components
240‧‧‧銲墊 240‧‧‧ solder pads
241‧‧‧電極墊 241‧‧‧electrode pads
25‧‧‧封裝層 25‧‧‧Encapsulation layer
300‧‧‧訊號線 300‧‧‧ signal line
54‧‧‧第四導電元件 54‧‧‧fourth conductive element
A‧‧‧第一接地區域 A‧‧‧First grounding area
B‧‧‧第二接地區域 B‧‧‧Second grounding area
C,D‧‧‧虛線 C, D‧‧‧ dotted line
L,r,t‧‧‧長度 L, r, t‧‧‧ length
G‧‧‧接地區 G‧‧‧Contact area
S‧‧‧訊號區 S‧‧‧ Signal Zone
第1A圖係為習知半導體封裝件之剖面示意圖;第1B圖係為第1A圖之局部上視示意圖;第2A圖係為本發明之電子封裝件之剖面示意圖;第2B及2C圖係為第2A圖之局部上視示意圖;第2D圖係為本發明之電子封裝件之另一剖面示意圖;第3圖係為本發明之電子封裝件之另一實施例的局部上視示意圖;第4A圖係為本發明之電子封裝件之再一實施例的剖面示意圖;以及第4B圖係為第4A圖之局部上視示意圖。 1A is a schematic cross-sectional view of a conventional semiconductor package; FIG. 1B is a partial top view of FIG. 1A; FIG. 2A is a schematic cross-sectional view of the electronic package of the present invention; FIGS. 2B and 2C are 2A is a partial cross-sectional view of the electronic package of the present invention; FIG. 3 is a partial top view of another embodiment of the electronic package of the present invention; The figure is a schematic cross-sectional view of still another embodiment of the electronic package of the present invention; and FIG. 4B is a partial top view of FIG. 4A.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術 內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.
第2A至2D圖係為本發明之電子封裝件2之第一實施例的示意圖。 2A to 2D are schematic views of the first embodiment of the electronic package 2 of the present invention.
如第2A至2D圖所示,所述之電子封裝件2係包括:一承載結構20、至少一電子元件24、至少一第一導電元件21、至少一第二導電元件22以及一封裝層25。 As shown in FIGS. 2A to 2D, the electronic package 2 includes a carrier structure 20, at least one electronic component 24, at least one first conductive component 21, at least one second conductive component 22, and an encapsulation layer 25. .
所述之承載結構20係於一表面20a上定義有相互分離之第一接地區域A與第二接地區域B,且該電子元件24係位於該第一接地區域A中,令部分該第一接地區域A位於該第二接地區域B與該電子元件24之間,亦即該第一接地區域A較該第二接地區域B鄰近該電子元件24,其中,該第一接地區域A上佈設有複數(如圖所示之三個)第一接地接點201,而於該第二接地區域B上佈設有相互分離之複數(如圖所示之三條)線路200與複數(如圖所示之三個)第二接地接點202。 The carrying structure 20 is defined on a surface 20a defining a first grounding area A and a second grounding area B separated from each other, and the electronic component 24 is located in the first grounding area A, so that the first grounding portion The area A is located between the second ground area B and the electronic component 24, that is, the first ground area A is adjacent to the electronic component 24, and the first ground area A is provided with a plurality of (three as shown) the first ground contact 201, and the second ground area B is provided with a plurality of lines (three as shown) separated from each other by a line 200 and a plurality (as shown in the figure) a second ground contact 202.
於本實施例中,該承載結構20係為具有核心層之線路構造或無核心層(coreless)之線路構造,而具有複數線路層(圖略,可參考第1圖之線路層100),例如為核心基板、無核心基板或扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL),且該線路層於該承載結構20之表面20a 上包含有該些第一接地接點201、線路200與第二接地接點202。 In this embodiment, the load-bearing structure 20 is a line structure having a core layer or a coreless core line structure, and has a plurality of circuit layers (not shown, referring to the circuit layer 100 of FIG. 1), for example The core substrate, the coreless substrate, or a fan-out type redistribution layer (RDL), and the circuit layer includes the first ground contacts 201 on the surface 20a of the load-bearing structure 20 Line 200 and second ground contact 202.
再者,該承載結構20用以層間隔離線路層之材質係為如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)等之介電材。應可理解地,該承載結構20亦可為其它承載晶片之承載件,如有機板材、晶圓(wafer)、或其他具有金屬佈線(routing)之載板,並不限於上述。 Furthermore, the material of the load-bearing structure 20 for the interlayer isolation circuit layer is, for example, polybenzoxazole (PBO), polyimide (PI), prepreg (prepreg, PP for short). ) such as dielectric materials. It should be understood that the carrying structure 20 may also be other carrier supporting the wafer, such as an organic board, a wafer, or other carrier board having a metal routing, and is not limited to the above.
又,該第一接地區域A之分佈面積(第2B圖之假想線所圍繞之ㄩ字形面積)大於該第二接地區域B之分佈面積(第2B圖之假想線所圍繞之長方形面積)。應可理解地,該第一接地區域A之分佈面積亦可等於該第二接地區域B之分佈面積。 Moreover, the distribution area of the first grounding area A (the U-shaped area surrounded by the imaginary line of FIG. 2B) is larger than the distribution area of the second grounding area B (the rectangular area surrounded by the imaginary line of FIG. 2B). It should be understood that the distribution area of the first grounding area A may also be equal to the distribution area of the second grounding area B.
另外,該線路200係包含有導電跡線200a及分別位於該導電跡線200a兩端之訊號接點200b與電性端點200c。 In addition, the circuit 200 includes a conductive trace 200a and a signal contact 200b and an electrical terminal 200c respectively located at opposite ends of the conductive trace 200a.
所述之電子元件24係設於該承載結構20上並具有複數(如圖所示之三個)用以電性連接第一及/或第二接地接點201,202之銲墊240及複數(如圖所示之三個)用以電性連接該線路200之電極墊241。 The electronic component 24 is disposed on the carrying structure 20 and has a plurality of (three as shown) for electrically connecting the solder pads 240 of the first and/or second ground contacts 201, 202 and a plurality (such as The three shown in the figure are used to electrically connect the electrode pads 241 of the line 200.
於本實施例中,該電子元件24係為主動元件、被動元件或其組合等,其中,該主動元件係例如半導體晶片,且該被動元件係例如電阻、電容及電感。 In this embodiment, the electronic component 24 is an active component, a passive component or a combination thereof, etc., wherein the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor.
再者,該銲墊240係為該電子元件24之接地墊,且該電極墊241係為該電子元件24之訊號墊。 Furthermore, the pad 240 is a ground pad of the electronic component 24, and the electrode pad 241 is a signal pad of the electronic component 24.
又,該電子元件24之電極墊241係藉由複數第三導電元件23電性連接該些訊號接點200b,其中,該第三導電元件23係為銲線。 Moreover, the electrode pads 241 of the electronic component 24 are electrically connected to the signal contacts 200b by a plurality of third conductive elements 23, wherein the third conductive elements 23 are solder wires.
另外,如第2C圖所示,該銲墊240、該第一接地接點201與該第二接地接點202係排列於同一直線(如第2C圖所示之虛線C)上,且該訊號接點200b與該電極墊241係位於同一直線(如第2C圖所示之虛線D)上。 In addition, as shown in FIG. 2C, the pad 240, the first ground contact 201, and the second ground contact 202 are arranged on the same straight line (as shown by the broken line C in FIG. 2C), and the signal is The contact 200b and the electrode pad 241 are in the same straight line (as shown by the broken line D shown in FIG. 2C).
所述之第一導電元件21係為銲線,其接觸及電性連接該銲墊240與該第一接地接點201。 The first conductive element 21 is a bonding wire that is in contact with and electrically connected to the pad 240 and the first ground contact 201.
所述之第二導電元件22係為銲線,其接觸及電性連接該第一接地接點201與該第二接地接點202。 The second conductive element 22 is a bonding wire that is in contact with and electrically connected to the first ground contact 201 and the second ground contact 202.
於本實施例中,該第一導電元件21之長度r與該第二導電元件22之長度t係小於該第三導電元件23之長度L。 In this embodiment, the length r of the first conductive element 21 and the length t of the second conductive element 22 are smaller than the length L of the third conductive element 23.
另外,於另一實施例中,如第3圖所示,該電子元件24之銲墊240亦可藉由如銲線之第四導電元件54直接電性連接該第二接地接點202,而無需經由該第一接地接點201進行跳線;或者,如第3圖所示,該電子元件24之銲墊240亦可僅藉由如銲線之第一導電元件51電性連接該第一接地接點201,而不再跳接至該第二接地接點202。 In addition, in another embodiment, as shown in FIG. 3, the solder pad 240 of the electronic component 24 can be directly electrically connected to the second ground contact 202 by a fourth conductive component 54 such as a bonding wire. The soldering pad 240 of the electronic component 24 can be electrically connected to the first conductive component 51 only by the first conductive component 51, such as the bonding wire, as shown in FIG. The ground contact 201 is not jumped to the second ground contact 202.
所述之封裝層25係形成於該承載結構20之表面20a上,以包覆該電子元件24、該第一導電元件21、該第二導電元件22與該第三導電元件23。 The encapsulation layer 25 is formed on the surface 20a of the carrier structure 20 to cover the electronic component 24, the first conductive component 21, the second conductive component 22 and the third conductive component 23.
於本實施例中,該封裝層25係為絕緣材,如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy) 或封裝材(molding compound),其可用壓合(lamination)或模壓(molding)之方式形成於該承載結構20之表面20a上。然而,有關該封裝層25之材質及製作方式並不限於上述。 In this embodiment, the encapsulation layer 25 is an insulating material, such as polyimide (PI), dry film, epoxy or molding compound, which is available. A lamination or molding is formed on the surface 20a of the load-bearing structure 20. However, the material and manufacturing method of the encapsulating layer 25 are not limited to the above.
因此,本發明之電子封裝件2係藉由該承載結構20定義有第一接地區域A與第二接地區域B,使該電子元件24可選擇性電性連接該第一及/或第二接地接點201,202,故相較於習知技術,當該電子元件24之功能增多而使通過該電子元件24之電流增加時,可將該電子元件24電性連接該第一及第二接地接點201,202,以滿足該電子元件24之接地電位之需求。 Therefore, the electronic package 2 of the present invention defines a first grounding area A and a second grounding area B by the supporting structure 20, so that the electronic component 24 can be selectively electrically connected to the first and/or second grounding. The contacts 201, 202 are electrically connected to the first and second ground contacts when the current of the electronic component 24 is increased to increase the current through the electronic component 24, as compared with the prior art. 201, 202 to meet the ground potential of the electronic component 24.
再者,當該電子元件24之功能不多時,可將該電子元件24僅電性連接該第一接地接點201(或該第二接地接點202),以符合該電子元件24之較小接地電位之需求。 Moreover, when the electronic component 24 has a small function, the electronic component 24 can be electrically connected only to the first ground contact 201 (or the second ground contact 202) to conform to the electronic component 24. The need for a small ground potential.
第4A及4B圖係為本發明之電子封裝件3之再一實施例的示意圖。本實施例與前述實施例之差異僅在於該承載結構20之佈線,其它構件大致相同,故以下僅說明相異處,而不再贅述相同處。 4A and 4B are schematic views of still another embodiment of the electronic package 3 of the present invention. The difference between this embodiment and the foregoing embodiment is only the wiring of the load-bearing structure 20, and the other components are substantially the same, so only the differences will be described below, and the same points will not be described again.
如第4A及4B圖所示,該承載結構20係於該第一接地區域A與該第二接地區域B之間形成有一訊號線300。 As shown in FIGS. 4A and 4B, the load-bearing structure 20 is formed with a signal line 300 between the first ground area A and the second ground area B.
於本實施例中,該訊號線300係藉由該承載結構20內之線路層電性連接該線路200,以令該電子元件24藉由打線至該訊號接點200b以電性導通至該訊號線300,提升線路佈局靈活度。 In the present embodiment, the signal line 300 is electrically connected to the line 200 by the circuit layer in the carrying structure 20, so that the electronic component 24 is electrically connected to the signal contact 200b to electrically connect to the signal. Line 300 improves the flexibility of the line layout.
綜上所述,本發明之電子封裝件,係藉由該承載結構定義有第一接地區域與第二接地區域,使該電子元件可依其功能規格選擇性電性連接該第一及/或第二接地接點,以滿足該電子元件所需之較大或較小的接地電位,故能提升該電子封裝件之實用性。 In summary, the electronic package of the present invention defines a first grounding area and a second grounding area by the supporting structure, so that the electronic component can be selectively electrically connected to the first and/or according to its functional specifications. The second ground contact can meet the larger or smaller ground potential required for the electronic component, thereby improving the utility of the electronic package.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
Claims (14)
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| JP2006140202A (en) * | 2004-11-10 | 2006-06-01 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| TW200830484A (en) * | 2007-01-04 | 2008-07-16 | Chipmos Technologies Bermuda | Chip package structure |
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