[go: up one dir, main page]

TW201903987A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TW201903987A
TW201903987A TW107110699A TW107110699A TW201903987A TW 201903987 A TW201903987 A TW 201903987A TW 107110699 A TW107110699 A TW 107110699A TW 107110699 A TW107110699 A TW 107110699A TW 201903987 A TW201903987 A TW 201903987A
Authority
TW
Taiwan
Prior art keywords
printed circuit
circuit board
semiconductor device
holes
resin
Prior art date
Application number
TW107110699A
Other languages
English (en)
Other versions
TWI672773B (zh
Inventor
一法師大
奥村紀彦
Original Assignee
日商三菱電機股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商三菱電機股份有限公司 filed Critical 日商三菱電機股份有限公司
Publication of TW201903987A publication Critical patent/TW201903987A/zh
Application granted granted Critical
Publication of TWI672773B publication Critical patent/TWI672773B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142Sealing arrangements between parts, e.g. adhesion promotors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894Materials of the insulating layers or coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00012Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

半導體裝置(20)具備:沿著外周(2e)以基板厚度之4倍以下的間隔形成有複數個貫通孔(4)且安裝有屬於電阻、電容器、積體電路、光耦合器等電路零件的零件(3)之印刷電路基板(2),與印刷電路基板(2)電連接之屬於電力用半導體元件之功率元件(7),以及封裝印刷電路基板(2)及功率元件(7)之封裝樹脂(10);印刷電路基板(2)為外周具有凸部之外形形狀,於凸部形成有貫通孔(4),於複數個貫通孔(4)中填充有封裝樹脂(10)。

Description

半導體裝置
本發明係關於藉由樹脂材料將半導體元件與印刷電路基板模製封裝之半導體裝置。
以往已知,藉由樹脂材料將半導體元件與印刷電路基板模製封裝之半導體裝置中,由於以樹脂封裝後的熱收縮或冷熱環境下的熱應力,於印刷電路基板與封裝樹脂材料之界面上產生應力,可能會引起界面剝離。當界面剝離蔓延至印刷電路基板的零件安裝位置時,可能成為焊料接合部產生龜裂,零件剝離或產生斷線之缺失的原因。
專利文獻1中,揭示一種於印刷電路基板的四個角落設置貫通孔,並藉由設置在貫通孔之樹脂的定錨效果來抑制印刷電路基板與封裝樹脂材料之界面剝離之內容。
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開2012-256803號公報
然而,專利文獻1所揭示之發明中,無法抑制從無貫通孔之各邊的中央部所產生之界面剝離,而使剝離蔓延至電路內。
本發明係鑑於上述情形而研創者,其目的在於得到可抑制印刷電路基板之各邊的中央部上之印刷電路基板與封裝樹脂材料之界面剝離的產生及蔓延之半導體裝置。
為了解決上述課題以達成目的,本發明係具備:沿著外周以基板厚度之4倍以下的間隔形成有複數個貫通孔之印刷電路基板,以及與印刷電路基板電連接之半導體元件。本發明具備封裝印刷電路基板及半導體元件之封裝樹脂,印刷電路基板為外周具有凸部之外形形狀,於凸部形成有貫通孔,於複數個貫通孔中填充有封裝樹脂。
本發明之半導體裝置具有可抑制印刷電路基板之各邊的中央部上之印刷電路基板與封裝樹脂材料之界面剝離的產生及蔓延之效果。
1‧‧‧導線架
2‧‧‧印刷電路基板
2a‧‧‧凸部
2e‧‧‧外周
3‧‧‧零件
4‧‧‧貫通孔
4a‧‧‧緣
5‧‧‧焊墊
6‧‧‧金屬線
7‧‧‧功率元件
8‧‧‧絕緣薄片
9‧‧‧金屬基底
10‧‧‧封裝樹脂
20‧‧‧半導體裝置
F‧‧‧從印刷電路基板2的外周2e之距離
t‧‧‧基板厚度
第1圖為本發明的實施形態1之半導體裝置之剖面示意圖。
第2圖為實施形態1之半導體裝置之俯視圖。
第3圖為顯示實施形態1之半導體裝置之設置在印刷電路基板之貫通孔的間隔與界面剝離的剝離長度之關係之圖。
第4圖為用以顯示實施形態1之半導體裝置的印刷電路基板與封裝樹脂之界面剝離的剝離長度之定義之俯視圖。
第5圖為本發明的實施形態2之半導體裝置之俯視圖。
以下係根據圖式來詳細說明本發明的實施形態之半導體裝置。惟本發明並不限定於此實施形態。
實施形態1.
第1圖為本發明的實施形態1之半導體裝置之剖面示意圖。第2圖為實施形態1之半導體裝置之俯視圖。半導體裝置20係藉由封裝樹脂10來模製封裝安裝有屬於電阻、電容器、積體電路、光耦合器等電路零件的零件3之印刷電路基板2,以及屬於電力用半導體元件之功率元件7。功率元件7可例示出絕緣閘雙極性電晶體及二極體,但不限定於此等。功率元件7裝載於導線架1的表面,並經由金屬線6連接於印刷電路基板2的焊墊5。裝載有功率元件7之導線架1,於與裝載有功率元件7之面為相反側的面之背面上,隔著絕緣薄片8配置有金屬基底9。金屬 基底9暴露於封裝樹脂10的外部,而將功率元件7所產生之熱,隔著絕緣薄片8及金屬基底9而往半導體裝置20的外部散熱。
於印刷電路基板2,沿著外周2e以基板厚度t之4倍以下的間隔L形成有複數個貫通孔4。亦即,於印刷電路基板2的外周部,以基板厚度t之4倍以下的間隔L形成有複數個貫通孔4。貫通孔4的間隔L為相鄰之貫通孔4的中心間距離。貫通孔4係形成於離印刷電路基板2的外周2e之距離F為基板厚度t的2倍以下之位置上。配置在印刷電路基板2之零件3以及印刷電路基板2之表面或內部的配線圖案,係配置在由貫通孔4所包圍之區域內。由於配線圖案是為了屬於電路零件之零件3的電連接而形成,所以零件3被配置在形成有配線圖案之區域。於貫通孔4中填充有封裝樹脂10,並藉由填充於貫通孔4之封裝樹脂10的定錨效果,來抑制印刷電路基板2與封裝樹脂10之界面剝離。
第3圖為顯示實施形態1之半導體裝置之設置在印刷電路基板之貫通孔的間隔L與界面剝離的剝離長度d之關係之圖。第3圖中的界面剝離,是將半導體裝置20加熱及冷卻,因熱應力而在印刷電路基板2與封裝樹脂10之間產生。
第4圖為用以顯示實施形態1之半導體裝置的印刷電路基板與封裝樹脂之界面剝離的剝離長度之定義之俯視圖。如第4圖所示,所謂界面剝離的剝離長度d, 為在與貫通孔4的排列配置方向正交之方向且遠離印刷電路基板2的外周2e之方向,亦即從貫通孔4朝向印刷電路基板2的中心側之方向界面剝離最為蔓延之位置,與和印刷電路基板2的外周2e成為相反側之貫通孔4的緣4a之距離。亦即,剝離長度d係界面剝離以貫通孔4為起點往印刷電路基板2的中心側蔓延之距離。第4圖中,所謂與貫通孔4的排列配置方向正交之方向且遠離印刷電路基板2的外周2e之方向,為以箭頭A所示之方向。
如第3圖所示,若貫通孔的間隔L為印刷電路基板2之基板厚度t的4倍以下,則界面剝離的剝離長度為0.1mm以下,即使產生界面剝離,亦可抑制該蔓延。
於半導體裝置20的驅動時,由於功率元件7發熱,所以半導體裝置20的溫度上升。而且,半導體裝置20之溫度變化的原因,亦可列舉出於製造時將封裝樹脂10模製硬化時之溫度。
印刷電路基板2與封裝樹脂10之界面剝離,係起因於由印刷電路基板2的基材與封裝樹脂10之線膨脹差所造成之應力而產生,由於由線膨脹差所造成之應力在印刷電路基板2的外周2e上較大,所以將貫通孔4配置在離印刷電路基板2的外周2e為基板厚度t的2倍以下之區域,並將零件3配置在貫通孔4的內側。藉由將貫通孔4配置在印刷電路基板2的外周2e附近,可抑制在印刷電路基板2的外周2e上所產生之界面剝離。再者,即使產生界面剝離,亦可藉由貫通孔4,於印刷電路基板2的 外周2e附近阻止界面剝離的蔓延。
為了將封裝樹脂10確實地填充於貫通孔4,在貫通孔4的上部及從封裝樹脂10的模製所使用之模具的樹脂注入口至貫通孔4為止之間,不配置會妨礙封裝樹脂10的注入之零件3為較佳。
用以封裝功率元件7及印刷電路基板2之封裝樹脂10,可選擇環氧樹脂系模製樹脂。封裝樹脂10中,可含有二氧化矽或氧化鋁之無機填充劑。填充劑的平均粒徑,一般為數μm至數十μm,為了將封裝樹脂10確實地填充於貫通孔4,將貫通孔4的口徑設為填充劑的平均粒徑之10倍以上為較佳。
印刷電路基板2與封裝樹脂10之間之應力的因素之線膨脹,由於會受到玻璃轉移溫度的影響,藉由將印刷電路基板2的基材與封裝樹脂10之玻璃轉移溫度差設為30℃以下,即可縮小應力而抑制界面剝離。
如上述般,根據實施形態1之半導體裝置20,可抑制印刷電路基板2與封裝樹脂10之界面剝離的產生及蔓延,而提高可靠度。
實施形態1中,貫通孔4係形成於印刷電路基板2的外周全體,但若形成於容易產生剝離之處,則亦可不形成於外周全體。
實施形態2.
第5圖為本發明的實施形態2之半導體裝置之俯視 圖。實施形態2之半導體裝置20中,印刷電路基板2並非矩形狀,而是具有往面內方向突出之凸部2a之外形,此點係與實施形態1之半導體裝置20不同。實施形態2中,係將貫通孔4形成於凸部2a。除此之外,其他與實施形態1相同。
於具有凸部2a之外形形狀的印刷電路基板2中,印刷電路基板2與封裝樹脂10之界面剝離,會在應力容易集中之凸部2a上產生。因此,較佳係盡可能在離印刷電路基板2的外周2e之距離F較短之處,將貫通孔4形成於凸部2a。
實施形態2之半導體裝置20,可抑制具有凸部2a之外形形狀的印刷電路基板2與封裝樹脂10之界面剝離的產生及蔓延,而提高可靠度。
上述實施形態1、2中,已說明藉由封裝樹脂10將印刷電路基板2與電力用半導體元件之功率元件7一齊封裝之構造,但藉由封裝樹脂10而與印刷電路基板2一齊封裝者,並不限定於電力用半導體元件。
以上實施形態所示之構成,僅顯示本發明之內容的一例,亦可與其他一般所知的技術組合,且在不脫離本發明的主旨之範圍內,亦可省略或變更構成的一部分。

Claims (6)

  1. 一種半導體裝置,具備:沿著外周以基板厚度之4倍以下的間隔形成有複數個貫通孔之印刷電路基板,與該印刷電路基板電連接之半導體元件,以及封裝前述印刷電路基板及前述半導體元件之封裝樹脂;前述印刷電路基板為外周具有凸部之外形形狀,於該凸部形成有前述貫通孔,於複數個前述貫通孔中填充有前述封裝樹脂。
  2. 如申請專利範圍第1項所述之半導體裝置,其中複數個前述貫通孔係形成於從前述印刷電路基板的外周距離基板厚度之2倍以下的位置上。
  3. 如申請專利範圍第1項所述之半導體裝置,其中前述印刷電路基板僅在由複數個前述貫通孔所包圍之區域內形成有配線圖案。
  4. 如申請專利範圍第1項所述之半導體裝置,其中前述印刷電路基板之基材的玻璃轉移溫度與前述封裝樹脂的玻璃轉移溫度之差為30℃以內。
  5. 如申請專利範圍第2項所述之半導體裝置,其中前述印刷電路基板之基材的玻璃轉移溫度與前述封裝樹脂的玻璃轉移溫度之差為30℃以內。
  6. 如申請專利範圍第1至5項中任一項所述之半導體裝置,其中前述封裝樹脂含有屬於無機材料粒子之填充 劑,前述貫通孔的口徑為前述填充劑的平均粒徑之10倍以上。
TW107110699A 2017-04-21 2018-03-28 半導體裝置 TWI672773B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/JP2017/016015 WO2018193614A1 (ja) 2017-04-21 2017-04-21 半導体装置
WOPCT/JP2017/016015 2017-04-21

Publications (2)

Publication Number Publication Date
TW201903987A true TW201903987A (zh) 2019-01-16
TWI672773B TWI672773B (zh) 2019-09-21

Family

ID=61756590

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107110699A TWI672773B (zh) 2017-04-21 2018-03-28 半導體裝置

Country Status (6)

Country Link
US (1) US10615093B2 (zh)
JP (1) JP6301031B1 (zh)
CN (1) CN109104878B (zh)
DE (1) DE112017000347B4 (zh)
TW (1) TWI672773B (zh)
WO (1) WO2018193614A1 (zh)

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03205857A (ja) * 1990-01-06 1991-09-09 Fujitsu Ltd 樹脂封止型電子部品
US5264730A (en) 1990-01-06 1993-11-23 Fujitsu Limited Resin mold package structure of integrated circuit
JPH06224325A (ja) 1993-01-26 1994-08-12 Matsushita Electric Works Ltd 半導体装置
DE10162676B4 (de) 2001-12-19 2005-06-02 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip und einer Umverdrahtungsplatte und Systemträger für mehrere elektronische Bauteile sowie Verfahren zur Herstellung derselben
JP2008205308A (ja) * 2007-02-21 2008-09-04 Sanyo Electric Co Ltd 半導体装置
JP5482791B2 (ja) * 2009-07-27 2014-05-07 株式会社豊田自動織機 配線基板および配線基板の製造方法
KR101678052B1 (ko) * 2010-02-25 2016-11-22 삼성전자 주식회사 단층 배선 패턴을 포함한 인쇄회로기판(pcb), pcb를 포함한 반도체 패키지, 반도체 패키지를 포함한 전기전자장치, pcb제조방법, 및 반도체 패키지 제조방법
TW201250950A (en) 2011-05-19 2012-12-16 Sumitomo Bakelite Co A semiconductor module component and a liquid sealing resin composition
JP5518000B2 (ja) 2011-06-10 2014-06-11 三菱電機株式会社 パワーモジュールとその製造方法
WO2013140704A1 (ja) * 2012-03-21 2013-09-26 富士電機株式会社 電力変換装置
JP5930070B2 (ja) * 2012-12-28 2016-06-08 富士電機株式会社 半導体装置
WO2015151235A1 (ja) * 2014-04-01 2015-10-08 富士電機株式会社 半導体装置
JP2017022346A (ja) * 2015-07-15 2017-01-26 富士電機株式会社 半導体装置及び半導体装置の製造方法
US10368448B2 (en) * 2017-11-11 2019-07-30 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method of manufacturing a component carrier

Also Published As

Publication number Publication date
JPWO2018193614A1 (ja) 2019-06-27
WO2018193614A1 (ja) 2018-10-25
US20190393115A1 (en) 2019-12-26
CN109104878A (zh) 2018-12-28
US10615093B2 (en) 2020-04-07
CN109104878B (zh) 2020-01-21
TWI672773B (zh) 2019-09-21
DE112017000347T5 (de) 2018-12-06
JP6301031B1 (ja) 2018-03-28
DE112017000347B4 (de) 2021-08-05

Similar Documents

Publication Publication Date Title
US9570405B2 (en) Semiconductor device and method for manufacturing same
US8018072B1 (en) Semiconductor package having a heat spreader with an exposed exterion surface and a top mold gate
US8441120B1 (en) Heat spreader package
TWI614849B (zh) 封裝結構
TW201537719A (zh) 堆疊型半導體封裝
JP7247574B2 (ja) 半導体装置
CN205789929U (zh) 装备有散热器的电子设备
US20160247775A1 (en) Chip packaging strcutre and manufaturing method thereof
US10096578B1 (en) Semiconductor package device and method of manufacturing the same
KR102228461B1 (ko) 반도체 패키지 장치
US20230069969A1 (en) Package for several integrated circuits
US10964627B2 (en) Integrated electronic device having a dissipative package, in particular dual side cooling package
JP5195282B2 (ja) 半導体装置およびその製造方法
JP2014187264A (ja) 半導体装置
TWI843813B (zh) 半導體裝置
TWI672773B (zh) 半導體裝置
JP2014216326A (ja) 電子装置およびその製造方法
CN108682631B (zh) 一种led发光面板及其制造方法
US9355999B2 (en) Semiconductor device
CN107749408A (zh) 一种弹性导热件露出封装结构
KR20000073112A (ko) 내장형 히트 슬러그
JP7178978B2 (ja) 半導体装置および半導体装置の製造方法
JP2009021366A (ja) 半導体装置
KR100459820B1 (ko) 칩스케일패키지및그제조방법
KR100924543B1 (ko) 반도체 패키지의 제조 방법

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees