TW201809818A - Display device - Google Patents

Abstract

This disclosure relates to a display device, including: a substrate; a gate insulating layer provided on the substrate; a first active layer provided on the gate insulating layer, wherein the first active layer is a polycrystalline silicon layer; a first An insulating layer is provided on the first active layer and the gate insulating layer; a second active layer is provided on the first insulating layer, wherein the second active layer is a metal oxide layer; a first source electrode, a first A drain, a second source, and a second drain, wherein the first source and the first drain are disposed on the first insulating layer and are electrically connected to the first active layer through a plurality of through holes; and The second source electrode and the second drain electrode are disposed on the second active layer and electrically connected to the second active layer; and a display medium is located on the substrate.

Description

Display device

The main purpose of this disclosure is to provide a display device, particularly a display device including both a low temperature polycrystalline silicon thin film transistor unit and a metal oxide thin film transistor unit.

With the continuous advancement of display technology, all display panels are trending towards small size, thin thickness, and light weight. Therefore, the mainstream display devices on the market have developed from the previous cathode ray tubes to thin displays, such as liquid crystal display panels, An organic light emitting diode display panel, an inorganic light emitting diode display panel, and the like. Among them, there are quite a few applications for thin displays. For example, most display panels such as mobile phones, notebook computers, video cameras, cameras, music players, mobile navigation devices, and televisions are used in daily life.

Although liquid crystal display devices or organic light emitting diode display devices have become common display devices on the market, especially the technology of liquid crystal display devices is quite mature, but with the continuous development of display devices and consumers' requirements for display quality of display devices Increasingly, manufacturers are all striving to develop display devices with higher display quality. Among them, in addition to the thin film transistor structure on the display area, the thin film transistor element structure used in the gate driving circuit area in the non-display area is also one of the factors affecting the overall efficiency of the display device.

If both the display area and the gate drive circuit area use thin-film transistor elements, if the two are different thin-film transistor elements, the manufacturing processes of the two will affect each other and will also complicate the overall manufacturing process of the display device (for example: Multiple chemical vapor deposition processes). In view of this, the display area still needs to be targeted And the structure of the thin film transistor element in the gate driving circuit area is improved to simplify the process and structure of the two under the good characteristics of the thin film transistor element.

The main purpose of this disclosure is to provide a display device, which includes both a low temperature polycrystalline silicon thin film transistor unit and a metal oxide thin film transistor unit.

In one embodiment of the present disclosure, the display device may include: a substrate; a first gate and a second gate provided on the substrate; and a gate insulating layer provided on the substrate and the first A gate and the second gate; a first active layer disposed on the gate insulating layer and corresponding to the first gate, wherein the first active layer includes a polycrystalline silicon layer; a first insulating layer, provided On the first active layer and the gate insulating layer; a second active layer disposed on the first insulating layer and corresponding to the second gate, wherein the second active layer includes a metal oxide layer; A first source, a first drain, a second source, and a second drain, wherein the first source and the first drain are disposed on the first insulating layer and pass through a plurality of through holes; To be electrically connected to the first active layer, and the second source electrode and the second drain electrode are disposed on the second active layer and electrically connected to the second active layer; wherein the first gate electrode, The gate insulating layer, the first active layer, the first insulating layer, the first source and the first drain constitute a first thin film transistor unit. And the second gate, the gate insulating layer, the first insulating layer, the second active layer, the second source and the second drain constitute a second thin film transistor unit; and a display medium, Located on the substrate.

In another embodiment of the present disclosure, the display device may have a substrate; a first gate electrode disposed on the substrate; a gate insulation layer disposed on the substrate and the first gate electrode; a first active Layer on the gate insulating layer and corresponding to the first gate, wherein the first active layer includes a polycrystalline silicon layer; a second gate on the gate insulating layer; a first insulating layer Is disposed on the first active layer and the second gate; a second active layer is disposed on the first insulating layer and corresponds to the second gate, wherein the second active layer includes a metal oxide layer ; A first source, a first drain, a second source And a second drain electrode, wherein the first source electrode and the first drain electrode are disposed on the first insulation layer and are electrically connected to the first active layer through a plurality of through holes, and the second source electrode And the second drain electrode is disposed on the second active layer and is electrically connected to the second active layer; wherein the first gate electrode, the gate insulation layer, the first active layer, and the first insulation layer , The first source electrode and the first drain electrode constitute a first thin film transistor unit, and the second gate electrode, the first insulation layer, the second active layer, the second source electrode, and the second drain electrode The electrodes constitute a second thin film transistor unit; and a display medium is located on the substrate.

It can be known from the foregoing that the display device of the present disclosure includes a first thin film transistor unit with a first active layer being a polycrystalline silicon layer and a second thin film transistor unit with a second active layer being a metal oxide layer. In particular, by adjusting the relationship between the first and second active layers, the gate insulating layer, and the layers and layers of the first insulating layer, the structure of the components on the substrate can be simplified, and the formation of the first and second thin-film electrical layers can be simplified. The manufacturing process of the crystal unit; meanwhile, the obtained first and second thin film transistor units can still maintain good characteristics of the thin film transistor unit.

1‧‧‧ the first substrate

11‧‧‧ substrate

121‧‧‧first gate

122,122’‧‧‧Second gate

123‧‧‧first conductive layer

124‧‧‧Second conductive layer

125‧‧‧scan line

125a‧‧‧through hole

13‧‧‧Gate insulation

131‧‧‧ bottom gate insulation

132‧‧‧Top gate insulation

14‧‧‧amorphous silicon layer

14’‧‧‧polycrystalline silicon layer

141‧‧‧Source area

142‧‧‧Drain

143‧‧‧Channel area

145‧‧‧amorphous silicon layer

146‧‧‧ doped amorphous silicon layer

15‧‧‧first insulating layer

151‧‧‧The first bottom insulation layer

152‧‧‧First top insulation layer

16‧‧‧Second Active Level

171‧‧‧First source

171a, 172a‧‧‧through hole

172‧‧‧first drain

173‧‧‧Second Source

174‧‧‧Second Drain

175‧‧‧ fourth conductive layer

18‧‧‧Second insulation layer

19‧‧‧ pixel electrode

19a‧‧‧ contact hole

2‧‧‧ second substrate

21,21’22‧‧‧Mask

3‧‧‧Display Media Layer

AA‧‧‧Display Area

B‧‧‧Peripheral area

H1, H2‧‧‧Distance

TFT1‧‧‧The first thin film transistor unit

TFT2‧‧‧Second thin film transistor unit

SL‧‧‧scan line

FIG. 1A is a top view of a display device according to Embodiment 1 of the present disclosure.

FIG. 1B is a schematic cross-sectional view of a display device according to Embodiment 1 of the present disclosure.

FIG. 2A to FIG. 2G are schematic cross-sectional views illustrating a manufacturing process of components on a substrate of a display device according to Embodiment 1 of the present disclosure.

3A to 3E are schematic cross-sectional views illustrating a manufacturing process of a component on a substrate of a display device according to Embodiment 2 of the present disclosure.

4 is a schematic cross-sectional view of a display device according to a second embodiment of the disclosure.

5A to 5H are schematic cross-sectional views illustrating a manufacturing process of components on a substrate of a display device according to Embodiment 3 of the present disclosure.

FIG. 6A is a schematic cross-sectional view of a display device according to Embodiment 4 of the present disclosure.

FIG. 6B is a top view of some layers in the second thin film transistor unit of the display device of Embodiment 4 of this disclosure.

7A to 7G are schematic cross-sectional views illustrating a manufacturing process of components on a substrate of a display device according to Embodiment 5 of the present disclosure.

FIG. 8A is a schematic cross-sectional view of a display device according to Embodiment 6 of the present disclosure.

FIG. 8B is a partial top view of the second thin film transistor unit of the display device of Embodiment 6 of this disclosure.

FIG. 9 is a schematic cross-sectional view of a display device according to Embodiment 7 of the present disclosure.

FIG. 10 is a schematic cross-sectional view of a display device according to Embodiment 8 of the present disclosure.

FIG. 11 is a schematic cross-sectional view of a display device according to Embodiment 9 of the present disclosure.

The following is a description of the implementation of the disclosure through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the disclosure from the content disclosed in the description. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed for different viewpoints and applications without departing from the spirit of this creation.

Furthermore, the ordinal numbers used in the description and the request items, such as "first", "second", etc., to modify the elements of the request item do not themselves imply and represent that the request element has any previous ordinal number, It also does not represent the order of one request element and another request element, or the order of manufacturing methods. The use of these ordinal numbers is only used to enable a request element with a certain name to be able to function with another request element with the same name. Make a clear distinction.

Example 1

1A and 1B are a top view and a schematic cross-sectional view, respectively, of the display device of this embodiment. The display device of this embodiment includes: a first substrate 1; a second substrate 2 disposed opposite the first substrate 1; and a display medium layer 3 disposed between the first substrate 1 and the second substrate 2. The display device may include: a display area AA; and a peripheral area B disposed around the display area AA. Here, the so-called peripheral area B is an area where the wiring is distributed, for example, a gate driving circuit area; and the so-called display area AA is an area where the pixel units are distributed.

FIG. 2A to FIG. 2G are schematic cross-sectional views of a manufacturing process of components on a substrate of a display device of this embodiment, for example, a manufacturing process of components on a first substrate 1. First, as shown in FIG. 2A, a substrate 11 is provided, and a first gate electrode 121 and a second gate electrode 122 are formed on the substrate 11. Here, the substrate 11 is made of a base material such as glass, plastic, and a flexible material; and the first gate electrode 121 and the second gate electrode 122 may be made of a metal material such as Cu or Al. Then, a gate insulating layer 13 is formed on the substrate 11, the first gate electrode 121 and the second gate electrode 122. In this embodiment, the gate insulating layer 13 includes a bottom gate insulating layer 131 and a top gate insulating layer 132. The bottom gate insulating layer 131 is disposed between the substrate 11 and the top gate insulating layer 132, and the bottom gate The material of the electrode insulating layer 131 is silicon nitride, and the material of the top gate insulating layer 132 is silicon oxide. Next, an amorphous silicon layer 14 is formed on the gate insulating layer 13.

As shown in FIG. 2B, the amorphous silicon layer 14 can be converted into a polycrystalline silicon layer 14 'through a laser sintering process and a channel doping process. Next, as shown in FIG. 2C, the mask 21 made of a photoresist is used to pattern the polycrystalline silicon layer 14 ', and the formed polycrystalline silicon layer 14' corresponds to the first gate electrode 121. Then, as shown in FIG. 2D, another mask 21 'is used to perform the n + or p + doping process, so that the polycrystalline silicon layer 14' of FIG. 2C can be converted to include doped source regions 141, drain regions 142, and A channel region 143. The channel region 143 is located between the source region 141 and the drain region 142.

After removing the mask 21, as shown in FIG. 2E, the first active layer (the polycrystalline silicon layer 14 '(see FIG. 2C) includes the source region 141, the drain region 142, and the channel region 143) and the gate insulating layer 13 A first insulating layer 15 is formed thereon. In this embodiment, the first insulating layer 15 includes a first bottom insulating layer 151 and a first top insulating layer. Layer 152, the first bottom insulating layer 151 is provided between the gate insulating layer 13 and the first top insulating layer 152; wherein the material of the first bottom insulating layer 151 is silicon nitride, and the material of the first top insulating layer 152 is Silicon oxide. Then, a patterned second active layer 16 is formed on the first insulating layer 15 and corresponding to the second gate electrode 122. The second active layer 16 is a metal oxide layer, such as an IGZO layer.

As shown in FIG. 2F, the first active layer (the polycrystalline silicon layer 14 '(see FIG. 2C) includes a source region 141, a drain region 142, and a channel region 143), a first insulating layer 15 and a second active layer 16 A first source electrode 171, a first drain electrode 172, a second source electrode 173, and a second drain electrode 174 are formed on the first source electrode 171, the first source electrode 172, the second source electrode 173, and the first source electrode 171. The material of the second drain electrode 174 may be, for example, Cu or Al. The first source electrode 171 and the first drain electrode 172 are disposed on the first insulating layer 15 and pass through the vias 171a and 172a, respectively, to contact the source region 141 and the drain region 142 of the polycrystalline silicon layer 14 '(see FIG. 2C). The second source electrode 173 and the second drain electrode 174 are disposed on the second active layer 16 and electrically connected to the second active layer 16.

2G, a second insulating layer 18 is formed on the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174, and then formed on the second insulating layer 18. A pixel electrode 19 is electrically connected to the second drain electrode 174 through a contact hole 19a. Here, the second insulating layer 18 may have a single-layer structure composed of silicon oxide, or a double-layer structure with silicon oxide in the lower layer and silicon nitride in the upper layer, or an organic material layer may be laminated outside the double-layer structure. Its multilayer structure. In addition, as the material of the pixel electrode 19, a transparent conductive oxide such as ITO, IZO, or the like can be used.

Through the aforementioned process, the device fabrication on the substrate 11 is completed. As shown in FIG. 2G, the display device of this embodiment includes: a substrate 11; a first gate electrode 121 and a second gate electrode 122 provided on the substrate 11; and a gate insulating layer 13 provided on the substrate 11, On the first gate electrode 121 and the second gate electrode 122; a first active layer (polycrystalline silicon layer 14 '(refer to FIG. 2C) including a source region 141, a drain region 142, and a channel region 143) is provided at the gate insulation Layer 13 and corresponding to the first gate electrode 121; a first insulating layer 15 provided on the first active layer and the gate insulating layer 13; a second active layer 16 provided on the first insulating layer 15 and The second gate electrode 122 corresponds, wherein the second active layer 16 is a metal oxide layer (in this embodiment, an IGZO layer); and The first source electrode 171, a first drain electrode 172, a second source electrode 173, and a second drain electrode 174. The first source electrode 171 and the first drain electrode 172 are disposed on the first insulating layer 15 and pass through. The vias 171 a and 172 a are electrically connected to the source region 141 and the drain region 142 of the first active layer, and the second source electrode 173 and the second drain electrode 174 are disposed on the second active layer 16 and are in communication with the second active layer 16. Layer 16 is electrically connected; wherein the first gate electrode 121, the gate insulating layer 13, the first active layer 14 ', the first insulating layer 15, the first source electrode 171, and the first drain electrode 172 constitute a first thin film The crystal unit TFT1, and the second gate electrode 122, the gate insulating layer 13, the first insulating layer 15, the second active layer 16, the second source electrode 173, and the second drain electrode 174 constitute a second thin film transistor unit TFT2.

In this embodiment, the display device includes a first thin film transistor unit TFT1 with a first active layer being a polycrystalline silicon layer and a second thin film transistor unit TFT2 with a second active layer 16 being a metal oxide layer. In particular, in this embodiment, by adjusting the layer-to-layer relationship between the first active layer and the second active layer 16 and the gate insulating layer 13 and the first insulating layer 15, the process steps can be reduced, and low temperature formation can be avoided. The processes of the polycrystalline silicon thin film transistor unit (ie, the first thin film transistor unit TFT1) and the metal oxide (eg, IGZO) thin film transistor unit (ie, the second thin film transistor unit TFT2) affect each other. At the same time, in the obtained display device, the element structure on the substrate 11 can be further simplified.

Further, the second gate electrode 122 and the second active layer 16 of the metal oxide thin film transistor unit TFT2 have a relatively thick insulating layer thickness, that is, the first gate electrode of the first thin film transistor unit TFT1 and the first The distance H1 between the active layers (polycrystalline silicon layer 14 ′, see FIG. 2C) is smaller than the distance H2 between the second gate electrode 122 of the second thin film transistor unit TFT2 and the second active layer 16.

In addition, since the first thin-film transistor unit TFT1 and the second thin-film transistor unit TFT2 are both thin-film transistor units with a bottom gate structure, an additional light-shielding layer may not be required on the substrate 11, thereby reducing process steps and simplifying components. structure.

In particular, in the display device of this embodiment, as shown in FIG. 2G, the gate insulating layer 13 includes a bottom gate insulating layer 131 and a top gate insulating layer 132, and the bottom gate insulating layer 131 is disposed on the substrate 11. And the top gate insulation layer 132, and the material of the bottom gate insulation layer 131 is silicon nitride, and the top gate insulation layer The material of 132 is silicon oxide. In addition, the first insulating layer 15 includes a first bottom insulating layer 151 and a first top insulating layer 152. The first bottom insulating layer 151 is disposed between the gate insulating layer 13 and the first top insulating layer 152, and the first bottom The material of the insulating layer 151 is silicon nitride, and the material of the first top insulating layer 152 is silicon oxide. Therefore, in the display device of this embodiment, a first active layer (polycrystalline silicon layer 14 '(refer to FIG. 2C)) formed of a polycrystalline silicon material includes a source region 141, a drain region 142, and a channel region 143 above it. Covered by the first bottom insulating layer 151 formed of silicon nitride, the element characteristics of the low-temperature polycrystalline silicon thin film transistor unit can be maintained; and the second active layer 16 formed of an oxide metal (eg, IGZO) layer is provided on the On the first top insulating layer 152 formed of silicon oxide, the element characteristics of the metal oxide thin film transistor unit can be maintained.

In addition, as shown in FIG. 1A, FIG. 1B, and FIG. 2G, in the display device of this embodiment, the first thin-film transistor unit TFT1 is disposed in the peripheral region B as a line switch; and the second thin-film transistor unit The TFT 2 is provided in the display area AA, and is used as a pixel electrode 19 for switching.

Example 2

In Embodiment 1, as shown in FIG. 2G, the materials of the first gate electrode 121 and the second gate electrode 122 are the same, and may be Cu or Al. The structure of the display device of this embodiment is similar to that of Embodiment 1, except that the structures and materials of the first gate electrode 121 and the second gate electrode 122 are different.

3A to 3E are schematic cross-sectional views of a manufacturing process of a first gate and a second gate on a substrate of a display device of this embodiment. First, as shown in FIG. 3A, a substrate 11 is provided, and a first conductive layer 123 and a second conductive layer 124 are sequentially formed on the substrate 11. Then, for example, a half tone mask is used to form a first mask 21 made of a photoresist in a region where the first thin-film transistor unit TFT1 is to be formed, and a second thin-film transistor unit TFT2 is to be formed at a region to be formed. The area forms a second mask 22 made of a photoresist. Next, as shown in FIG. 3B, the first conductive layer 123 and the second conductive layer 124 are etched; the masks 21 and 22 are ashed, as shown in FIG. 3C; and the first film is formed to be removed by etching. The second conductive layer 124 in the region of the transistor unit TFT1 is shown in FIG. 3D. Finally, the mask 22 is removed to complete the first gate electrode 121 and the second gate electrode 122 in this embodiment.

After the first gate electrode 121 and the second gate electrode 122 are formed, the manufacturing process of the thin film transistor unit is similar to that of the first embodiment (as shown in FIG. 2A to FIG. 2G), so it will not be repeated here.

After the foregoing process, the display device of this embodiment can be obtained. As shown in FIG. 4, the display device of this embodiment is different from Embodiment 1 in that in this embodiment, the first gate electrode 121 is formed by a first conductive layer 123 and the second gate electrode 122 is formed by The first conductive layer 123 and a second conductive layer 124 are sequentially stacked on the substrate 11, and the second conductive layer 124 completely covers the first conductive layer 123. In this embodiment, the material of the first conductive layer 123 is preferably selected from highly heat-resistant metal materials such as Ti, Cr, and Mo, or transparent conductive oxides such as ITO, IZO, and the like, so as to avoid the subsequent laser process failure of forming polycrystalline silicon. To the first gate electrode 121; and in addition to the second conductive layer 124, a high heat-resistant metal material such as Ti, Cr, Mo, or a transparent conductive oxide may be selected, and a metal material such as Cu or Al may also be selected.

Therefore, in this embodiment, since the first gate electrode 121 is made of only the first conductive layer 123, the thickness of the first gate electrode 121 can be reduced, so that the thickness of the first gate electrode 121 is smaller than that of the second gate electrode 122. thickness of. At the same time, because the first conductive layer 123 is made of a highly heat-resistant metal material or a transparent conductive oxide, the first gate electrode 121 can be prevented from being damaged by a subsequent laser process.

Example 3

The difference between the structure of the display device of this embodiment and Embodiment 1 is that the components above the substrate 11 are different. FIG. 5A to FIG. 5H are schematic cross-sectional views illustrating a manufacturing process of components on a substrate of a display device according to this embodiment. First, as shown in FIG. 5A, a substrate 11 is provided, and a first gate electrode 121 is formed on the substrate 11. Here, the substrate 11 is made of a base material such as glass, plastic, and a flexible material; and the first gate electrode 121 can be made of a highly heat-resistant metal material such as Ti, Cr, Mo, or a transparent conductive oxide. to make.

As shown in FIG. 5B, a gate insulating layer 13 is formed on the substrate 11 and the first gate 121. In this embodiment, the gate insulating layer 13 includes a bottom gate insulating layer 131 and a top gate insulating layer 132. The bottom gate insulating layer 131 is disposed between the substrate 11 and the top gate insulating layer 132, and the bottom gate The material of the electrode insulating layer 131 is Silicon nitride, and the material of the top gate insulating layer 132 is silicon oxide. Then, an amorphous silicon layer 14 is formed on the gate insulating layer 13.

As shown in FIG. 5C, the amorphous silicon layer 14 can be converted into a polycrystalline silicon layer 14 'through a laser sintering process and a channel doping process. Next, as shown in FIG. 5D, the polycrystalline silicon layer 14 'is patterned with a mask 21 made of a photoresist, so that the polycrystalline silicon layer 14' is disposed corresponding to the first gate electrode 121, and the mask 21 (which can be patterned with The mask of the polycrystalline silicon layer 14 ′ is the same, or a mask 21 is formed separately. The n + or p + doping process is performed, so that the polycrystalline silicon layer 14 ′ includes a source region 141, a drain region 142 and a channel region 143 , As shown in Figure 5D.

After the mask 21 is removed, as shown in FIG. 5E, a second gate electrode 122 is formed on the gate insulating layer 13, which can be made of a metal material such as Cu or Al. Then, a first insulating layer 15 is formed on the polycrystalline silicon layer 14 ′ (including the source region 141, the drain region 142 and the channel region 143) (see FIG. 5C) and the second gate electrode 122. In this embodiment, the first insulating layer 15 includes a first bottom insulating layer 151 and a first top insulating layer 152, and the first bottom insulating layer 151 is disposed between the gate insulating layer 13 and the first top insulating layer 152; The material of the first bottom insulating layer 151 is silicon nitride, and the material of the first top insulating layer 152 is silicon oxide. Then, a second active layer 16 is formed on the first insulating layer 15 and in a region corresponding to the second gate electrode 122. The second active layer 16 is a metal oxide layer, such as an IGZO layer.

As shown in FIG. 5G and FIG. 5H, the subsequent processes of forming the first source electrode 171, the first drain electrode 172, the second source electrode 173, the second drain electrode 174, a second insulating layer 18, and a pixel electrode 19 are all Example 1 is similar, so it will not be described in detail here.

Through the aforementioned process, the device fabrication on the substrate 11 is completed. As shown in FIG. 5H, the display device of this embodiment includes: a substrate 11; a first gate electrode 121 provided on the substrate 11; a gate insulating layer 13 provided on the substrate 11 and the first gate electrode 121; A first active layer (polycrystalline silicon layer including a source region 141, a drain region 142, and a channel region 143) is disposed on the gate insulating layer 13 and corresponds to the first gate electrode 121, wherein the first active layer is a polycrystalline silicon Layer; a second gate electrode 122 provided on the gate insulating layer 13; a first gate electrode The edge layer 15 is provided on the first active layer and the second gate electrode 122. A second active layer 16 is provided on the first insulating layer 15 and corresponds to the second gate electrode 122. The second active layer 16 is a A metal oxide layer (in this embodiment, an IGZO layer); and a first source electrode 171, a first drain electrode 172, a second source electrode 173, and a second drain electrode 174, wherein the first source The electrode 171 and the first drain electrode 172 are disposed on the first insulating layer 15 and are electrically connected to the source region 141 and the drain region 142 of the first active layer through the through holes 171a and 172a, and the second source electrode 173 and The second drain electrode 174 is disposed on the second active layer 16 and is electrically connected to the second active layer 16. Among them, the first gate electrode 121, the gate insulating layer 13, and the first active layer (polycrystalline silicon layer 14 ', see FIG. 5C), the first insulating layer 15, the first source electrode 171, and the first drain electrode 172 constitute a first thin film transistor unit TFT1, and the second gate electrode 122, the first insulating layer 15, the second active layer 16, the first The two source electrodes 173 and the second drain electrode 174 constitute a second thin film transistor unit TFT2.

The display device is the same as the display device of Embodiment 1. In this embodiment, the display device includes a first thin-film transistor unit TFT1 having a first active layer being a polycrystalline silicon layer and a second thin film having a second active layer 16 being a metal oxide layer. Transistor unit TFT2. The biggest difference between the structure of the display device in this embodiment and Embodiment 1 is that in this embodiment, the second gate electrode 122 is formed on the gate insulating layer 13 as shown in FIG. 5H; The second gate electrode 122 is formed under the gate insulating layer 13, as shown in FIG. 2G. In addition, another difference between the display device structure of this embodiment and Embodiment 1 is that in this embodiment, the first gate electrode 121 is made of a highly heat-resistant metal material such as Ti, Cr, Mo, or a transparent conductive oxide. The first gate electrode 121 can be prevented from being damaged by the laser process, and the thickness of the first gate electrode 121 can be reduced.

Example 4

FIG. 6A is a schematic cross-sectional view of the display device of this embodiment; and FIG. 6B is a top view of some layers in the second thin film transistor unit, which shows the second gate electrode 122 ', the scan line 125, the second active layer 16, The relationship between the second source electrode 173 and the second drain electrode 174. The structure of the display device of this embodiment is similar to that of Embodiment 3, except for the following differences.

In Embodiment 3, the second gate electrode 122 may be made of a metal material such as Cu or Al, as shown in FIG. 5H. However, in this embodiment, the material of the second gate electrode 122 'is polycrystalline silicon. More specifically, when the first active layer (polycrystalline silicon layer including the source region 141, the drain region 142, and the channel region 143) is formed, the polycrystalline silicon is further formed on a region where the second thin film transistor unit TFT2 is to be formed; and The polycrystalline silicon formed on the region of the second thin film transistor unit TFT2 is further n + heavily doped to form the second gate electrode 122 ′ of this embodiment.

In addition, in this embodiment, while forming the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174, a scan line 125 is further formed on the first insulating layer 15, and The scan line 125 passes through a through hole 125a to be electrically connected to the second gate electrode 122 '.

Example 5

The structure of the display device of this embodiment is similar to that of Embodiment 1, except that the structure and material of the second gate electrode 122 are different.

7A to 7G are schematic cross-sectional views illustrating a manufacturing process of components on a substrate of a display device according to this embodiment. First, as shown in FIG. 7A, a substrate 11 is provided, and a first conductive layer 123 and a second conductive layer 124 are sequentially formed on the substrate 11. Then, a first mask 21 made of a photoresist is formed in a region where the first thin film transistor unit TFT1 is to be formed using a half-tone mask, and is formed in a region where the second thin film transistor unit TFT2 and the scan line SL are to be formed. First mask 22. Next, as shown in FIG. 7B, the first conductive layer 123 and the second conductive layer 124 are etched; the masks 21 and 22 are ashed, and the first thin-film transistor unit TFT1 and the second thin-film transistor that are intended to be formed are removed by etching. The second conductive layer 124 in the region of the crystal unit TFT2 is shown in FIG. 7C. Finally, the mask 22 is removed to complete the first gate 121 and the second gate (the first conductive layer 123 and the second conductive layer 124 in the region of the second thin film transistor unit TFT2) of this embodiment, such as Figure 7D.

In this embodiment, the first gate electrode 121 is formed by the first conductive layer 123, and the second gate electrode is formed by sequentially stacking the first conductive layer 123 and the second conductive layer 124 on the substrate 11, and the first Second Leader The electrical layer 124 partially covers the first conductive layer 123. The second gate electrode in the TFT2 region of the second thin film transistor unit is composed of the first conductive layer 123, and the second gate electrode in the scan line SL region is composed of the first conductive layer 123 and the second conductive layer 124. . The material of the first conductive layer 123 includes Ti, Cr, Mo, or a transparent conductive oxide, and the material of the second conductive layer 124 includes Cu, Al, Ti, Cr, Mo, or a transparent conductive oxide.

After forming the first gate electrode 121 and the second gate electrode, a first active layer (a polycrystalline silicon layer including a source region 141, a drain region 142, and a channel region 143) is sequentially formed using a process similar to that in Embodiment 1. The first insulating layer 15 and the second active layer 16 are shown in FIGS. 7D and 7E. The second conductive layer 124 partially covers the first conductive layer 123, and an area of the first conductive layer 123 that does not cover the second conductive layer 124 corresponds to the second active layer 16.

Then, as shown in FIG. 7F, the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 are formed using a process similar to that of Embodiment 1 except that the materials and structures are different. In this embodiment, the first source electrode 171 and the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 are formed of a third conductive layer such as Ti, Cr, Mo, or a transparent conductive oxide. And a fourth conductive layer 175, such as Cu or Al, partially covers at least one of the second source electrode 173 and the second drain electrode 174. In this embodiment, the fourth conductive layer 175 is formed on the second source electrode 173 as a data line.

Finally, as shown in FIG. 7G, using a process similar to that of Embodiment 1 to form the second insulating layer 18 and the pixel electrode 19, the fabrication of each element on the substrate 11 in this embodiment is completed.

Example 6

FIG. 8A is a schematic cross-sectional view of the display device of this embodiment; and FIG. 8B is a top view of some layers in the second thin film transistor unit, which shows the second conductive layer 124, the second active layer 16, The relationship between the second source electrode 173, the second drain electrode 174, and the fourth conductive layer 175. The process and structure of this embodiment are similar to those of Embodiment 5, except for the following differences.

First, in the region of the second thin-film transistor unit TFT2, the second conductive layer 124 completely covers the first conductive layer 123; and this part can be manufactured by the process shown in FIG. 3A to FIG. 3E of Embodiment 2. form. In addition, in the region of the second thin film transistor unit TFT2, a fourth conductive layer 175, such as Cu or Al, is partially covered on the second source electrode 173 as in the embodiment 5, and further covers the second drain electrode 174.

Example 7

FIG. 9 is a schematic cross-sectional view of the display device of this embodiment. This embodiment is similar to the process and structure of Embodiment 6, except that the fourth conductive layer 175 is formed only on the second source electrode 173 and is not formed on the second drain electrode 174.

Example 8

FIG. 10 is a schematic cross-sectional view of the display device of this embodiment. This embodiment is similar to the process and structure of Embodiment 1, except for the following differences.

In the display device of this embodiment, on the first thin film transistor unit TFT1, the first active layer may further include an amorphous silicon layer 145 and a doped amorphous silicon layer 146, wherein the amorphous silicon layer 145 and The doped amorphous silicon layer 146 is sequentially disposed on the source region 141 and the drain region 142 of the polycrystalline silicon layer. This can reduce the leakage current of the low-temperature polycrystalline silicon thin film transistor unit.

Example 9

FIG. 11 is a schematic cross-sectional view of the display device of this embodiment. This embodiment is similar to the process and structure of Embodiment 9, except that the amorphous silicon layer 145 is further disposed on the channel region 143 of the polycrystalline silicon layer.

The amorphous silicon layer 145 and the doped amorphous silicon layer 146 of the foregoing Embodiments 8 and 9 may be provided on the display device of Embodiment 1 or on the display devices of Embodiments 1 to 7 in addition to the display device of Embodiment 1.

In this disclosure, the display device manufactured in the foregoing embodiment can be combined with a touch panel and used as a touch display device. At the same time, the display device or touch display device manufactured in the foregoing embodiments can be applied to any electronic device known in the art that requires a display screen, such as a display, a mobile phone, a notebook computer, a video camera, a camera, and music Players, mobile navigation devices, televisions and other electronic devices that need to display images.

The above embodiments are merely examples for the convenience of description. The scope of the rights claimed in this disclosure should be based on the scope of the patent application, rather than being limited to the above embodiments.

11‧‧‧ substrate

121‧‧‧first gate

122‧‧‧Second Gate

13‧‧‧Gate insulation

131‧‧‧ bottom gate insulation

132‧‧‧Top gate insulation

141‧‧‧Source area

142‧‧‧Drain

143‧‧‧Channel area

15‧‧‧first insulating layer

151‧‧‧The first bottom insulation layer

152‧‧‧First top insulation layer

16‧‧‧Second Active Level

171‧‧‧First source

171a, 172a‧‧‧through hole

172‧‧‧first drain

173‧‧‧Second Source

174‧‧‧Second Drain

18‧‧‧Second insulation layer

19‧‧‧ pixel electrode

19a‧‧‧ contact hole

H1, H2‧‧‧Distance

TFT1‧‧‧The first thin film transistor unit

TFT2‧‧‧Second thin film transistor unit

Claims (14)

A display device includes: a substrate; a first gate and a second gate disposed on the substrate; a gate insulating layer disposed on the substrate, the first gate, and the second gate; A first active layer is provided on the gate insulating layer and corresponds to the first gate, wherein the first active layer includes a polycrystalline silicon layer; a first insulating layer is provided on the first active layer and the gate A second active layer disposed on the first insulating layer and corresponding to the second gate, wherein the second active layer includes a metal oxide layer; a first source electrode, a first A drain electrode, a second source electrode, and a second drain electrode, wherein the first source electrode and the first drain electrode are disposed on the first insulating layer and pass through a plurality of through holes to electrically communicate with the first active layer; Connected, and the second source and the second drain are disposed on the second active layer and electrically connected to the second active layer; wherein the first gate, the gate insulating layer, and the first The active layer, the first insulating layer, the first source and the first drain constitute a first thin film transistor unit, and the second gate, the gate Insulating layer, the first insulating layer, the second active layer, the second source and drain of the second thin film transistor constituting a second unit; and a display medium disposed on the substrate. The display device according to item 1 of the scope of patent application, wherein a distance between the first gate electrode and the first active layer is smaller than a distance between the second gate electrode and the second active layer. The display device according to item 1 of the scope of patent application, wherein the display device includes a display area and a peripheral area, the peripheral area is arranged around the display area, and the first thin film transistor unit is disposed in the peripheral area, The second thin film transistor unit is disposed in the display area. The display device according to item 1 of the scope of patent application, wherein the gate insulating layer includes a bottom gate insulating layer and a top gate insulating layer, and the bottom gate insulating layer is provided on the substrate to be insulated from the top gate. Between layers, and the material of the bottom gate insulating layer is silicon nitride, and the material of the top gate insulating layer is silicon oxide. The display device according to item 1 of the scope of patent application, wherein the first insulating layer includes a first bottom insulating layer and a first top insulating layer, and the first bottom insulating layer is provided on the gate insulating layer and the first insulating layer. Between a top insulating layer, the material of the first bottom insulating layer is silicon nitride, and the material of the first top insulating layer is silicon oxide. The display device according to item 1 of the scope of patent application, wherein the first gate is formed by a first conductive layer, and the second gate is formed by laminating the first conductive layer and a second conductive layer on the first conductive layer. Formed on the substrate. The display device according to item 1 of the scope of patent application, wherein a thickness of the first gate electrode is smaller than a thickness of the second gate electrode. The display device according to item 6 of the scope of patent application, wherein the second conductive layer partially covers the first conductive layer, and an area of the first conductive layer that does not cover the second conductive layer is related to the second active layer. Layer correspondence. The display device according to item 1 of the patent application scope, wherein the polycrystalline silicon layer includes a source region, a drain region, and a channel region, and the channel region is located between the source region and the drain region. The electrode region and the drain region are electrically connected to the first source electrode and the first drain electrode, respectively; and the first active layer further includes an amorphous silicon layer disposed on the polycrystalline silicon layer. A display device includes: a substrate; a first gate electrode disposed on the substrate; a gate insulation layer disposed on the substrate and the first gate electrode; A first active layer disposed on the gate insulating layer and corresponding to the first gate, wherein the first active layer includes a polycrystalline silicon layer; a second gate disposed on the gate insulating layer; A first insulating layer is disposed on the first active layer and the second gate; a second active layer is disposed on the first insulating layer and corresponds to the second gate, wherein the second active layer includes a Metal oxide layer; a first source, a first drain, a second source, and a second drain, wherein the first source and the first drain are disposed on the first insulating layer And through a plurality of through holes to be electrically connected to the first active layer, and the second source electrode and the second drain electrode are disposed on the second active layer and electrically connected to the second active layer; wherein, the The first gate, the gate insulating layer, the first active layer, the first insulating layer, the first source and the first drain constitute a first thin film transistor unit, and the second gate, The first insulating layer, the second active layer, the second source electrode and the second drain electrode constitute a second thin film transistor unit; and a display medium, On the substrate. The display device according to item 10 of the scope of patent application, wherein the display device includes a display area and a peripheral area, the peripheral area is disposed around the display area, and the first thin film transistor unit is disposed in the peripheral area, The second thin film transistor unit is disposed in the display area. The display device according to item 10 of the scope of patent application, wherein the gate insulating layer includes a bottom gate insulating layer and a top gate insulating layer, and the bottom gate insulating layer is provided on the substrate to be insulated from the top gate. Between layers, and the material of the bottom gate insulating layer is silicon nitride, and the material of the top gate insulating layer is silicon oxide. The display device according to item 10 of the scope of patent application, wherein the first insulating layer includes a first bottom insulating layer and a first top insulating layer, and the first bottom insulating layer is provided on the gate insulating layer and Between the first top insulating layers, a material of the first bottom insulating layer is silicon nitride, and a material of the first top insulating layer is silicon oxide. The display device according to item 10 of the scope of patent application, wherein the polycrystalline silicon layer includes a source region, a drain region, and a channel region, and the channel region is located between the source region and the drain region. The electrode region and the drain region are electrically connected to the first source electrode and the first drain electrode, respectively; and the first active layer further includes an amorphous silicon layer, wherein the amorphous silicon layer is disposed on the polycrystalline silicon layer.