TW201633050A - Data write back - Google Patents

Abstract

Example implementations relate to data write back. For example, a data write back system, comprising a micro-uninterruptible power supply ([mu]UPS) module to signal a primary power supply interruption to a controller, and the controller to segregate a portion of memory, and restore data to the segregated portion of memory in response to the primary power supply interruption signal.

Description

Data write back technique Field of invention

The present invention relates to data writing back techniques.

Background of the invention

Since the reliance on computing systems continues to grow, so does the need for reliable power systems and the support mechanisms for these computing systems. For example, the server can provide mechanisms for backing up data to flash or permanent memory and for powering back to the backup data after power loss.

Summary of invention

According to an embodiment of the present invention, a data write back system is specifically provided, comprising: a micro uninterruptible power supply (μUPS) for issuing a main power supply interruption signal to a controller; and the control The device is configured to: isolate a portion of the memory; and respond to the main power supply interruption signal to reply data to the memory of the isolated portion.

100‧‧‧ system

102‧‧‧Micro-continuous power supply

104‧‧‧ Controller

106‧‧‧Central Processing Unit (CPU)

108‧‧‧Double inline memory module

110, 112‧‧‧ memory

114‧‧‧Isolated part of memory

116‧‧‧ nodes

118‧‧‧load

120‧‧‧ Path

122‧‧‧ signal

230‧‧‧data writing back system

232‧‧‧Handling resources

234‧‧‧Communication link

236‧‧‧ Memory resources

238‧‧‧ memory

240‧‧‧ signalling

242‧‧‧Respond to instructions

352‧‧‧Cache Information

354‧‧‧ metadata

356‧‧‧Information

460‧‧‧Information writing method

462-468‧‧‧Material write back method steps

Figure 1 illustrates a system for data writeback techniques in accordance with the present disclosure Block diagram of a system example; FIG. 2 illustrates a block diagram of a system example for data writeback techniques in accordance with the present disclosure; FIG. 3 illustrates a block diagram of a system example for data writeback techniques in accordance with the present disclosure; 4 illustrates an example of a method of writing back a process according to the disclosure.

Detailed description of the preferred embodiment

A computing data storage system can include a number of nodes that support several loads. For example, the nodes can be a number of servers. A number of loads may include storage controllers or devices associated with the servers. For example, a load may include cache memory, dual in-line memory modules (DIMMs), non-electrical dual in-line memory modules (NVDIMMs), and/or array control logic, and other associated with the servers. Storage controller and/or device.

The removal of a primary power supply can be scheduled or not scheduled. For example, one of the primary power supply schedule removals can be the result of scheduled maintenance on several nodes and/or on several loads. An unscheduled primary power supply removal may be one of the major power supply interruptions. An unscheduled primary power supply interruption may occur, for example, when the primary power supply is briefly and/or fails over a time period. Failures may include accidental power losses from one of the primary power supplies to the nodes and/or loads.

A tiny uninterrupted power supply (μUPS) can be a one-time A power supply that is used to provide emergency power to a load when a primary power supply (eg, input power) is interrupted. A disruption to a primary power supply may involve a power failure, power surge, inadequate power, and/or transient failure. A μ UPS can provide near instantaneous protection from power interruptions by supplying energy stored in batteries, supercapacitors, or flywheels, and the like.

When a primary power supply is removed, it may require moving memory from a number of nodes to move data to non-electrical memory. However, moving data from cache to non-electrical memory may involve a primary power supply. A μUPS can be a primary power supply that is used to provide power to move data from the cache to non-electrical memory when the primary power is removed (eg, standby mode). Further, the μUPS may be present in a power supply tank and/or a shared μUPS, wherein the shared μUPS associated with a particular node is commonly used among a plurality of loads associated with the node.

An example of the present disclosure can include a system that includes a μUPS to issue a main power supply interrupt signal to a controller. The controller can isolate a portion of the memory and/or respond to the main power supply interrupt signal to reply data to an isolated portion of the memory.

1 illustrates a block diagram of an example of a system 100 for data writeback in accordance with the present disclosure. As illustrated in FIG. 1, the system 100 can include a μUPS 102 to signal a primary power supply interruption to a controller 104. A μ UPS system can relate to an electrical device that provides a temporary power source to a load 118 when a main power supply is interrupted (eg, stopped). And can be integrated into a node 116 (eg, as one of the server nodes integrated components). One of the integrated components of the node 116, as used herein, can include a separate component from the node 116 that is combined with the node 116 such that the node 116 and the integrated component act together as a single unit. For example, a μ UPS may be present in one of the power supply slots of node 116 (eg, physically and/or directly plugged into one of the power supply slots of node 116). The μUPS 102 can be used in response to a primary power supply interruption to protect the system 100, such as a system central processing unit (CPU) 106 and system DIMM 108, from hardware and components.

Controller 104 can manage access memory 110, 112, and controller 104 can isolate a portion of memory 114. The memory of the isolated portion can be performed by the controller 104 when the power is turned on. The controller can isolate a portion of the memory 114 for use in data storage. In some examples, the isolated portion of memory 114 is within a hidden partition. A hidden partition, as used herein, may involve non-electrical memory that is not visible to a segment of the CPU and is uniquely reserved for use in a data dump when a primary power supply is interrupted. A data dump can involve the transfer of quantity data from one system or location to another. The controller can generate a hidden partition in which the memory 114 of the isolated portion can be reserved for use in a data dump.

In some examples, controller 104 can identify an associated number of drivers within system 100 within the memory of the isolated portion. The controller 104 can identify the sequential bandwidth of one of the associated number of drivers. In some examples, the controller 104 can include a delay period to specify Used to reply to a portion of the permanent data to the associated number of drives. For example, the controller can delay specifying the material that will be replied to. Further, the controller 104 can reply the data to the memory 114 of the isolated portion in response to the main power supply interruption signal 122.

In some examples, the μUPS 102 can be one of the nodes 116 to integrate components and/or provide temporary power to a load 118 associated with a node 116 for a critical time. For example, the integrated power supply can include a μUPS that is used to provide power for moving data from the cache memory to non-electrical memory when the primary power is interrupted. Further, the μUPS may be present in one of the node power supply slots and/or may be a shared μUPS in which the shared μUPS associated with a particular node is commonly used in a plurality of loads associated with the node. The μUPS can be integrated into the node. The node 116 and the load 118 may be in communication via a path 120 (e.g., a link). Although a single load 118 is illustrated in FIG. 1, more than one load may be hosted by node 116. For example, the node 116 can host several devices, such as local memory or data storage (eg, which is commonly referred to as memory). The memory can include both electrical and non-electrical memory (eg, cache, DIMM, NVDIMM). Node 116 may include other devices associated with node 116, such as cache memory, DIMMs, array control logic, and storage controllers. In some examples, the node 116 can also include a control logic unit (not shown in the graphics).

In some examples, the isolated portion of memory 114 can be a data write available for use during a main power supply interruption. That is, when the Lord When the power supply is interrupted, the data can be transferred to the memory 114 of the isolated portion and the data can be written back to the non-electrical memory. In some examples, controller 104 can linearly reply to the data from the data dump. As used herein, a linear response to a data can relate to an ongoing data chain. That is, the data is stored in a sequential order and is replied. Further, the controller 104 can, in some examples, reply to system functions associated with the material. In other words, the data stored by the isolated portion of memory 114 can be implemented and restored to the functionality of system 100.

A primary power supply interruption interrupt signal may be a signal that communicates an instruction and/or a command, for example, initiates a write from one of the nodes 116 to the node 116 based on the location of the electrical memory. One of the nodes 116 of the memory location sequentially turns off one of the instructions and/or commands. In one example, a primary power supply interruption signal can include a signal from one of the controllers 104 that communicates via one of the power button logic one of the node button 116 system complex programmable logic devices (CPLDs) to initiate the node 116. One is sequentially turned off as if one of the power buttons on node 116 has been pressed.

In an additional example, a primary power supply interruption signal may be one of the primary power supply units from one of the primary power supplies, which is used on a south bridge of one of the nodes 116 (eg, in one of the CPUs) A general purpose interface (GPI) pin of one of the two chips in the core logic chipset on one of the Northbridge/Southbridge chipset structures is transmitted. In this additional example, the pin can be programmed to issue a primary power supply interrupt signal to the operating system and the node 116 can then execute an isolation engine, as discussed further in FIG.

2 illustrates a block diagram of an example of a system 230 for data writeback in accordance with the present disclosure. The system 230 can employ hardware, software (e.g., program instructions), firmware, and/or logic to perform some of the functions described herein. The system 230 can be any combination of hardware and program instructions that are assembled to share information. The hardware can, for example, include a processing resource 232 and a memory resource 236 (eg, computer or machine readable media (CRM/MRM), database, etc.). A processing resource 232, as used herein, can include one or more processors capable of executing instructions stored by the memory resource 236. The processing resource 232 can be implemented at a single node (e.g., as illustrated by node 116 in FIG. 1) or distributed across a plurality of nodes. The program instructions (eg, computer or machine readable instructions (CRI/MRI)) may include instructions stored on the memory resource 236 and may be executed by processing the resource 232 for performing a particular function, task, and / or action (for example, to isolate a portion of memory 238).

The memory resource 236 can be a non-transitory MRM that includes one or more memory components capable of storing instructions, and can be executed by a processing resource 232 and can be integrated into a single node or spread across Most nodes. The memory resource 236 can be in communication with the processing resource 232 via a communication link (e.g., a route) 234. The communication link 234 can provide a wired and/or wireless connection between the processing resource 232 and the memory resource 236.

As illustrated in FIG. 2, memory resource 236 can include isolation 238 instructions, signal 240 instructions, and/or reply data to isolate instructions. As used herein, an instruction includes at least one processing resource that can be utilized (eg, For example, the software executed by the resource 232) is executed to perform a specific task, function, and/or action. A plurality of instructions may be combined or may be a subroutine of other instructions. As shown in FIG. 2, the isolation 238 command, the issue signal 240 command, and/or the reply 242 command may be individual instructions disposed on a memory resource 236. However, the examples are not limited by this, and a plurality of instructions can be placed at separate and distinct memory resource locations, for example, in a distributed computing environment, in a cloud computing environment, and the like.

For example, system 230 can include executable instructions to use a controller (e.g., controller 104 as illustrated in FIG. 1) to identify hidden partitions of memory including isolated portions. That is, the controller can identify the hidden partition and locate the memory of the isolated portion during a data dump. In other words, in some instances, the controller can direct the data to the memory of the isolated portion for writeback by the cache. The data in the memory of the isolated portion can be recovered and implemented within the system.

Each of the plurality of instructions can include instructions that, when executed by processing resource 232, can act as an engine. For example, the isolation 238 instructions may include instructions that, when executed by the processing resource 232, act as an isolation engine (not shown in the graphics). The signaling 240 command can include instructions that, when executed by the processing resource 232, act as a signaling engine (not shown in the graphics). The reply 242 command may include instructions that, when executed by the processing resource 232, act as a reply engine (not shown in the graphics).

A plurality of engines (not shown in the graphics) may include a combination of hardware and software (eg, program instructions), but at least include being configured to The hardware of a particular function, task, and/or action. For example, the plurality of engines can be used to isolate a portion of the memory using a controller coupled to a node, wherein the memory of the isolated portion is a hidden partition; using a μUPS to issue a master A power supply interrupt signal is sent to the controller, wherein the μUPS is integrated to the node; and the data is replied to the memory of the isolated portion in response to a signal to issue a main power supply interruption.

System 230 can include a library (not shown in the graphics) of a plurality of engines (e.g., an isolation engine, a signaling engine, a reply engine) that are accessible and in communication with them. The system 230 can include additional or fewer engines to perform the various functions described herein and the examples are not limited to the examples shown in FIG. The system 230 can include hardware (eg, in the form of transistor logic and/or application specific integrated circuits (ASIC)), firmware, and software, for example, in the form of machine readable and executable instructions (eg, The program instructions stored in a machine readable medium, which cooperatively form a computing device as discussed in connection with FIG.

The examples are not limited to the example instructions shown in Figure 2, and in some cases, several instructions may operate together to act as a particular engine. Additionally, one or more of the engines described above, or one or more of the above instructions, may be combined or may be a sub-engine of another engine. Further, the engine and/or instructions of FIG. 2 may be located in a single system and/or computing system or in a decentralized network, cloud computing, enterprise service environment (eg, a software as a service (SaaS) environment), etc. In their respective positions.

3 illustrates a block diagram of an example of a memory 314 for an isolated portion of a data writeback in accordance with the present disclosure. The memory portion 314 of the isolated portion can The memory 352, metadata 354, and data 356 are included in a memory portion of the isolated portion (e.g., portion 114 illustrated in FIG. 1).

In some examples, a portion of the memory isolation can be initiated during system power up. That is, in some instances, the portion of the memory (e.g., portion 114 as illustrated in Figure 1) may be isolated prior to a main power supply interruption. This portion of the memory can be isolated by a controller as a primary power supply interruption and one of the preventative measures in the upcoming data dump event.

In some examples, a controller (eg, controller 104 as illustrated in FIG. 1) can sequentially transmit data to the memory of the isolated portion. As illustrated in FIG. 3, the data may be instructed in sequence such that different types of material (eg, cache material 352, metadata 354, and material 356) are classified.

In some examples, when the system is powered, the memory that replies to the isolated portion can reply to the function associated with the data. That is, the memory in which the data is transferred into the isolated portion can store the data and execute the data, thereby reverting to the function associated with the stored material. For example, when the system is powered, the cache data 352 stored in the memory of the isolated portion can be used by the CPU. For example, the cache data can be written back so that the CPU can use the data.

4 illustrates an example of the flow of a data writeback method 460 in accordance with one aspect of the present disclosure. At 462, method 460 can include isolating a portion of the memory using a controller coupled to a node, wherein the memory of the isolated portion is a hidden partition. The controller can be isolated when the power is turned on Will be assigned to a portion of the memory of the memory in the main power outage event. The memory of the isolated portion can be a hidden partition. The hidden partition can isolate the portion of the memory such that the computing system does not use a portion of the memory for memory storage during normal system operation.

At 464, method 460 can include using a μUPS to issue a primary power supply interrupt signal to the controller. In some examples, the μUPS can be integrated to the node and can include providing a backup power supply to the node as a temporary power source for a critical time. That is, the μUPS can be associated with the node and provide a backup power supply source when the primary power supply is interrupted. The μUPS can provide the backup power supply for a limited period of time. For example, when the main power supply is interrupted, the μUPS can provide power to the node for a critical time, for example, 60 seconds.

At 466, method 460 can include identifying the hidden partition of the memory including the isolated portion using the controller and in response to the signal. As discussed with respect to 464, the μUPS can provide power for a critical time during which the controller can recognize the hidden partition. Once the hidden portion is recognized, the controller can continue the data dump. That is, the controller can transmit data to the hidden partition, which includes the memory of the isolated portion. The data can be stored in the memory of the isolated portion and written to the non-electrical memory. In some examples, the method 460 can include sequentially transmitting data to the memory of the isolated portion. For example, the controller can transfer data in a sequential manner.

At 468, method 460 can include responding to identifying the memory of the isolated portion and replying the data to the memory of the isolated portion. E.g, The data stored in the memory of the isolated portion can be written to the non-electrical memory. This data can be executed and replied when the system is powered. That is, the data transferred to the memory of the isolated portion can be stored, executed, and thus returned to the system.

In some examples, method 460 can include a plurality of controllers, such as the controllers described above, and a plurality of drivers associated with the plurality of partial memories, and recovering the plurality of data to the plurality of memory partitions. Share. That is, a plurality of controllers executing a plurality of sets of drivers can perform data dumping and reply data to the memory.

In the above Detailed Description of the Disclosure, reference is made to the accompanying drawings, in which FIG. The examples are described in sufficient detail to enable those skilled in the art to implement the disclosed examples, and other examples may be employed, and the process, electrical, and/or structure may be modified without departing from the scope of the present disclosure.

The graphics here follow a numbering convention in which the first number corresponds to the graphical number and the remaining digits identify one of the elements or components in the graphic. Elements shown in the various figures herein may be added, exchanged, and/or removed to provide some additional examples of the present disclosure. In addition, the proportions and relative dimensions of the elements provided in the figures are intended to exemplify the present disclosure and are not to be construed as limiting. Further, as used herein, "a" or "an" may refer to one or more of the elements and/or features.

As used herein, "logic" is relative to computer executable instructions (eg, software, toughness) that are stored in memory and executable by a processor. Body, etc.) for performing a particular action and/or function, etc., as an alternative or additional processing resource as described herein, including hardware, for example, various forms of transistor logic, Application specific integrated circuits (ASIC) and the like.

100‧‧‧ system

102‧‧‧Micro-continuous power supply (μUPS)

104‧‧‧ Controller

106‧‧‧Central Processing Unit (CPU)

108‧‧‧Double Inline Memory Module (DIMM)

110, 112‧‧‧ memory

114‧‧‧Isolated part of memory

116‧‧‧ nodes

118‧‧‧load

120‧‧‧ Path

122‧‧‧ signal

Claims (15)

A data write back system includes: a miniature uninterruptible power supply (μUPS) for issuing a main power supply interruption signal to a controller; and the controller is configured to perform the following actions: isolating a part a memory; and a memory that replies to the isolated portion in response to the main power supply interruption signal. The system of claim 1, wherein the controller is configured to identify the memory of the isolated portion: an associated number of drivers within the system; one of the associated number of drivers in sequence; and a delay period, It is used to specify the permanent data for a portion of the reply to the associated number of drives. The system of claim 1, wherein the micro-continuous power supply is one of the nodes that integrates the components and provides a temporary power source to a load associated with the node for a critical time. The system of claim 1, wherein the memory of the isolated portion is within a hidden partition. A system as claimed in claim 1, comprising the controller for performing the following actions: linearly replying to the material; and replying to system functions associated with the material. The system of claim 1, wherein the memory of the isolated portion is available The data is written back during a power supply interruption. A non-transitory machine readable medium storing instructions, the instructions being executable by a processing resource to cause a computer to perform the following actions: using a controller coupled to a node to isolate a portion of the memory The memory of the isolated portion is a hidden partition; using a miniature uninterruptible power supply (μUPS) to issue a main power supply interruption signal to the controller, wherein the micro-continuous power supply is integrated And to the node; and responsive to the issued main power supply interruption signal, and replying the data to the memory of the isolated portion. The medium of claim 7, further comprising instructions executable to identify the hidden partition of the memory comprising the isolated portion using the controller. The medium of claim 7, further comprising instructions executable to sequentially transmit data to the isolated memory. The medium of claim 7, wherein the instructions executable to reply data to the memory of the isolated portion include instructions executable to reply to a function associated with the material when the power is turned on. The medium of claim 7, wherein the instructions executable to isolate a portion of the memory are initiated during system power up. A method for writing data back includes the steps of isolating a portion of the memory using a controller coupled to a node, wherein the memory of the isolated portion is a hidden partition; Using a miniature uninterruptible power supply (μUPS) to issue a main power supply interrupt signal to the controller; using the controller and responsive to the signal, identifying the hidden partition of the memory including the isolated portion And responding to the memory of the identified isolated portion and replying the data to the memory of the isolated portion. The method of claim 12, further comprising sequentially transmitting data to the memory of the isolated portion. The method of claim 12, further comprising performing a plurality of data replies to the memory of the plurality of isolated portions using a plurality of controllers and a plurality of drivers associated with the plurality of isolated portions of memory. The method of claim 12, wherein the miniature uninterruptible power supply is integrated into the node and provides a backup power supply as a temporary power source to the node for a critical time.