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TW201631722A - 功率轉換電路的封裝模組及其製造方法 - Google Patents

功率轉換電路的封裝模組及其製造方法 Download PDF

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Publication number
TW201631722A
TW201631722A TW104128234A TW104128234A TW201631722A TW 201631722 A TW201631722 A TW 201631722A TW 104128234 A TW104128234 A TW 104128234A TW 104128234 A TW104128234 A TW 104128234A TW 201631722 A TW201631722 A TW 201631722A
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Taiwan
Prior art keywords
layer
substrate
package module
conversion circuit
power conversion
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TW104128234A
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English (en)
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TWI685075B (zh
Inventor
魯凱
趙振清
洪守玉
王濤
梁樂
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台達電子工業股份有限公司
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Publication of TW201631722A publication Critical patent/TW201631722A/zh
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Abstract

本案公開了一種功率轉換電路的封裝模組及其製造方法。該功率轉換電路的封裝模組可表面貼裝於一系統板。功率轉換電路的封裝模組包括:基板,功率器件晶片和塑封層以及多個引腳。基板具有金屬層,絕緣基板層和導熱層,絕緣基板層位於金屬層和導熱層之間。功率器件晶片連接金屬層;基板的金屬層上的所有器件埋入塑封層。多個引腳電性連接金屬層且多個該引腳埋入塑封層,至少露出引腳與系統板的電性連接的接觸面。接觸面平行及/或垂直於導熱層。此種結構的封裝模組佔用面積小,利於批量製作。

Description

功率轉換電路的封裝模組及其製造方法
本發明涉及半導體封裝領域,尤其涉及一種功率轉換電路的封裝模組及其製造方法。
高效率、高功率密度、高可靠性以及低成本一直是電力、電子領域對電源變換器的要求。高效率意味著減少能耗,利於節能減排、保護環境,並減少使用成本。高功率密度則意味著體積小、重量輕,在減少材料成本的同時亦可減少運輸成本和空間需求,從而減少建設成本。高可靠性意味著更長的使用壽命以及更低的維護成本。
在電源變換器中,半導體器件是決定效率的重要因素之一。為了順應電源變換器的發展趨勢,半導體器件的模組化成為了重點的發展趨勢,功率模組封裝本身亦不斷以輕、薄、短、小的方向發展。隨著功率半導體器件封裝尺寸不斷縮小,對散熱的需求也越來越高。
圖1為傳統的方形扁平無引腳封裝(Quad Flat None-lead Package,QFN)結構的剖面圖。如圖1所示,其通常將晶片(die)90通過粘接材料(adhesive)91貼裝到引線框架(lead frame)92上,再通過引線鍵合(wire bonding)方式將晶片90上表面的焊盤(pad)和引線框架92的引腳相連,最後再通過塑封料(molding compound)93將晶片90、鍵合線94及引線框架92封裝成一個整體。雖然該封裝結構具有結構簡單、封裝尺寸小及系統板使用效率高等優點,但在散熱方面存在比較明顯的問題。在該結構中,晶片貼裝在引線框架上,而引線框架又作為一個電極貼裝到系統板(圖中未示出)上,因此晶片在工作過程中產生的熱量通過其正下方的引線框架散到系統板上。但由於晶片產生的熱量絕大部分會傳導到系統板上,不利於系統板上其他單元(如驅動單元、控制單元等)的有效工作,因而在實際使用時,通常需要在系統板上預留足夠的空間以防止熱對驅動及控制單元的影響,並且需要在系統板上進行專門的熱設計,從而達到有效散熱的目的。
圖2A-圖2C為雙列直插式封裝(Dual Inline Package,DIP)結構的剖面圖。由於引線框架92的引腳95在塑封料93的外面,佔用了一定的空間此種引腳的設計不利於節省系統端空間,因此該種引腳設計還有待優化。此外由於引腳框架92的引腳95在塑封料93的外面,也導致了在進行塑封時需要採用一穴一模組的結構,即一個封裝尺寸需要一個模具,這樣在模組尺寸改變時就必須更換新的塑封模具,而不同尺寸模具的成本提高了功率模組的生產成本。在實際操作時,為了避免過多的塑封模具的投資,在設計時往往會考慮模具的通用性,但這樣又對設計產生了種種限制。
有鑑於此,本發明提供了一種在滿足封裝輕、薄的基礎上,具有高散熱性的功率轉換電路的封裝模組,及其製造方法。
本發明提供的實施例的額外方面和優點將部分地在下面的描述中闡述,並且部分地將從描述中變得顯然,或者可以通過本發明的實踐而習得。
本發明一方面公開了一種功率轉換電路的封裝模組,該功率轉換電路的封裝模組可表面貼裝於一系統板,包括:基板,功率器件晶片,塑封層和多個引腳。該基板具有金屬層,絕緣基板層和導熱層。該絕緣基板層位於該金屬層和該導熱層之間。功率器件晶片連接該金屬層。基板的金屬層上的所有器件埋入塑封層。多個引腳電性連接金屬層且埋入塑封層,至少露出引腳與系統板的電性連接的接觸面,接觸面平行及/或垂直導熱層。其中,基板的導熱層對與金屬層相連的需散熱的器件進行散熱。
於一實施例中,上述引腳為引線框架製成。
於另一實施例中,上述引腳為銅柱,該銅柱通過導電粘接材料與上述金屬層電性連接。
於再一實施例中,上述塑封層至少包封上述基板的金屬層,曝露上述基板的導熱層。
於再一實施例中,還包括金屬連接體,該金屬連接體埋入上述塑封層。
於再一實施例中,上述金屬連接體為鍵合線,該鍵合線電連接上述功率器件晶片或者上述功率器件晶片與上述金屬層。
於再一實施例中,上述金屬連接體為銅條,該銅條電連接上述功率器件晶片或者上述功率器件晶片與上述金屬層。
於再一實施例中,上述金屬連接體為金屬凸點,上述功率器件晶片反扣於上述金屬凸點,實現上述功率器件晶片與上述金屬層的電性連接。
於再一實施例中,上述基板為金屬化陶瓷基板或者絕緣金屬基板。
於再一實施例中,上述引腳包括至少一L型金屬部,上述L型金屬部由豎直部和水平部構成;上述引腳曝露的接觸面位於該水平部。
本發明另一方面公開了一種製造上述功率轉換電路的封裝模組的方法步驟a:將未封裝的功率轉換電路製作為矩陣排列的形式;步驟b:用塑封層將該功率轉換電路帶器件的一麵包封起來;步驟c:使該功率轉換電路中引腳的接觸面從該塑封層中曝露出;步驟d:分割包封後的矩陣排列的功率轉換電路為單個獨立的功率轉換電路的封裝模組。
於一實施例中,步驟a包括:步驟a1:製作連片式基板;步驟a2:完成該連片式基板上功率器件晶片的安裝和連片式引腳的連接。
於另一實施例中,步驟d包括:步驟d1:預切割上述連片式基板;步驟d2:切割上述連片式引腳和上述塑封層。
於再一實施例中,步驟a包括:步驟a1:將若干基板形成矩陣式擺放;步驟a2:完成若干基板上功率器件晶片的安裝和連片式引腳的連接。
於再一實施例中,步驟d中分割包括分割上述連片式引腳和塑封層。
於再一實施例中,上述連片式引腳為引線框架製作。
本發明公開的功率轉換電路的封裝模組通過將引腳從遠離基板下表面的一側引出,實現電、熱的分離,有利於功率轉換電路的封裝模組在工作時的散熱,並因為不會散熱到系統板,節省了系統板散熱所需要的空間,且不會影響到系統板上其他單元的工作;此外,由於引腳整體在封裝體的內部,有效提升了封裝體本身的利用效率,節省了空間。本發明公開的功率轉換電路的封裝模組製造方法,採用連片式的塑封方式,這種整體塑封的方式對塑封模具的要求明顯降低,即使功率轉換電路的封裝模組的尺寸改變,也無須更新塑封模具,並具有通用性,為功率轉換電路的封裝模組的製造降低了生產成本。
90‧‧‧晶片 92‧‧‧引線框架 94‧‧‧鍵合線 93‧‧‧塑封料 91‧‧‧粘接材料 95‧‧‧引腳 96‧‧‧絕緣層 97‧‧‧基板 1、100‧‧‧基板 2‧‧‧晶片 3,3’‧‧‧連片式引腳 4、4’、130‧‧‧塑封層 5、140‧‧‧鍵合線 6‧‧‧鍵合材料 10、20、30、40‧‧‧功率轉換電路的封裝模組 11‧‧‧金屬層 12‧‧‧絕緣層 13‧‧‧第三銅層 110‧‧‧功率器件晶片 120‧‧‧引腳 150‧‧‧鍵合材料 260‧‧‧金屬凸點 370‧‧‧金屬條 420、520、620‧‧‧引腳 1000‧‧‧金屬層 1100‧‧‧絕緣層 1200‧‧‧導熱層 A-A’‧‧‧剖面線 a、b‧‧‧接觸面
圖1為傳統的方形扁平無引腳封裝結構的剖面圖。 圖2A至圖2C為傳統的雙列直插式封裝結構的剖面圖。 圖3為本發明實施例一的功率轉換電路的封裝模組的剖面圖。 圖4為本發明實施例二的功率轉換電路的封裝模組的剖面圖。 圖5為本發明實施例三的功率轉換電路的封裝模組的剖面圖。 圖6為本發明實施例四的功率轉換電路的封裝模組的剖面圖。 圖7為本發明實施例五的功率轉換電路的封裝模組的剖面圖。 圖8為本發明實施例六的功率轉換電路的封裝模組的剖面圖。 圖9為本發明一個實施例的功率轉換電路的封裝模組製造方法中整體塑封後的塑封體的俯視圖。 圖10為沿圖9中AA’線的剖面圖。 圖11A至圖11D為本發明一個實施例的功率轉換電路的封裝模組製造方法的流程示意圖。 圖12為本發明另一個實施例的功率轉換電路的封裝模組製造方法中整體塑封後的塑封體的俯視圖。 圖13為沿圖12中AA’線的剖面圖。 圖14為本發明實施例的功率轉換電路的封裝模組的多種引腳結構的示意圖。
現在將參考圖式更全面地描述示例實施方式。然而,示例實施方式能夠以多種形式實施,且不應被理解為限於在此闡述的實施方式;相反,提供這些實施方式使得本發明將全面和完整,並將示例實施方式的構思全面地傳達給本領域的技術人員。在圖中相同的元件符號表示相同或類似的結構,因而將省略對它們的重複描述。
所描述的特徵、結構可以以任何合適的方式結合在一個或更多實施方式中。在下面的描述中,提供許多具體細節從而給出對本發明的實施方式的充分理解。然而,本領域技術人員應意識到,沒有所述特定細節中的一個或更多,或者採用其它的方法、組元、材料等,也可以實踐本發明的技術方案。在其它情況下,不詳細示出或描述公知結構、材料或者操作以避免模糊本發明。
圖3為本發明實施例一的功率轉換電路的封裝模組的剖面圖。如圖3所示,本發明實施例一的功率轉換電路的封裝模組10包括:基板100、至少一個功率器件晶片110、至少一個引腳120及塑封層130。
基板100作為至少一個功率器件晶片110的安裝載板具有金屬層、絕緣基板層和導熱層,其中絕緣基板層位於金屬層和導熱層之間。至少一個功率器件晶片110例如可以為MOSFET(金屬氧化物半導體場效應電晶體)、IGBT(絕緣柵雙極電晶體)或二極體等,安裝於基板100的第一表面上,通過鍵合材料(bonding material)150(例如導電膠、釺料、燒結材料、擴散焊接材料等)實現與基板100的電/機械/熱連接;功率器件晶片110的電極可以通過鍵合線(bonding wire)140以引線鍵合(wire bonding)方式實現與基板100、引腳120等之間的電/機械/熱連接。引腳120可以通過導電粘接材料(例如焊錫、導電有機漿料等)粘接到基板100上,以實現與基板100的電連接。此外,基板100金屬層上還安裝有無源器件(圖中未示出),例如電感、電容等。基板100的導熱層供傳導功率轉換電路工作時產生的熱量。
如圖3所示,基板100包括金屬層1000、絕緣層1100及導熱層1200。其中,在金屬層1000上形成有電路圖案,絕緣層1100位於金屬層1000與導熱層1200之間,至少一個功率器件晶片110形成於金屬層1000上。在導熱層1200遠離絕緣層1100的表面外接散熱器(圖中未示出),該種結構可以有效的將功率轉換電路的封裝模組工作時產生的熱量傳遞到基板100一側,並通過外接的散熱器將熱量帶走,此外,導熱層1200與散熱器之間還可以設置導熱矽脂層,從而使熱量更快更直接地傳導出去。
基板100例如可以為直接敷銅陶瓷(Direct Bonding Copper,DBC)基板,還可以為厚膜基板、直接鍍銅(Direct Plating Copper,DPC)基板、絕緣金屬基板(Insulated Metal Substrate,IMS)等,本發明不以此為限。其中,厚膜基板一般是將金屬粉末(Ag,Cu等)與玻璃材料加上粘接劑混合,均勻成泥狀的漿料,利用刮刀和掩膜板將漿料以圖案的形式印製到陶瓷基板上,再通過800~900度的燒結溫度製作成有電路圖形的厚膜基板。DPC基板是將陶瓷基板先做前處理清潔,利用真空鍍膜方式在陶瓷基板上濺射結合於銅金屬的複合層,再以蝕刻工藝製作成線路,最後再通過電鍍或化學鍍的方式增加線路的厚度,從而完成金屬層的製作。IMS基板是在金屬板(鋁或銅等)上壓合一層有機膜充當絕緣層,再在絕緣膜上電鍍金屬化線路(或者再在絕緣膜上壓合銅箔再蝕刻成線路)。
塑封層130是在製造工藝中通過向模具(圖中未示出)中填充塑封料(molding compound)而形成,以進行整體結構的機械支撐和電氣保護。塑封層130形成於基板100之上,並將至少一個功率器件晶片110及至少一個引腳120包裹于其中,形成一個封裝體,包括:頂表面和與頂表面相交的多個側表面,其中頂表面與基板100大致平行。此外,在一實施例中塑封層130還將基板100的金屬層1000包裹於其中。
引腳120電性連接基板100的金屬層1000,僅露出與外接的系統板(圖中未示出)的接觸面,以使功率轉換電路的封裝模組10與系統板電連接。為了使功率轉換電路的封裝模組10在工作時,散熱和與系統板的電連接不在一個平面上,每個引腳120的與系統板電性連接的接觸面(即暴露出封裝體外的表面)均被設置于塑封層130的頂表面上,即每個引腳120的頂表面暴露于塑封層130的頂表面,與基板100的導熱層1200平行,例如如圖3中的接觸面a所示,如此使得功率轉換電路的封裝模組的散熱及與系統板的電連接分別在基板的導熱層一側和塑封層130的頂表面一側,從而可以在基板的導熱層一側加裝散熱器來提高模組的散熱能力;此外,因為不會散熱到系統板,節省了系統板散熱所需要的空間,並且不會影響到系統板上其他單元的工作。
此外,為了簡化封裝工藝、降低生產成本(具體將在下文中介紹),在對引腳120進行設計時,使得每個引腳120包括至少一個L形彎折部,該L形彎折部具有水平部和豎直部,水平部和豎直部僅是就其相對位置而言,水平部與豎直部之間的夾角不局限於90度。其中,除了水平部在頂表面上的接觸面a外,水平部還包括設置于塑封層130的一個側表面上的接觸面b,即與基板100的導熱層1200垂直的接觸面。引腳120的豎直部全部嵌入塑封層130中,引腳120的水平部嵌入塑封層130中,且引腳120的水平部的頂表面與水平部的一個側表面分別暴露于塑封層130的頂表面和多個側表面的其中之一。
在圖3中,以兩個引腳為例示意,兩個引腳120分別設置於功率轉換電路的封裝模組10相對的兩側,其各自的接觸面b分別位於兩個相對的側表面上。但本發明不以此為限,例如也可以僅包括一個引腳,接觸面暴露于塑封層130的頂表面和一個側表面上;或者還可以包括多於兩個引腳,其各自的接觸面分別暴露于塑封層130的頂表面及與多個側表面上。
此外,引腳120例如可以由引線框架製成,或者引腳120為銅柱,該銅柱通過導電粘接材料與基板上的金屬層電性連接。
從上述內容可以看出,本發明實施例一的功率轉換電路的封裝模組10通過將引腳從遠離基板下表面的一側引出,實現電、熱的分離,有利於功率轉換電路的封裝模組在工作時的散熱,並因為不會散熱到系統板,節省了系統板散熱所需要的空間,且不會影響到系統板上其他單元的工作;此外,由於引腳120整體在封裝體的內部,有效提升了封裝體本身的利用效率。
圖4為本發明實施例二的功率轉換電路的封裝模組的剖面圖。如圖4所示,本發明實施例二的功率轉換電路的封裝模組20與圖3所示的功率轉換電路的封裝模組10的區別在於功率器件晶片110與基板100的電連接方式不同。功率轉換電路的封裝模組20中的功率器件晶片110還可以通過倒裝晶片(flip chip)的方式與基板100電連接。在功率器件晶片110的焊盤上製作金屬凸點(bump)260,再通過金屬凸點260與基板110電連接。通常,針對平面形功率器件晶片採用倒裝晶片的方式電連接,但本發明不限於此。
實施例二的功率轉換電路的封裝模組20與實施例一的功率轉換電路的封裝模組10相同的內容,在此不再贅述。
圖5為本發明實施例三的功率轉換電路的封裝模組的剖面圖。如圖5所示,本發明實施例三的功率轉換電路的封裝模組30與圖3所示的功率轉換電路的封裝模組10的區別也在於功率器件晶片110與基板100的電連接方式不同。功率轉換電路的封裝模組30中的功率器件晶片110還可以通過金屬條370,例如銅條(cooper clip)與基板100電連接。可以先通過焊接或者燒結銀等材料將金屬條370與功率器件晶片110電連接,再將金屬條370與基板110電連接。此外,金屬條370也可以是基板110的一部分,本發明不以此為限。
實施例三的功率轉換電路的封裝模組30與實施例一的功率轉換電路的封裝模組10相同的內容,在此不再贅述。
圖6為本發明實施例四的功率轉換電路的封裝模組的剖面圖。如圖6所示,本發明實施例四的功率轉換電路的封裝模組40與圖3所示的功率轉換電路的封裝模組10的區別在於引腳420與引腳120的形狀不同。引腳420為一柱狀形狀,僅包括暴露于塑封層130的頂表面的接觸面a。在其他實施例中,引腳為倒L型,且引腳僅其水平部位于塑封層的側表面的接觸面曝露出,而水平部對應於頂表面的表面部分被較薄的塑封層覆蓋住。實施例四的功率轉換電路的封裝模組40與實施例一的功率轉換電路的封裝模組10相同的內容,在此不再贅述。
圖7為本發明實施例五的功率轉換電路的封裝模組的剖面圖。如圖7所示,本發明實施例五的功率轉換電路的封裝模組50與圖3所示的功率轉換電路的封裝模組10的區別僅在於引腳620的設計。相比於圖3中的引腳120,引腳520的水平部的厚度小於引腳520的豎直部的寬度。這樣的設計,可增強了引腳的柔性,降低其在塑封時在塑封模具上產生的的應力。
實施例五的功率轉換電路的封裝模組50與實施例一的功率轉換電路的封裝模組10相同的內容,在此不再贅述。
圖8為本發明實施例六的功率轉換電路的封裝模組的剖面圖。如圖8所示,本發明實施例六的功率轉換電路的封裝模組60與圖3所示的功率轉換電路的封裝模組10的區別也僅在於引腳620的設計。相比於圖3中的引腳120,在引腳620的水平部和豎直部相交的部分設置了一個局部凹槽,這樣的設計一方面使得引腳的加工更為容易,即使相交部分轉角位置的控制更加精准,從而增加加工精度;另一方面,也可以增加引腳的柔性,降低其在塑封時在塑封模具上產生的應力。
實施例六的功率轉換電路的封裝模組60與實施例一的功率轉換電路的封裝模組10相同的內容,在此不再贅述。
圖9為本發明一個實施例的功率轉換電路的封裝模組製造方法中整體塑封後的塑封體的俯視圖。圖10為沿圖9中AA’線的剖面圖。如圖9和圖10所示,進行整體塑封對塑封模具的要求明顯降低,即使功率轉換電路的封裝模組的尺寸改變,也無須更新塑封模具,並具有通用性,為功率轉換電路的封裝模組的製造降低了生產成本。
圖10中仍以直接敷銅陶瓷基板為例,其中每個功率轉換電路的封裝模組內部的結構與圖3中的結構基本相同,在此不再贅述。
從圖10中可以看出,虛線為功率轉換電路的封裝模組之間的切割線,即沿著該虛線進行切割後,將該整體的塑封體切割成多個功率轉換電路的封裝模組。為了增加設置、連接引腳的穩定度,簡化製造工藝,優選地,相鄰兩個功率轉換電路的封裝模組的引腳採用一體式結構,從而在切割後,在功率轉換電路的封裝模組的側表面上會出現圖3中的接觸面b,但本發明不以此為限。
同樣,圖10中也以兩個引腳為例示意,兩個引腳分別設置於每個功率轉換電路的封裝模組90相對的兩側。但本發明不以此為限,例如若干引腳均位於功率轉換電路的封裝模組的同一邊,接觸面暴露於功率轉換電路的封裝模組的頂表面和與頂表面相交的一個側表面上;或者若干引腳分佈於功率轉換電路的封裝模組不同的邊,其各自的接觸面分別暴露於功率轉換電路的封裝模組的頂表面及與頂表面相交的側表面上。
本發明還公開了一種製造上述封裝模組的方法,包括:
步驟a:將未封裝的功率轉換電路製作為矩陣排列的形式;
步驟b:用塑封層將功率轉換電路帶器件的一麵包封起來;
步驟c:使功率轉換電路中引腳的接觸面從塑封層中曝露出;
步驟d:分割包封後的矩陣排列的功率轉換電路為單個獨立的功率轉換電路的封裝模組。
圖11A至圖11D為本發明一個實施例的功率轉換電路的封裝模組製造方法的流程示意圖。該方法包括:
步驟a:如圖11A所示,提供一張連片式的基板1,以直接敷銅陶瓷基板為例,其包括:金屬層11,絕緣層12及第三銅層13。
步驟b:如圖11B所示,在連片式基板1上設置功率器件晶片2及連片式引腳3,並使功率器件晶片2、連片式引腳3及基板1之間電連接,例如通過鍵合材料6(如導電膠、釺料、燒結材料、擴散焊接材料等)實現與基板1的電/機械/熱連接;還可以通過鍵合線5以引線鍵合方式實現與基板1的電/機械/熱連接,本發明不以此為限。
步驟c:如圖11C所示,對基板1、功率器件晶片2及連片式引腳3整體進行塑封,形成整體的塑封層4,將基板1、功率器件晶片2及連片式引腳3包裹於其中;並且,連片式引腳3的頂表面暴露於整體的塑封層4的頂表面上。
步驟d:如圖11D所示,切割整體的塑封層4及連片式引腳3,使基板1及塑封層4’彼此之間分離,例如沿圖中虛線繼續切割,以形成多個獨立的功率轉換電路的封裝模組。
在一些實施例中,在切割整體的塑封層4及連片式引腳3之前還可以進行預切割,以利於其後的整體切割。
圖12為本發明另一個實施例的功率轉換電路的封裝模組製造方法中整體塑封後的塑封體的俯視圖。圖13為沿圖12中AA’線的剖面圖。與圖9和圖10中的製造方法不同的是,本實施例中的基板不是連片式的基板,而是多個單顆的基板1,通過採用連片式引腳將多個矩陣排列式的獨立基板連接起來。該連片式引腳可以是如圖12所示整體式的引腳框架3。對基板進行上述的功率器件晶片2的貼裝、電連接以及引腳3’的安裝等工藝;之後對基板1、功率器件晶片2及引腳3’整體進行塑封,形成整體的塑封層4;再通過切割整體的塑封層4及引腳3’,使基板1及塑封層4’彼此之間分離,例如沿圖中虛線繼續切割,以形成多個獨立的功率轉換電路的封裝模組。通過該製造方法,可以使每個功率轉換電路的封裝模組基板的側表面也封裝到封裝體內,利於保護基板的側面。
需要說明的是上述方法步驟僅為示例性說明,而並非用以限制本發明方法的執行順序。在可實施的情況下,本發明方法步驟可以任意順序進行。
在如圖10所示的整體塑封體結構中,除了上述公開的引腳結構外,圖14還列舉了其他幾種引腳結構。從圖14中可以看出,這幾種引腳結構在以圖14中所示虛線的位置切割後的共同點為:切割後引腳至少有兩端,一端與基板連接,另一端作為接觸面而連接系統板。這些結構的引腳也利於做成連片式引腳結構,方便引腳的電連接和後續引腳的切割。
本發明公開的功率轉換電路的封裝模組製造方法,採用連片式的塑封方式,這種整體塑封的方式對塑封模具的要求明顯降低,即使功率轉換電路的封裝模組的尺寸改變,也無須更新塑封模具,並具有通用性,為功率轉換電路的封裝模組的製造降低了生產成本。
以上具體地示出和描述了本發明的示例性實施方式。應該理解,本發明不限於所公開的實施方式,相反,本發明意圖涵蓋包含在所附申請專利範圍內的各種修改和等效置換。
10‧‧‧功率轉換電路的封裝模組
100‧‧‧基板
110‧‧‧功率器件晶片
120‧‧‧引腳
130‧‧‧塑封層
140‧‧‧鍵合線
150‧‧‧鍵合材料
1000‧‧‧金屬層
1100‧‧‧絕緣層
1200‧‧‧導熱層
a、b‧‧‧接觸面

Claims (16)

  1. 一種功率轉換電路的封裝模組,該功率轉換電路的封裝模組可表面貼裝於一系統板,其特徵在於,該功率轉換電路的封裝模組包括:   基板,該基板具有金屬層、絕緣基板層和導熱層,該絕緣基板層位於該金屬層和該導熱層之間;   功率器件晶片,該功率器件晶片連接該金屬層;   塑封層,該基板的金屬層上的所有器件埋入該塑封層;以及   多個引腳,該多個引腳電性連接該金屬層且埋入該塑封層,至少露出該引腳與該系統板的電性連接的接觸面,該接觸面平行及/或垂直該導熱層;   其中,該基板的導熱層對與該金屬層相連的需散熱的器件進行散熱。
  2. 根據申請專利範圍第1項所述之封裝模組,其中該引腳為引線框架製成。
  3. 根據申請專利範圍第1項所述之封裝模組,其中該引腳為銅柱,該銅柱通過導電粘接材料與該金屬層電性連接。
  4. 根據申請專利範圍第1項所述之封裝模組,其中該塑封層至少包封該基板的金屬層,曝露該基板的導熱層。
  5. 根據申請專利範圍第1項所述之封裝模組,還包括金屬連接體,該金屬連接體埋入該塑封層。
  6. 根據申請專利範圍第5項所述之封裝模組,其中該金屬連接體為鍵合線,該鍵合線電連接該功率器件晶片或者該功率器件晶片與該金屬層。
  7. 根據申請專利範圍第5項所述之封裝模組,其中該金屬連接體為銅條,該銅條電連接該功率器件晶片或者該功率器件晶片與該金屬層。
  8. 根據申請專利範圍第5項所述之封裝模組,其中該金屬連接體為金屬凸點,該功率器件晶片反扣於該金屬凸點,實現該功率器件晶片與該金屬層的電性連接。
  9. 根據申請專利範圍第1項所述之封裝模組,其中該基板為金屬化陶瓷基板或者絕緣金屬基板。
  10. 根據申請專利範圍第1項所述之封裝模組,其中該引腳包括至少一L型金屬部,該L型金屬部由豎直部和水平部構成;該引腳曝露的接觸面位於該水平部。
  11. 一種製造申請專利範圍第1項所述之功率轉換電路的封裝模組的方法,其中該製造方法包括:   步驟a:將未封裝的功率轉換電路製作為矩陣排列的形式;   步驟b:用塑封層將該功率轉換電路帶器件的一麵包封起來;   步驟c:使該功率轉換電路中引腳的接觸面從該塑封層中曝露出;以及   步驟d:分割包封後的矩陣排列的功率轉換電路為單個獨立的功率轉換電路的封裝模組。
  12. 根據申請專利範圍第11項所述之方法,其中步驟a包括:   步驟a1:製作連片式基板;以及   步驟a2:完成該連片式基板上功率器件晶片的安裝和連片式引腳的連接。
  13. 根據申請專利範圍第12項所述之方法,其中步驟d包括:   步驟d1:預切割該連片式基板;以及   步驟d2:切割該連片式引腳和該塑封層。
  14. 根據申請專利範圍第11項所述之方法,其中步驟a包括:   步驟a1:將若干基板形成矩陣式擺放;以及   步驟a2:完成該若干基板上功率器件晶片的安裝和連片式引腳的連接。
  15. 根據申請專利範圍第14項所述之方法,其中步驟d中分割包括分割該連片式引腳和該塑封層。
  16. 根據申請專利範圍第12項或第14項所述之方法,其中該連片式引腳為引線框架製作。
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Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10163766B2 (en) 2016-11-21 2018-12-25 Semiconductor Components Industries, Llc Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks
US9899349B2 (en) 2009-01-29 2018-02-20 Semiconductor Components Industries, Llc Semiconductor packages and related methods
US10199311B2 (en) 2009-01-29 2019-02-05 Semiconductor Components Industries, Llc Leadless semiconductor packages, leadframes therefor, and methods of making
US11036269B2 (en) 2014-09-02 2021-06-15 Delta Electronics (Shanghai) Co., Ltd. Power module and manufacturing method thereof
US20210081013A1 (en) 2014-09-02 2021-03-18 Delta Electronics, Inc. Power supply apparatus
CN111106074B (zh) * 2018-10-26 2022-04-08 台达电子企业管理(上海)有限公司 功率模块及其制造方法
US10447166B2 (en) 2015-08-31 2019-10-15 Delta Electronics, Inc. Power module
US9659837B2 (en) 2015-01-30 2017-05-23 Semiconductor Components Industries, Llc Direct bonded copper semiconductor packages and related methods
US20170018487A1 (en) * 2015-07-15 2017-01-19 Broadcom Corporation Thermal enhancement for quad flat no lead (qfn) packages
DE102016000264B4 (de) * 2016-01-08 2022-01-05 Infineon Technologies Ag Halbleiterchipgehäuse, das sich lateral erstreckende Anschlüsse umfasst, und Verfahren zur Herstellung desselben
CN108109973A (zh) * 2016-11-25 2018-06-01 同欣电子工业股份有限公司 芯片封装结构及其制造方法
TWI637536B (zh) * 2017-02-24 2018-10-01 矽品精密工業股份有限公司 電子封裝結構及其製法
CN108878391A (zh) * 2018-06-07 2018-11-23 珠海格力电器股份有限公司 智能功率模块结构及其制造方法
CN111341762A (zh) * 2018-12-19 2020-06-26 江苏宏微科技股份有限公司 一种用于大功率多管芯封装结构
CN109872987B (zh) * 2019-03-08 2022-03-08 中国科学院微电子研究所 带有散热结构的系统封装板卡结构及其制作方法
CN110060991B (zh) * 2019-04-26 2021-06-22 广东美的制冷设备有限公司 智能功率模块及空调器
CN210379040U (zh) * 2019-06-22 2020-04-21 深圳市奕通功率电子有限公司 一种功率模块
DE102019120886A1 (de) * 2019-08-02 2021-02-04 Infineon Technologies Ag Halbleitergehäuse mit einem Hohlraum in seinem Gehäusekörper
US20210082790A1 (en) * 2019-09-18 2021-03-18 Alpha And Omega Semiconductor (Cayman) Ltd. Power semiconductor package having integrated inductor and method of making the same
CN110756943A (zh) * 2019-09-20 2020-02-07 西安中车永电电气有限公司 一种提高焊接质量的底板结构及其焊接方法
CN110620094A (zh) * 2019-10-12 2019-12-27 芜湖启迪半导体有限公司 一种功率半导体器件的封装结构及其封装工艺
CN110931448A (zh) * 2019-11-22 2020-03-27 瑞能半导体科技股份有限公司 引线框架、半导体器件以及电路装置
US20210175155A1 (en) * 2019-12-06 2021-06-10 Alpha And Omega Semiconductor (Cayman) Ltd. Power module having interconnected base plate with molded metal and method of making the same
CN113013106B (zh) * 2019-12-19 2023-08-11 广东美的白色家电技术创新中心有限公司 智能功率模块及其制备方法、包含该智能功率模块的电器
CN111599696A (zh) * 2020-05-28 2020-08-28 矽磐微电子(重庆)有限公司 半导体模块封装方法及半导体模块
US11342275B2 (en) * 2020-10-22 2022-05-24 Nxp Usa, Inc. Leadless power amplifier packages including topside terminations and methods for the fabrication thereof
CN112645279B (zh) * 2020-12-23 2023-09-05 东南大学 一种mems风速风向传感器的封装方法
CN112864113B (zh) * 2021-02-10 2025-08-29 华为数字能源技术有限公司 功率器件、功率器件组件与相关装置
CN113161337B (zh) * 2021-03-29 2025-05-16 广东汇芯半导体有限公司 智能功率模块
US11984429B2 (en) 2021-09-30 2024-05-14 Nxp Usa, Inc. Leadless power amplifier packages including topside termination interposer arrangements and methods for the fabrication thereof
CN114062447B (zh) * 2021-11-30 2023-08-18 中国工程物理研究院激光聚变研究中心 应用于低湿度环境的超薄湿敏传感器及其制备方法
CN115623665A (zh) * 2022-10-21 2023-01-17 苏州悉智科技有限公司 功率模块封装结构及其制造方法
CN116454028A (zh) * 2023-06-14 2023-07-18 赛晶亚太半导体科技(浙江)有限公司 一种高效散热的igbt模块及其制备方法
KR20250038472A (ko) * 2023-09-12 2025-03-19 (주)라온반도체 인쇄 회로 기판을 적용한 파워 모듈

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002246515A (ja) * 2001-02-20 2002-08-30 Mitsubishi Electric Corp 半導体装置
US7405468B2 (en) * 2003-04-11 2008-07-29 Dai Nippon Printing Co., Ltd. Plastic package and method of fabricating the same
TWI257164B (en) * 2005-04-01 2006-06-21 Cyntec Co Ltd Package structure having mixed circuit and complex substrate
TWI284407B (en) * 2005-11-03 2007-07-21 Cyntec Co Ltd Package device with electromagnetic interference shield
US8018056B2 (en) * 2005-12-21 2011-09-13 International Rectifier Corporation Package for high power density devices
JP4760585B2 (ja) * 2006-07-18 2011-08-31 三菱電機株式会社 電力用半導体装置
KR101221807B1 (ko) * 2006-12-29 2013-01-14 페어차일드코리아반도체 주식회사 전력 소자 패키지
US8129225B2 (en) * 2007-08-10 2012-03-06 Infineon Technologies Ag Method of manufacturing an integrated circuit module
US7875962B2 (en) * 2007-10-15 2011-01-25 Power Integrations, Inc. Package for a power semiconductor device
WO2009081723A1 (ja) * 2007-12-20 2009-07-02 Fuji Electric Device Technology Co., Ltd. 半導体装置およびその製造方法
KR101524544B1 (ko) * 2008-03-28 2015-06-02 페어차일드코리아반도체 주식회사 펠티어 효과를 이용한 열전기 모듈을 포함하는 전력 소자패키지 및 그 제조 방법
KR101505552B1 (ko) * 2008-03-31 2015-03-24 페어차일드코리아반도체 주식회사 복합 반도체 패키지 및 그 제조방법
WO2009125779A1 (ja) * 2008-04-09 2009-10-15 富士電機デバイステクノロジー株式会社 半導体装置及び半導体装置の製造方法
EP2709149A4 (en) * 2011-05-13 2015-08-05 Fuji Electric Co Ltd SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREFOR
KR101222831B1 (ko) * 2011-09-16 2013-01-15 삼성전기주식회사 전력 모듈 패키지
CN103430307B (zh) * 2012-02-13 2016-04-27 松下知识产权经营株式会社 半导体装置及其制造方法

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