TW201507159A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a first source configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage source, and a second source configured to Connecting a second power rail to a second impurity region, the second power rail is coupled to a second voltage source, the first and second voltage sources are different; and a gate is located at the first and second a first drain region on the first impurity region; a second drain electrode on the second impurity region; and an interconnect line connected to the first drain region The second drain, the interconnect forms at least one closed loop.

Description

Semiconductor device and method of manufacturing same

The priority of the Korean Patent Application No. 61-845,555, filed on July 12, 2013, to the USPTO, and the Korean Patent Application No. 10-2013-0126065, filed on October 22, 2013, to the Korean Intellectual Property Office, The contents of each case are incorporated into the case as a whole by reference.

field

Specific examples are exemplified in relation to a semiconductor device and/or a method of manufacturing the same.

Related technical description

Electromigration (EM) is a phenomenon in which an electrode atom moves by, for example, a carrier in a line. The movement of the electrode atoms may create voids in the line, thereby degrading the conductivity of the wire.

Therefore, research is being actively carried out to reduce electromigration.

summary

The aspect exemplifying a specific example provides a semiconductor device having reduced electromigration.

Examples of specific examples are also provided with reduced electromigration A method of manufacturing a semiconductor device.

However, the aspects exemplifying the specific examples are not limited to the ones listed in the present case. The above-described and other aspects of the specific embodiments will be more apparent from the ordinary skill in the art of the invention.

According to at least one exemplary embodiment, there is provided a semiconductor device comprising: a first source configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage a second source, configured to connect a second power rail to a second impurity region, the second power rail coupled to a second voltage source, the first and second voltage sources being different; a gate on the first and second impurity regions; a first drain on the first impurity region; a second drain on the second impurity region; and an interconnection a line connected to the first drain and the second drain, the interconnect forming at least one closed loop.

According to another illustrative embodiment, there is provided a semiconductor device comprising: a first transistor; a second transistor different from the first transistor; and an interconnect connected to the first And the respective output terminals of the second transistor and a circuit component, the interconnect forming at least one closed loop.

According to another illustrative embodiment, there is provided a semiconductor device comprising: an inverter configured to invert a voltage level of an input signal and output the input signal having the inverted voltage level; a circuit component configured to receive an output of the inverter; and an interconnect configured to provide the output of the inverter to the circuit component, the interconnect The line forms at least one closed loop.

According to another illustrative embodiment, there is provided a method of fabricating a semiconductor device, the method comprising: fabricating a semiconductor device using a standard unit, wherein the standard unit comprises: a PMOS transistor; an NMOS transistor; and an interconnect Connected to the PMOS transistor and the respective output terminals of the NMOS transistor and a circuit component, the interconnect forming at least one closed loop.

At least one exemplary embodiment discloses a semiconductor device including an input line, a circuit component, and an interconnect having at least one closed loop component coupled to a plurality of transistors, the interconnect The plurality of transistors are configured to selectively connect the input line to the circuit component.

At least another exemplary embodiment discloses a semiconductor device including an input line, a circuit component, and an interconnect coupled to a plurality of transistors, the plurality of transistors being configured along the interconnect Applying a first current in a first direction and applying a second current in a second direction of the interconnect, the interconnect and the plurality of transistors being configured to selectively connect the input line to The circuit component.

1, 2, 3, 4‧‧‧ semiconductor devices

5, 6, 7, 8, 9a‧‧‧ semiconductor devices

12.14‧‧‧ impurity area

16‧‧‧Device isolation

17‧‧‧Source area

18‧‧‧Bungee area

20‧‧‧ gate insulation

21‧‧‧ spacers

22‧‧‧ gate

24a, 24b‧‧‧ source

26a, 26b‧‧‧汲

28, 38‧‧‧Interface insulating film

32‧‧‧gate contacts

34‧‧‧Power rail contacts

36‧‧‧汲pole contacts

42‧‧‧ distribution line

44, 46‧‧‧ energy rail

52‧‧‧Input contacts

62‧‧‧ input line

64‧‧‧Interconnection lines

64a, 64b, 64e, 64f‧‧‧ interconnects

64c, 64g‧‧‧ bridge wiring

64d, 64h‧‧‧ bridge joints

65, 67, 69‧‧‧ contacts

66a, 66b‧‧‧ interconnection

68a, 68b, 68c‧‧‧ interconnection lines

72‧‧‧ circuit components

91a, 91b‧‧‧ bungee

92‧‧‧汲pole contacts

96‧‧‧Interconnection lines

100‧‧‧ active layer

101‧‧‧Device isolation

102‧‧‧Interface insulating film

115‧‧‧ spacers

120‧‧‧Interface

125‧‧‧ recesses

132‧‧‧ gate insulation

142‧‧‧Work function control layer

161‧‧‧Source/bungee area

162‧‧‧ gate

192‧‧ ‧ gate structure

900‧‧‧Wireless communication device

910‧‧‧ display

911‧‧‧Antenna

913‧‧‧ Receiver (RCVR)

915‧‧‧Transmitter (TMTR)

920‧‧‧Digital Section

922‧‧‧Video Processor

924‧‧‧Application Processor

926‧‧‧Multicore processor

928‧‧‧Display Processor

930‧‧‧CPU

932‧‧‧External bus interface

934‧‧‧Data machine processor

940‧‧‧External memory

1000‧‧‧System Level Wafer (SoC) System

1001‧‧‧Application Processor

1010‧‧‧CPU

1012, 1016‧‧ ‧ cluster

1014, 1014a-d‧‧‧ core

1018, 1018a-d‧‧‧ core

1019‧‧‧Power Management Unit

1020‧‧‧Multimedia system

1030‧‧‧ Busbar

1040‧‧‧ memory system

1050‧‧‧ peripheral circuits

1060‧‧‧ Dynamic Random Access Memory

1100‧‧‧Electronic system

1110‧‧‧ Controller

1120‧‧‧I/O devices

1130‧‧‧ memory device

1140‧‧ interface

1150‧‧ ‧ busbar

1200‧‧‧ Tablet PC

1300‧‧‧Note Computer

1400‧‧‧Smart mobile phone

BL‧‧‧ bit line

BLb‧‧‧complementary bit line

CB‧‧‧ wafer ball

DT‧‧‧ drive transistor

F1, F2‧‧‧ active fin structure

I1, I2, I3‧‧‧ current

IVN1, IVN2‧‧‧ Inverter

JB‧‧‧Junction ball

MN1-MN8‧‧‧NMOS transistor

MP1-MP8‧‧‧ PMOS transistor

PB‧‧‧Packing ball

PD1, PD2‧‧‧ pull-down transistor

PS‧‧‧Package substrate

PS1, PS2‧‧‧ pass transistor

PS1, PS2‧‧‧Selective transistor

PT‧‧‧pass transistor

PU1, PU2‧‧‧ pull-up transistor

RBL‧‧‧Read bit line

RWL‧‧‧Read word line

S100, S110‧‧‧ steps

TR‧‧‧O crystal

VCC‧‧‧ power node

VDD‧‧‧ voltage

VSS‧‧‧ Grounding node, voltage

WL‧‧‧ character line

WWL‧‧‧Write word line

The above-described and other aspects and features of the specific embodiments will be more apparent from the detailed description of the embodiments illustrated in the accompanying drawings. FIG. 1 is a plan view of a semiconductor device according to a specific example; FIG. To illustrate the first and second drains of FIG. 1 and the interconnections FIG. 3 is a cross-sectional view taken along line AA of FIG. 1; FIG. 4 is a circuit diagram of a semiconductor device according to a specific example of FIG. 1; FIG. 5 is a detailed version of the circuit diagram of FIG. FIG. 8 is a partial layout view of a semiconductor device according to an example of a specific example; FIG. 9 is a partial perspective view of a region B1 of FIG. 8; FIG. 10 is a partial perspective view of FIG. FIG. 11 is a partial perspective view of a region B2 of FIG. 10; FIG. 12 is a partial layout view of a semiconductor device according to an exemplary embodiment; and FIG. 13 is a semiconductor device according to an exemplary embodiment. Figure 14 is a layout view of a semiconductor device according to an exemplary embodiment; Figure 15 is a partial perspective view of a region C of Figure 14; Figure 16 is a cross-sectional view taken along line DD of Figure 15; a cross-sectional view taken along line EE of FIG. 15; FIG. 18 is a circuit diagram of a semiconductor device according to an exemplary embodiment; 19 is a circuit diagram of a semiconductor device according to an exemplary embodiment; FIG. 20 is a block diagram of a wireless communication device including a semiconductor device according to an exemplary embodiment; and FIG. 21A is a system-level chip (SoC) including a semiconductor device according to an exemplary embodiment. Figure 21B is a schematic block diagram of the central processing unit (CPU) of Figure 21A; Figure 21C is a diagram of the semiconductor device of Figure 21A after being packaged; Figure 22 is a diagram of a semiconductor including a specific example according to an exemplary embodiment FIG. 23 to FIG. 25 are diagrams showing an example of a semiconductor system to which a semiconductor device according to an exemplary embodiment is applicable; and FIG. 26 is a flow chart showing a method of fabricating a semiconductor device according to an exemplary embodiment. Figure.

Detailed description

Advantages and features of the exemplary embodiments and methods for accomplishing the same are more readily understood by reference to the detailed description of the preferred embodiments. However, the exemplified specific examples may be embodied in many different forms and should not be construed as being limited to the specific examples set forth herein. Rather, the specific examples are provided so that this disclosure will be thorough and complete and the concept of the specific examples will be fully conveyed to those skilled in the art. Scope definition. In the drawings, the thickness of layers and regions are exaggerated to be clear.

It will be understood that when an element or layer is referred to as being "on" or "connected" to another element or layer, Connected to the other element or layer, or an intervening element or layer may be present. In contrast, when an element is referred to as "directly on" another element or "directly connected" to another element or layer, there are no intervening elements or layers. Like numbers throughout the text refer to like elements. The term "and/or" as used in this context includes any and all combinations of one or more of the associated listed items.

Spatial relative terms, such as "beneath", "below", "lower", "above", "upper" The invention may be used in the context of the present invention for ease of description of the relationship of one element or feature and the other element(s) or features(s) as illustrated. It will be appreciated that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is overturned, the component described as "below" or "below" other components or features will be positioned "on" other components or features "above" . Thus, the exemplary terms "below" can include the orientation above and below. The device can be additionally positioned (rotated 90 degrees or rotated in other orientations), and the spatial relative description used in this case can be interpreted accordingly.

The words "a", "an" and "the", and the like, used in the context of the exemplifying the specific examples (particularly in the context of the following patent application) should be interpreted as Including singular and plural, unless otherwise Indicate or clearly contradict the context. The words "comprising", "having", "including" and "containing" shall be interpreted as open words (ie, meaning "including, but not limited to"), Unless otherwise noted.

It will be appreciated that although the terms first, second, etc. may be used to describe various elements in the present disclosure, such elements are not limited to such terms. These terms are only used to distinguish one element from another. Thus, for example, a first element, a first component, or a first block, discussed below, may be termed a second element, a second component, or a second block, without departing from the teachings of the exemplary embodiments.

The specific examples will be described with reference to a perspective view, a cross-sectional view, and/or a plan view, which illustrate a specific example. Thus, the outline of the illustrations may vary depending on manufacturing techniques and/or tolerances. That is, the specific examples are not intended to limit the scope of the specific examples, but all changes and modifications may be caused by process changes. The regions illustrated in the figures are illustrated by way of illustration and the

Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as commonly understood by those of ordinary skill in the art. It is to be understood that any and all of the embodiments, or the exemplified words used in the present invention, are intended to be illustrative only and not to limit the scope of the specific examples, unless otherwise specified. Furthermore, unless otherwise defined, all terms defined in a commonly used dictionary are not to be over-interpreted.

A semiconductor device according to an exemplary embodiment will now be described with reference to Figs.

FIG. 1 is a layout view of a semiconductor device 1 according to a specific example. 2 is a partial layout view of the first and second drain electrodes 26a and 26b and the interconnect line 64 of FIG. Fig. 3 is a cross-sectional view taken along line A-A of Fig. 1. 4 is a circuit diagram of a semiconductor device 1 according to a specific example illustrated in FIG. 1. Figure 5 is a detailed version of the circuit diagram of Figure 4.

An inverter will hereinafter be described as an example of the semiconductor device 1 according to the present exemplary embodiment. However, the semiconductor device 1 is not limited to the inverter.

1 to 5, the semiconductor device 1 includes first and second impurity regions 12 and 14, a gate 22, first and second source electrodes 24a and 24b, first and second drain electrodes 26a and 26b, and interconnections. Line 64.

The first impurity region 12 and the second impurity region 14 may extend in the X direction. The first impurity region 12 and the second impurity region 14 may be formed inside or on the substrate. Here, the substrate on which the first impurity region 12 and the second impurity region 14 are formed inside or above may be a semiconductor substrate. The semiconductor substrate can be formed from one or more semiconductor materials selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP.

In an exemplary embodiment, each of the first impurity region 12 and the second impurity region 14 may be an epitaxial layer formed of a semiconductor material. The epitaxial layer can be formed on, for example, an insulating substrate. In other words, each of the first impurity region 12 and the second impurity region 14 may be formed as an insulator coating (SOI).

a first impurity region 12 and a second impurity region formed as SOIs 14 can reduce the delay time of the operation of the semiconductor device 1.

In the current exemplary embodiment, the first impurity region 12 and the second impurity region 14 may have different conductivity types. In an exemplary embodiment, the first impurity region 12 may include an N-type impurity region, and the second impurity region 14 may include a P-type impurity region.

The gate 22 may be disposed on the first and second impurity regions 12 and 14 and extend in the Y direction. As shown in FIG. 1, the gate 22 may span the first and second impurity regions 12 and 14.

Gate 22 can include a conductive material. In an exemplary embodiment, gate 22 may comprise polysilicon. In some other specific examples, gate 22 can comprise a metal.

A gate insulating layer 20 may be formed between the gate 22 and the first and second impurity regions 12 and 14. The gate insulating layer 20 may be formed of an oxide layer. In some exemplary embodiments, the gate insulating layer 20 may be formed of, but not limited to, -SiO ₂ , HfO ₂ , Al ₂ O ₃ , ZrO ₂ , or TaO ₂ .

The gates 22 can be separated from each other by the device isolation layer 16. A device isolation layer 16 may be formed in the first and second impurity regions 12 and 14. In an exemplary embodiment, device isolation layer 16 can include a shallow trench isolation (STI) layer. However, the device isolation layer 16 is not limited to the STI layer. In an exemplary embodiment, device isolation layer 16 may also include a deep trench isolation (DTI) layer.

The source region 17 may be formed in each of the first and second impurity regions 12 and 14 disposed on one side of each gate 22 . The drain region 18 may be formed in each of the first and second impurity regions 12 and 14 disposed on the other side of each gate 22.

In an exemplary embodiment, the source region 17 and the drain region 18 formed in the first impurity region 12 may include P-type impurities, and the source region 17 and the drain region 18 formed in the second impurity region 14 are formed. An N-type impurity can be included. However, the specific examples are not limited thereto, and the conductivity type may vary.

Spacers 21 may be formed on both sides of each of the gates 22, respectively. In some illustrative embodiments, the spacers 21 can each comprise a layer such as a nitride. In particular, the spacers 21 can each include, but are not limited to, a tantalum nitride (SiN) layer.

In Fig. 3, the spacer 21 is cylindrical. However, the shape of the spacer 21 is not limited to the cylindrical shape. The shape of the spacer 21 can be changed to any shape such as an L shape.

The source region 17, the drain region 18, the gate insulating layer 20, and the gate 22 in each of the first and second impurity regions 12 and 14 may be formed on the transistor TR. Therefore, as described above, it is assumed that the source region 17 and the drain region 18 formed in the first impurity region 12 include P-type impurities and if the source region 17 and the drain region 18 formed in the second impurity region 14 are formed. Including an N-type impurity, a p-type metal oxide semiconductor (PMOS) transistor may be formed on the first impurity region 12, and an n-type metal oxide semiconductor (NMOS) transistor may be formed in the second impurity region 14 on.

In FIGS. 1, 4 and 5, eight PMOS transistors MP1 to MP8 are formed on the first impurity region 12, and eight NMOS transistors MN1 to MN8 are formed on the second impurity region 14. However, the specific examples are not limited to this. The number of transistors formed can vary depending on the performance of the inverter.

The first source 24a may be formed on one side of each gate 22 to contact the source region 17 formed in the first impurity region 12. The first source 24a can be coupled to the first power rail 44 by a power rail junction 34 that is applied with a first voltage VDD. Accordingly, the first source 24a can be electrically connected to the first power rail 44 (which is applied with the first voltage VDD) to the source region 17 formed in the first impurity region 12.

The second source 24b may be formed on one side of each of the gates 22 to contact the source region 17 formed in the second impurity region 14. The second source 24b can be connected to the second power rail 46 by another power rail contact 34, which is applied with a second voltage VSS. Accordingly, the second source 24b can be electrically connected to the second power rail 46 (which is applied with the second voltage VSS) to the source region 17 formed in the second impurity region 14.

In an exemplary embodiment, the first voltage VDD applied to the first power rail 44 may include a supply voltage, and the second voltage VSS applied to the second power rail 46 may include a ground voltage. However, the specific embodiment is not limited thereto, and the first voltage VDD and the second voltage VSS may be changed. For example, in some other illustrative embodiments, the first voltage VDD applied to the first power rail 44 may include a first power voltage, and the second voltage VSS applied to the second power rail 46 may include less than the first power voltage The second supply voltage.

The first drain 26a may be formed on the other side of each gate 22 to contact the drain region 18 formed in the first impurity region 12. The first drain 26a can be connected to the interconnect 64 by a drain contact 36.

A second drain 26b may be formed on the other side of each gate 22 to contact the drain region 18 formed in the second impurity region 14. Second bungee 26b It can be connected to the interconnect 64 by another drain contact 36.

As shown in FIG. 3, the first and second source electrodes 24a and 24b can isolate the first and second drain electrodes 26a and 26b by the first interface insulating film 28. The drain contact 36 can isolate the first and second power rails 44 and 46, the gate contact 32, the distribution line 42, and the input contact 52 by the second interface insulating film 38.

The gate 22 can be electrically connected to the distribution line 42 by a gate contact 32. The distribution line 42 extending in the X direction can be electrically connected to the input line 62 by the input contact 52.

In an exemplary embodiment, input line 62, input contact 52, distribution line 42, gate contact 32, interconnect line 64, and drain contact 36 may comprise a conductive material. The electrically conductive material can be, but is not limited to, a metal.

In an exemplary embodiment, the input line 62 and the interconnect line 64 may be formed at the same height. Further, the distribution line 42 and the first and second power rails 44 and 46 may be formed at the same height. Here, the input line 62 and the interconnect line 64 may be formed higher than the distribution line 42 and the first and second power rails 44 and 46 above the input contact 52.

The gate 22, the first and second sources 24a and 24b, and the first and second drains 26a and 26b may be formed at the same height. Here, the distribution line 42 and the first and second power rails 44 and 46 may be formed to be higher than the gate 22, the first and second sources 24a and 24b, and the first and second drains 26a and 26b. The height of the pole contact 32 or the height of the power rail junction 34.

The input line 62 and the interconnect line 64 may be formed to be higher than the gate electrode 22, the first and second source electrodes 24a and 24b, and the first and second drain electrodes 26a and 26b above the drain contact 36. Therefore, the height of the drain contact 36 can be greater than the gate connection The height of point 32 or the height of power rail junction 34.

Circuit component 72 can be electrically connected to interconnect line 64. Although not explicitly shown, circuit component 72 can be connected to interconnect 64 by a contact (not shown) formed as a via, such as a portion of interconnect 64 being The X direction extends and can be connected to circuit component 72. That is, in the current illustrative embodiment, circuit component 72 can be coupled to interconnect 64 in any manner.

Circuit component 72 can include passive circuit components and active circuit components. Examples of passive circuit components can include, but are not limited to, resistors, capacitors, and inductors. Examples of active circuit components can include, but are not limited to, diode transistors.

Referring to FIG. 4, the semiconductor device 1 may be embodied as an inverter driven by a first voltage VDD and a second voltage VSS. Thus, the input signal provided to input line 62 can have its voltage level reversed by input line 62 and then output to interconnect line 64 accordingly. The output signal can be provided to circuit component 72 via interconnect line 64 that forms a closed loop.

In particular, referring to FIG. 5, the voltage level of the input signal provided to input line 62 is inverted by an inverter comprising eight PMOS transistors MP1 through MP8 and eight NMOS transistors MN1 through MN8. The input signal whose voltage level has been inverted is output as an output signal. The output signal is then provided to component circuit 72 via interconnect 64 forming a closed loop.

In the semiconductor device 1, since the interconnection line 64 forms a closed loop, electromigration in the semiconductor device 1 can be reduced. This will be explained in more detail with reference to Figures 6 and 7.

6 and 7 are views showing the effects of the semiconductor device 1 according to the specific example illustrated in Fig. 1.

FIG. 6 is a diagram showing the flow of current in interconnect line 96 - unlike interconnect line 64 of semiconductor device 1 - semiconductor device 9a that does not form a closed loop. Referring to FIG. 6, the current I1 supplied from the first and second drain electrodes 91a and 91b to the drain contact 92 flows in only one direction inside the interconnect line 96. Accordingly, the atoms of the interconnect 96 continuously receive power in one direction (indicated by dashed lines) while the semiconductor device 9a is operating. When the atoms of interconnect 96 continue to receive power in one direction (indicated by dashed lines), the probability that electromigration will create voids within interconnect 96 increases.

However, if the interconnect line 64 forms a closed loop of the semiconductor device 1 as shown in FIG. 7, the current flows inside the semiconductor device 1 in a dispersed manner. In particular, referring to FIG. 7, in the semiconductor device 1, the currents I2 and I3 supplied from the first and second drain electrodes 26a and 26b to the drain contact 36 flow inside the interconnect line 64 in both directions. Accordingly, the force received by the atoms of the interconnection 64 is reduced as compared with the above-described semiconductor device 9a. In some cases, several atoms of interconnect 64 receive power in both directions (indicated by dashed lines) while semiconductor device 1 is operating. Thus, the probability of electromigration creating voids within interconnect 64 is significantly reduced when interconnect line 96 does not form a closed loop as described above.

A semiconductor device according to another exemplary embodiment will now be described with reference to Figs.

FIG. 8 is a partial layout view of the semiconductor device 2. Figure 9 is a partial perspective view of the area B1 of Figure 8. For the sake of simplicity, the redundant elements already explained will be omitted. Description, the current specific examples will mainly focus on the differences between the description and Figures 1-5.

Referring to FIGS. 8 and 9, the interconnection lines (66a, 66b) of the semiconductor device 2 may include a first interconnection line 66a and a second interconnection line 66b.

The first interconnect 66a can be connected to the first and second drains 26a and 26b by a drain contact 36. The first interconnect 66a can be U-shaped. In particular, the first interconnect 66a can be shaped like a "U" lying down.

The second interconnect line 66b can be connected to the first interconnect line 66a by the first contact 65. The second interconnect line 66b may extend in the Y direction. Since the first interconnect 66a is connected to the second interconnect 66b by the first contact 65, the closed loop (66a, 66b) of the semiconductor device 2 according to the present specific example can form a closed loop.

In an exemplary embodiment, the second interconnect line 66b may be formed to be higher than the first interconnect line 66a. In particular, the second interconnect line 66b may be formed to be higher than the first interconnect line 66a by the height of the first contact 65. Although the interface insulating film is omitted from FIG. 9 for ease of understanding, the first and second interconnecting lines 66a and 66b and the first contact 65 may be surrounded by an interlayer insulating film.

In the semiconductor device 2, since the interconnect lines (66a, 66b) form a closed loop, the electromigration within the interconnect lines (66a, 66b) can be reduced as described above. Also, in the semiconductor device 2, a separate line not connected to the first interconnect line 66a may be additionally formed under the second interconnect line 66b.

A semiconductor device according to an exemplary embodiment will now be described with reference to Figs.

FIG. 10 is a partial layout view of the semiconductor device 3. Figure 11 is Figure 10 A partial perspective view of area B2. The current specific examples will mainly focus on the differences between the description and the previous specific examples.

Referring to FIGS. 10 and 11, the interconnection lines (68a, 68b, 68c) of the semiconductor device 3 may include a third interconnection 68a, a fourth interconnection 68b, and a fifth interconnection 68c.

The third interconnect 68a can be connected to the first and second drains 26a and 26b by a drain contact 36. The third interconnect 68a may extend toward one side of the first and second drains 26a and 26b.

The third interconnect 68a can be U-shaped. In particular, the third interconnect 68a can be shaped like a "U" lying down.

The fourth interconnect line 68b may extend in the X direction. The fourth interconnect line 68b may extend toward the other of the first and second drains 26a and 26b.

The fourth interconnect 68b can be connected to the third interconnect 68a by a second contact 67. In an exemplary embodiment, the fourth interconnect 68b may be formed as a third interconnect 68a. In particular, the fourth interconnect 68b may be formed to be higher than the third interconnect 68a by the height of the second contact 67.

The fifth interconnect 68c can be connected to the fourth interconnect 68b by a third contact 69. The fifth interconnect 68c may extend in the Y direction. Since the fifth interconnect 68c is connected to the fourth interconnect 68b by the third contact 69 and the fourth interconnect 68b is connected to the third interconnect 68a by the second contact 67, according to the current The interconnection lines (68a, 68b, 68c) of the semiconductor device 3 of the specific example can form a closed loop.

In an exemplary embodiment, the fifth interconnect 68c may be formed to be higher than the fourth interconnect 68b. Specifically, the fifth interconnect 68c can be formed to be The fourth interconnect 68b is elevated above the third junction 69. Although the interface insulating film is omitted from FIG. 11 for ease of understanding, the third to fifth interconnect lines 68a to 68c and the second and third contacts 67 and 69 may be surrounded by an interlayer insulating film.

In the semiconductor device 3, since the interconnect lines (68a, 68b, 68c) form a closed loop, the electromigration within the interconnect lines (68a, 68b, 68c) can be reduced as described above. Further, in the semiconductor device 3, a separate line not connected to the third interconnect line 68a may be additionally formed under the fourth and fifth interconnect lines 68b and 68c.

FIG. 12 is a partial layout view of a semiconductor device 4 according to another exemplary embodiment. The current specific examples will mainly focus on the differences between the description and the previous specific examples.

In the layout of Fig. 12, for ease of explanation, among the elements of Fig. 1, only the first and second power rails 44 and 46 and interconnection lines (64a, 64b) are shown. In other words, the gate 22, the first and second sources 24a and 24b, the first and second drains 26a and 26b, etc. formed between the first power rail 44 and the second power rail 46 of FIG. 12 is omitted.

Referring to FIG. 12, the first power rail 44 of the semiconductor device 4 according to the present specific example may also be disposed under the second power rail 46. The interconnect lines (64a, 64b) may include a sixth interconnect line 64a and a seventh interconnect line 64b that are spaced apart from each other and form respective closed loops.

As described above, a plurality of PMOS transistors and a plurality of NMOS transistors may be formed between the first power rail 44 and the second power rail 46 located below the sixth interconnect line 64a. In addition, a plurality of PMOS transistors and a plurality of NMOS transistors may be formed in the first electricity under the seventh interconnect line 64b. The energy rail 44 is between the second energy rail 46.

The bridge line 64c can connect the sixth interconnect line 64a and the seventh interconnect line 64b. In particular, the bridge wire 64c can be connected to the sixth connection line 64a and the seventh interconnection line 64b by the bridge contact 64d. The bridge line 64c may be formed to be higher than the sixth interconnect line 64a and the seventh interconnect line 64b. In particular, the bridge wire 64c may be formed to be higher than the sixth interconnecting wire 64a and the seventh interconnecting wire 64b by the height of the bridge contact 64d.

The bridge wire 64c may connect a plurality of transistors formed between the first power rail 44 and the second power rail 46 under the sixth interconnect line 64a in series to the first portion formed under the seventh interconnect line 64b. A plurality of transistors between the power rail 44 and the second power rail 46. In other words, the configuration of FIG. 12 can be made into a semiconductor device 4 including more transistors than the semiconductor devices 1 to 3.

Although three bridge wires 64c are connected to the sixth interconnect line 64a and the seventh interconnect line 64b in FIG. 12, the specific examples are not limited thereto. The number of bridge wires 64c can vary depending on the desired.

Further, although the sixth interconnect line 64a and the seventh interconnect line 64b which are spaced apart from each other and form respective closed loops are arranged in the Y direction in FIG. 12, the specific examples are not limited thereto. In an exemplary embodiment, the sixth interconnect line 64a and the seventh interconnect line 64b which are spaced apart from each other and form respective closed loops may also be arranged in the X direction.

FIG. 13 is a partial layout view of a semiconductor device 5 according to another exemplary embodiment. The current specific examples will mainly focus on the differences between the description and the previous specific examples.

In the layout of Fig. 13, for ease of explanation, among the elements of Fig. 1, only the first and second power rails 44 and 46 and interconnection lines (64a, 64b) are shown. In other words, the gate 22, the first and second sources 24a and 24b, the first and second drains 26a and 26b, etc. formed between the first power rail 44 and the second power rail 46 of FIG. 13 is omitted.

Referring to FIG. 13, the interconnection lines (64e, 64f) of the semiconductor device 5 may include an eighth interconnection line 64e forming a closed loop and a ninth interconnection line 64f in a U-shape.

As described above, a plurality of PMOS transistors and a plurality of NMOS transistors may be formed between the first power rail 44 and the second power rail 46 located below the eighth interconnect line 64e. In addition, a plurality of PMOS transistors and a plurality of NMOS transistors may be formed between the first power rail 44 and the second power rail 46 located below the ninth interconnect line 64f.

The bridge line 64g can connect the eighth interconnect line 64e and the ninth interconnect line 64f. In particular, the bridge wire 64g can be connected to the eighth connection line 64e and the ninth interconnection line 64f by the bridge contact 64h. The bridge line 64g may be formed to be higher than the eighth interconnect line 64e and the ninth interconnect line 64f. In particular, the bridge wire 64g may be formed to be higher than the eighth interconnect line 64e and the ninth interconnect line 64f by the height of the bridge contact 64h.

The bridge wire 64g may connect a plurality of transistors formed between the first power rail 44 and the second power rail 46 located under the eighth interconnect line 64e in series to the first portion formed under the ninth interconnect line 64f. A plurality of transistors between the power rail 44 and the second power rail 46. In other words, the configuration of FIG. 13 can be made into a semiconductor device including more transistors than the semiconductor devices 1 to 3. 5.

Although the eighth interconnect line 64e forming the closed loop and the ninth interconnect line 64f forming the U-shape are arranged in the Y direction in FIG. 13, the exemplary embodiment is not limited thereto. In an exemplary embodiment, the eighth interconnect line 64e and the ninth interconnect line 64f may also be arranged in the X direction.

A semiconductor device according to another exemplary embodiment will now be described with reference to Figs.

FIG. 14 is a layout view of a semiconductor device 6 according to a specific example. Figure 15 is a partial perspective view of a region C of Figure 14. Figure 16 is a cross-sectional view taken along line D-D of Figure 15. Figure 17 is a cross-sectional view taken along line E-E of Figure 15.

The case where the semiconductor device 6 includes fin transistors (FinFETs) will be described later as an example. However, the specific examples are not limited to this case. The exemplary embodiment can also be applied to a semiconductor device including a three-dimensional space semiconductor element such as a transistor using a nanowire, instead of a fin transistor.

Referring to FIGS. 14 through 17, the semiconductor device 6 may in turn include first and second active fins F1 and F2 extending in the X direction.

The first and second active fin structures F1 and F2 may protrude from the active layer 100 in the third direction Z. In some exemplary embodiments, the first and second active fin structures F1 and F2 may be formed by partially etching the active layer 100. However, the specific examples are not limited to this.

In at least one exemplary embodiment, the active layer 100 can be a semiconductor substrate. When the active layer 100 is a semiconductor substrate, the semiconductor substrate may be formed of one or more semiconductor materials selected from the group consisting of: Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP.

In at least one exemplary embodiment, active layer 100 can be an epitaxial layer formed of a semiconductor material. Here, the epitaxial layer may be formed on an insulating substrate. In other words, the active layer 100 can be an SOI substrate.

The first and second active fin structures F1 and F2 may extend in the X direction and may be spaced apart from each other in the Y direction.

A pair of first and second active fin structures F1 and F2 may form each group. This is because the two active fin structures F1 and F2 are formed by a dummy gate called a mandrel.

First and second impurity regions 12 and 14 (see FIG. 1) may be formed in the first and second active fin structures F1 and F2.

The device isolation layer 101 may cover the sides of each of the first and second active fin structures F1 and F2. In particular, the device isolation layer 101 may cover the lower portions of each of the first and second active fin structures F1 and F2, as shown in FIGS. 15 and 16. The device isolation layer 101 can be, for example, an insulating layer. More specifically, the device isolation layer 101 may be, but not limited to, a cerium oxide (SiO ₂ ) layer, a cerium nitride (SiN) layer, or a cerium oxynitride (SiON) layer.

In the drawings, the cross-section of each of the first and second active fin structures F1 and F2 may be tapered, that is, may become wider from top to bottom. However, the cross-sectional shape of each of the first and second active fin structures F1 and F2 is not limited to a taper. Each of the first and second active fin structures F1 and F2 may have a quadrangular cross-sectional shape. In other exemplary embodiments, each of the first and second active fin structures F1 and F2 may have a chamfered cross-sectional shape. That is, the angle of each of the first and second active fin structures F1 and F2 may be curved.

The gate structure 192 may extend in the Y direction to form each of the first and second active fin structures F1 and F2. Spacers 115 may be disposed on both sides of the gate structure 192. The spacer 115 may be disposed to extend in the Y direction on each of the first and second active fin structures F1 and F2.

A transistor may be formed in a portion of each of the first and second active fin structures F1 and F2. Each of the transistors may include a gate structure 192, a spacer 115, and a source/drain region 161.

The gate structure 192 may include an interface layer 120, a gate insulating layer 132, a work function control layer 142, and a gate 162 sequentially formed on each of the first and second active fin structures F1 and F2.

The interface layer 120 may be disposed on each of the device isolation layer 101 and the first and second active fin structures F1 and F2 and extend in the Y direction. The interface layer 120 may comprise a low-k material layer having a dielectric constant (k) of 9 or less, such as a hafnium oxide layer (having a dielectric constant of about 4) or a hafnium oxynitride layer (having a thickness of about 4 to 8) The dielectric constant depends on the oxygen atom and nitrogen atom content). Alternatively, the interface layer 120 can be formed from a combination of silicate or the above-described exemplified layers.

A gate insulating layer 132 may be disposed on the interface layer 120. In particular, the gate insulating layer 132 may extend in the Y direction and partially cover the upper portion of each of the first and second active fin structures F1 and F2. As shown in FIG. 17, the gate insulating layer 132 may extend upward along sidewalls of the spacers 115 disposed on both sides of the gate 162. In Fig. 17, the gate insulating layer 132 is shaped as described above because it is formed by a replacement process (or a gate post process). However, the specific embodiment is not limited thereto, and the shape of the gate insulating layer 132 may be changed as desired.

That is, in other exemplary embodiments, the gate insulating layer 132 may be formed by a gate pre-fabrication process. Thus, the gate insulating layer 132 may not extend upward along the sidewall of the spacer 115, as shown in FIG.

The gate insulating layer 132 may be formed of a high-k material. In some exemplary embodiments, the gate insulating layer 132 may be formed of, but not limited to, -HfO ₂ , Al ₂ O ₃ , ZrO ₂ , TaO _{2 ,} or the like.

The work function control layer 142 may be disposed on the gate insulating layer 132. The work function control layer 142 may extend in the Y direction and partially cover the upper portion of each of the first and second active fin structures F1 and F2. Like the gate insulating layer 132, the work function control layer 142 may extend upward along the sidewall of the spacer 115. The work function control layer 142 is shaped as described above because it is formed by a replacement process (or a gate post process). However, the exemplary embodiment is not limited thereto, and the shape of the work function control layer 142 may be changed as desired.

The work function control layer 142 can be a layer for controlling the work function of the transistor. The work function control layer 142 may be at least one of an n-type work function control layer and a p-type work function control layer. When the work function control layer 142 is an n-type work function control layer, it may be, but not limited to, TiAl, TiAIN, TaC, TaAIN, TiC, or HfSi. In some exemplary embodiments, the work function control layer 142 formed on the second active fin structure F2 may include, for example, TiAl, TiAIN, TaC, TaAIN, TiC, or HfSi.

When the work function control layer 142 is a p-type work function control layer, it may include, for example, a metal nitride. In particular, the work function control layer 142 can include at least one of TiN and TaN. More specifically, the work function control layer 142 may be, but not limited to, a single layer formed of TiN or a lower layer of TiN A double layer composed of the upper layer of TaN. In some exemplary embodiments, the work function control layer 142 formed on the first active fin structure F1 may be, but not limited to, a single layer formed of TiN or a double layer composed of a TiN lower layer and a TaN upper layer.

The gate 162 may be disposed on the work function control layer 142. The gate 162 may extend in the Y direction and partially cover the upper portion of each of the first and second active fin structures F1 and F2.

Gate 162 can include a highly conductive material. In some illustrative embodiments, gate 162 can comprise a metal. Examples of metals may include, but are not limited to, Al and W.

A recess 125 may be formed on both sides of the gate structure 192 in each of the first and second active fin structures F1 and F2. The recesses 125 can each have a sloped side wall. Thus, the recess 125 may become wider as the distance from the active layer 100 increases. As shown in FIG. 15, the recess 125 can be wider than the first and second active fin structures F1 and F2.

Source/drain regions 161 may be formed in recesses 125, respectively. In some illustrative embodiments, the source/drain regions 161 may be elevated source/drain regions. That is, the top surface of the source/drain regions 161 may be higher than the top surfaces of the first and second active fin structures F1 and F2. Additionally, source/drain regions 161 may be isolated from gate structure 192 by spacers 115.

In the case of a p-type transistor, the source/drain region 161 may comprise a compressive stress material. The compressive stress material can be a material having a larger lattice constant than Si (such as SiGe). The compressive stress material can enhance carrier mobility in the channel region by applying compressive stress to each of the first and second active fin structures F1 and F2. In some exemplary embodiments, formed in the first main The source/drain region 161 on the flip fin structure F1 may include a compressive stress material.

In the case of an n-type transistor, the source/drain regions 161 may comprise the same material or tensile stress material as the active layer 100. For example, when the active layer 100 includes Si, the source/drain regions 161 may include Si or a material having a smaller lattice constant than Si (such as SiC). In some illustrative embodiments, the source/drain regions 161 formed on the second active fin structure F2 may include tensile stress materials.

In an exemplary embodiment, a recess 125 is formed in each of the first and second active fin structures F1 and F2, and a source/drain region 161 is formed in the recess 125. However, the specific examples are not limited to this. In some other exemplary embodiments, the source/drain regions 161 may be formed in the first and second active fin structures by directly implanting impurities into each of the first and second active fin structures F1 and F2. Within F1 and F2 each.

First and second source electrodes 24a and 24b and first and second drain electrodes 26a and 26b may be formed on the source/drain region 161. Specifically, the first source 24a and the first drain 26a may be formed on the source/drain region 161 formed on the first active fin structure F1, and the second source 24b and the second drain 26b may be It is formed on the source/drain region 161 formed on the second active fin structure F2.

Although only a portion of the interface insulating film 102 is illustrated in FIG. 15 for ease of understanding, the interface insulating film 102 may cover the source/drain regions 161 and the gate structure 192.

In an exemplary embodiment, the plurality of PMOS fin transistors formed on the first active fin structure F1 and the second active fin structure are formed. A plurality of NMOS fin transistors on F2 can form an inverter as described above, see FIG. Other elements of the semiconductor device 6 have been fully described above with reference to FIG. 1, and redundant description thereof will be omitted.

A semiconductor device according to another exemplary embodiment will now be described with reference to FIG.

FIG. 18 is a circuit diagram of the semiconductor device 7.

A 6T static random access memory (SRAM) device including six transistors will be hereinafter described as an example of the semiconductor device 7, but the specific examples are not limited thereto.

Referring to FIG. 18, the semiconductor device 7 may include a pair of first and second inverters INV1 and INV2 connected in parallel between the power supply node VCC and the ground node VSS, and respective ones connected to the first and second inverters INV1. The first and second passivation transistors PS1 and PS2 with the output node of INV2. The first and second passivation transistors PS1 and PS2 may be connected to the bit line BL and the complementary bit line BLb, respectively. The gates of the first and second passivation transistors PS1 and PS2 may be connected to the word line WL.

The first inverter INV1 includes a first pull-up transistor PU1 connected in series and a first pull-down transistor PD1, and the second inverter INV2 includes a second pull-up transistor PU2 connected in series Two pull-down transistors PD2. The first and second pull-up transistors PU1 and PU2 may be PMOS transistors, and the first and second pull-down transistors PD1 and PD2 may be NMOS transistors.

The input node of the first inverter INV1 is connected to the output node of the second inverter INV2, and the input node of the second inverter INV2 is connected to The output node of the first inverter INV1 is such that the first and second inverters INV1 and INV2 form a single latch circuit.

Each of the semiconductor devices 1 to 6 according to the above specific example can be employed as at least one of the first inverter INV1 and the second inverter INV2. In particular, at least one of the first pull-up transistor PU1 and the second pull-up transistor PU2 may be connected to the interconnect line 64 by the first drain 26a (see, for example, FIG. 1) (see, for example, FIG. 1). A plurality of PMOS transistors are formed. In addition, at least one of the first pull-down transistor PD1 and the second pull-down transistor PD2 may be connected to the plurality of interconnect lines 64 (see FIG. 1) by the second drain 26b (see, for example, FIG. 1). NMOS transistor structure.

A semiconductor device according to another exemplary embodiment will now be described with reference to FIG.

19 is a circuit diagram of the semiconductor device 8.

An 8T SRAM device including eight transistors will be hereinafter described as an example of the semiconductor device 8, but the specific examples are not limited thereto.

Referring to FIG. 19, the semiconductor device 8 may include a pair of first and second inverters INV1 and INV2 connected in parallel between the power supply node VCC and the ground node VSS, and are respectively connected to the first and second inverters INV1. First and second selective transistors PS1 and PS2 with an output node of INV2, a driving transistor DT controlled by an output of the first inverter INV1, and a pass transistor connected to an output node of the driving transistor DT PT.

The first and second selection transistors PS1 and PS2 may be connected to the bit line BL and the complementary bit line BLb, respectively. The gates of the first and second select transistors PS1 and PS2 are connectable to the write word line WWL.

The first inverter INV1 includes a first pull-up transistor PU1 and a first pull-down transistor PD1 connected in series, and the second inverter INV2 includes a second pull-up transistor PU2 connected in series with The second pull-down transistor PD2. The first and second pull-up transistors PU1 and PU2 may be p-type field effect transistors (PFETs), and the first and second pull-down transistors PD1 and PD2 may be n-type field effect transistors (NFETs). .

The input node of the first inverter INV1 is connected to the output node of the second inverter INV2, and the input node of the second inverter INV2 is connected to the output node of the first inverter INV1, so that the first and the The two inverters INV1 and INV2 form a single latching circuit.

The driving transistor DT and the pass transistor PT can be used to read data stored in the latch circuit formed by the first inverter INV1 and the second inverter INV2. The gate of the driving transistor DT can be connected to the output node of the first inverter INV1, and the gate of the pass transistor PT can be connected to the read word line RWL. The output of the driving transistor D1 can be connected to the ground node VSS, and the output of the pass transistor PT can be connected to the read bit line RBL.

The circuit arrangement of the semiconductor device 8 makes it possible to access data stored in the SRAM device through two ports, such as a double port.

For example, by selecting the write word line WWL, the bit line BL, and the complementary bit line BLb, it is possible to write data to the latch formed by the first inverter INV1 and the second inverter INV2. Circuit or read data stored in the latching circuit. Further, by selecting the read word line RWL and the read bit line RBL, it is possible to read the material stored in the latch circuit formed by the first inverter INV1 and the second inverter INV2.

In the SRAM device, the operation of reading data through the second frame can be performed independently of the operation of the first frame. Therefore, such operations may not affect the data stored in the latching circuit. In other words, the operation of reading the material stored in the latch circuit and the operation of writing the data to the latch circuit can be performed independently.

Each of the semiconductor devices 1 to 6 according to the above-described specific examples can be utilized as at least one of the first inverter INV1 and the second inverter INV2. In particular, at least one of the first pull-up transistor PU1 and the second pull-up transistor PU2 may be connected to the interconnect line 64 by the first drain 26a (see, for example, FIG. 1) (see, for example, FIG. 1). A plurality of PMOS transistors are formed. In addition, at least one of the first pull-down transistor PD1 and the second pull-down transistor PD2 may be connected to the plurality of interconnect lines 64 (see FIG. 1) by the second drain 26b (see, for example, FIG. 1). NMOS transistor structure.

A wireless communication device including a semiconductor device according to an exemplary embodiment will now be described with reference to FIG.

20 is a block diagram of a wireless communication device 900 including a semiconductor device according to an exemplary embodiment.

Referring to Figure 20, the wireless communication device 900 can be a portable telephone, a smart phone terminal, a cell phone, a personal digital assistant (PDA), a laptop, a video game unit, or several other devices. The device 900 can use code division multiple access (CDMA), time division multiple access (TDMA), such as the Global System for Mobile Communications (GSM), or several other wireless communication standards.

Device 900 can provide two-way communication via a receive path and a transmit path. On the receiving path, the signal sent by one or more base stations can be Line 911 is received and provided to a receiver (RCVR) 913. The RCVR 913 tunes and digitizes the received signals and provides samples to the digital section 120 for further processing. On the transmit path, the transmitter (TMTR) 915 receives the data transmitted from the digital section 120, processes and tunes the data, generates an amplitude modulated signal, and transmits the amplitude modulated signal via antenna 911 to one or more base stations.

Digital section 920 can be implemented by one or more digital signal processors (DSPs), microprocessors, reduced instruction set computers (RISCs), and the like. In addition, digital section 920 can be fabricated on one or more application specific integrated circuits (ASICs) or some other kind of integrated circuits (ICs).

Digital section 920 can include various processing and interface units such as, for example, data processor 934, video processor 922, application processor 924, display processor 928, controller/multi-core processor 926, central A processing unit (CPU) 930, and an external bus interface (EBI) 932.

Video processor 922 can perform graphics application processing. In general, video processor 922 can include any number of processing units or modules for any number of graphics operations. Portions of video processor 922 may be implemented in firmware and/or software. For example, the control unit can be implemented by a firmware and/or software module (such as a program, function, etc.) that performs the functions described herein. The firmware and/or software code can be stored in memory and operated by a processor, such as multi-core processor 926. The memory can be implemented inside or outside the processor.

Video processor 922 can implement a software interface, such as Open Graphics Library (OpenGL), Direct 3D, and the like. CPU 930, along with video processor 922, can operate a series of graphics processing operations. The controller/multi-core processor 926 can include two or three cores. Controller/multi-core processor 926 can be The workload distributes the workload to be processed to two cores and processes the workload simultaneously.

In the drawings, application processor 924 is depicted as an element of digital segment 920. However, the specific examples are not limited to this. In some illustrative embodiments, digital segment 920 can be integrated into an application processor 924 or an application chip.

Data machine processor 934 can perform the operations required to transfer data between RCVR 913 and TMTR 915 and digital segment 920. Display processor 928 can perform the operations required to drive display 910.

The semiconductor devices 1 through 8 can be directly applied to the processors 922, 924, 926, 928, 930, and 934 or can be used as cache memories that operate on the processors 922, 924, 926, 928, 930, and 934.

A system-on-a-chip (SoC) system including a semiconductor device according to an exemplary embodiment will now be described with reference to FIGS. 21A to 21C.

21A is a block diagram of an SoC system 1000 including a semiconductor device in accordance with an exemplary embodiment. 21B is a schematic block diagram of the CPU 1010 of FIG. 21A. 21C is a diagram showing the semiconductor device of FIG. 21A after being packaged.

Referring to FIG. 21A, the SoC system 1000 includes an application processor 1001 and a dynamic random access memory (DRAM) 1060.

The application processor 1001 may include a CPU 1010, a multimedia system 1020, a bus bar 1030, a memory system 1040, and a peripheral circuit 1050.

The CPU 1010 can perform the operations required to drive the SoC system 1000. In some illustrative embodiments, CPU 1010 can be configured to include a plurality of core multi-core environments.

In some illustrative embodiments, CPU 1010 can include a first cluster 1012 and a second cluster 1016, as shown in FIG. 21B.

The first cluster 1012 can be placed within the CPU 1010 and includes n (where n is a natural number) the first core 1014. In FIG. 21B, for ease of explanation, the case where the first cluster 1012 includes four (ie, n=4) first cores 1014a to 1014d will be explained as an example. However, the specific examples are not limited to this case.

The second cluster 1016 can also be placed within the CPU 1010 and include n second cores 1018. The second cluster 1016 can be spaced apart from the first cluster 1012. For ease of explanation, the case where the second cluster 1016 includes four (i.e., n = 4) second cores 1018a to 1018d will be explained as an example. However, the specific examples are not limited to this case.

In FIG. 21B, the number of first cores 1014 included in the first cluster 1012 is equal to the number of second cores 1018 included in the second cluster 1016. However, the specific examples are not limited to this. In some embodiments, the number of first cores 1014 included in the first cluster 1012 can also be different than the number of second cores 1018 included in the second cluster 1016.

Further, in FIG. 21B, only the first cluster 1012 and the second cluster 1016 are placed in the CPU 1010. However, the specific examples are not limited to this. If necessary, a third cluster (not shown) spaced apart from the first and second clusters 1012 and 1016 and including a third core (not shown) may additionally be placed within the CPU 1010.

In the current specific example, the calculated amount per unit time of the first core 1014 included in the first cluster 1012 may be different from the calculated amount per unit time of the second core 1018 included in the second cluster 1016.

In some illustrative embodiments, the first cluster 1012 can be a small cluster and the second cluster 1016 can be a large cluster. In this case, the calculated amount per unit time of the first core 1014 included in the first cluster 1012 may be less than the calculated amount per unit time of the second core 1018 included in the second cluster 1016.

Therefore, the amount of calculation per unit time in the case where all of the first cores 1014 included in the first cluster 1012 are activated to perform an operation may be smaller than all of the second cores 1018 included in the second cluster 1016. The amount of calculation per unit time in the case where an operation is started is started.

The respective calculation amounts per unit time of the (1-1) ^th to (1-4) ^th cores 1014a to 1014d included in the first cluster 1012 may be equal and included in the second cluster 1016 (2-1) The respective calculated amounts per unit time of ^th to (2-4) ^th cores 1018a to 1018d may be equal. That is, it is assumed that the calculation amount per unit time of each of the cores 1114a to 1014d of (1-1) ^th to (1-4) ^th is 10, (2-1) ^th to (2-4) ^th cores 1018a to 1018d The calculation per unit time of each can be 40.

The power management unit 1019 can initiate or deactivate the first cluster 1012 and the second cluster 1016 as needed. In particular, when an operation needs to be performed by the first cluster 1012, the power management unit 1019 can initiate the first cluster 1012 and deactivate the second cluster 1016. Conversely, when an operation needs to be performed by the second cluster 1016, the power management unit 1019 can initiate the second cluster 1016 and deactivate the first cluster 1012. When the required amount of computation can be completely processed by the (1-1) ^th core 1014a, the power management unit 1019 can initiate the first cluster 1014a and deactivate the second cluster 1016. Even within the first cluster 1012, the power management unit 1019 can activate (1-1) ^th core 1014a and deactivate (1-2) ^th to (1-4) ^th cores 1014b through 1014d. In other words, the power management unit 1019 may decide whether to activate the first cluster 1012 and the second cluster 1016 and may also decide whether to activate the (1-1) ^th to (1-4) ^th cores 1014a to 1014d included in the first cluster 1012. Each of each of the (2-1) ^th to (2-4) ^th cores 1018a through 1018d included in the second cluster 1016.

In some illustrative embodiments, power management unit 1019 may initiate by first powering first and second clusters 1012 and/or cores 1014a through 1014d and 1018a through 1018d included in first and second clusters 1012 and 1016. The first and second clusters 1012 and/or the cores 1014a through 1014d and 1018a through 1018d included in the first and second clusters 1012 and 1016. Moreover, the power management unit 1019 can disable the first by turning off power to the first and second clusters 1012 and/or the cores 1014a through 1014d and 1018a through 1018d included in the first and second clusters 1012 and 1016. And the second cluster 1012 and/or the cores 1014a through 1014d and 1018a through 1018d included in the first and second clusters 1012 and 1016.

The power management unit 1019 can only activate a particular cluster 1012 or 1016 and/or cores 1014a through 1014d or 1018a through 1018d included within a particular cluster 1012 or 1016, depending on the operating environment of the SoC system 1000, thereby managing the consumption of the entire SoC system 100. Electricity.

Referring back to FIG. 21A, the multimedia system 1020 can be used to perform various multimedia functions within the SoC system 1000. The multimedia system 1020 can include a 3D engine module, a video codec, a display system, a camera system, a post processor, and the like.

The bus bar 1030 can be used for data communication among the CPU 1010, the multimedia system 1020, the memory system 1040, and the peripheral circuit 1050. In some illustrative embodiments, bus bar 1030 can have a multi-layered structure. In particular, bus bar 1030 can be, but is not limited to, a multi-layer advanced high performance bus (AHB) or a multi-layer advanced scalable interface (AXI).

The memory system 1040 can provide an environment required for the application processor 1001 to connect to an external memory such as the DRAM 1060 and execute at high speed. In some illustrative embodiments, memory system 1040 can include a controller (such as a DRAM controller) required to control external memory, such as DRAM 1060.

The peripheral circuit 1050 can provide the environment required for the SoC system 1000 to be smoothly connected to an external device such as a motherboard. Accordingly, peripheral circuitry 1050 can include various interfaces that initiate connection to external devices of SoC system 1000 to be compatible with SoC system 1000.

The DRAM 1060 can function as an operational memory required for the operation of the application processor 1001. In some illustrative embodiments, DRAM 1060 can be placed external to application processor 1001. In particular, DRAM 1060 may be packaged together in a package-on-package (PoP) form with application processor 1001, as shown in FIG. 21C.

Referring to FIG. 21C, the semiconductor package may include a package substrate PS, a DRAM 1060, and an application processor 1001.

The package substrate PS may include a plurality of package balls PB. The package ball PB can be electrically connected to the wafer ball CB of the application processor 1001 by a signal line in the package substrate PS and can be electrically connected to the signal line in the package substrate PS. Join the ball JB.

The DRAM 1060 can be electrically connected to the bonding ball JB by wire bonding.

The application processor 1001 can be disposed below the DRAM 1060. The wafer ball CB of the application processor 1001 can be electrically connected to the DRAM 1060 by the bonding ball JB.

In FIG. 21A, the DRAM 1060 is placed outside of the application processor 1001. However, the specific examples are not limited to this. The DRAM 1060 can also be placed within the application processor 1001 as necessary.

Any of the semiconductor devices 1 to 8 can be provided as any of the components of the SoC system 1000.

An electronic system including a semiconductor device according to an exemplary embodiment will now be described with reference to FIG.

FIG. 22 is a block diagram showing an electronic system 1100 including a semiconductor device in accordance with an exemplary embodiment.

Referring to FIG. 22, the electronic system 1100 can include a controller 1110, an input/output (I/O) device 1120, a memory device 1130, an interface 1140, and a bus bar 1150. The controller 1110, the I/O device 1120, the memory device 1130, and/or the interface 1140 may be connected to each other by a bus bar 1150. Bus 1150 can serve as a path for transmitting data.

The controller 1110 can include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic capable of performing similar functions of the microprocessor, digital signal processor, and microcontroller functions. The I/O device 1120 can include a small numeric keypad (keypad) and a keyboard. And a display device. The memory device 1130 can store data and/or instructions. The interface 1140 can be used to transmit data to or receive data from a communication network. Interface 1140 can be a wired or wireless interface. In one example, interface 1140 can include an antenna or a wired or wireless transceiver.

Although not shown in the drawings, electronic system 1100 can be an operational memory that enhances operation of controller 1110, and can also include high speed DRAM or SRAM. Here, any of the semiconductor devices 1 to 8 can be utilized as a memory. Further, any of the semiconductor devices 1 to 8 may be disposed within the memory device 1130 or within the controller 1110 or the I/O device 1120.

The electronic system 1100 can be applied to nearly all kinds of electronic products capable of transmitting or receiving information in a wireless environment, such as PDAs, portable computers, network tablets, wireless phones, mobile phones, digital music players, memory cards, and the like.

23 to 25 are diagrams showing an example of a semiconductor system to which a semiconductor device according to an exemplary embodiment can be applied.

FIG. 23 illustrates a tablet personal computer (PC) 1200, FIG. 24 illustrates a notebook computer 1300, and FIG. 25 illustrates a smart phone 1400. As listed in the present case, at least one of the semiconductor devices 1 to 8 according to the above-described specific examples can be used for the tablet PC 1200, the notebook computer 1300, and the smart phone 1400.

The semiconductor devices 1 to 8 - as listed in the present case - can also be applied to various IC devices other than those listed in the present case. That is, when the tablet PC 120, the notebook computer 1300, and the smart phone 1400 have been described as an example of a semiconductor system according to a specific example as described above, according to a specific example Examples of the semiconductor system are not limited to the tablet PC 1200, the notebook computer 1300, and the smart phone 1400. In some exemplary embodiments, the semiconductor system can be provided as a computer, a super mobile PC (UMPC), a workstation, a web-based computer, a PDA, a portable computer, a wireless telephone, a mobile phone, an e-book, and a portable type. Multimedia player (PMP), portable game console, navigation device, black box, digital camera, 3-degree space TV, digital audio recorder, digital audio player, digital image recorder, digital video player, digital video Recorders, digital video players, and more.

A method of manufacturing a semiconductor device according to an exemplary embodiment will now be described with reference to FIG.

FIG. 26 is a flow chart showing a method of manufacturing a semiconductor device according to an exemplary embodiment.

Referring to Fig. 26, a standard unit is provided (operation S100). The standard unit may have any of the layouts of the semiconductor devices 1 to 8. In particular, the standard unit provided may include an inverter consisting of a plurality of PMOS transistors and a plurality of NMOS transistors and interconnects connected to the output terminals of the inverter and forming a closed loop. .

Next, the semiconductor device is manufactured using the supplied standard unit (operation S110). In particular, deposition processes, etching processes, and the like are performed using standard units provided, on semiconductor substrates using standard units provided. As a result, any of the semiconductor devices 1 to 8 can be manufactured.

In summarizing the detailed description, those skilled in the art will appreciate that numerous variations and modifications can be made to the exemplary embodiments without substantial escape. Therefore, the disclosed exemplary embodiments are only in a general and descriptive sense. Use rather than limit purpose.

1‧‧‧Semiconductor device

12.14‧‧‧ impurity area

22‧‧‧ gate

24a, 24b‧‧‧ source

26a, 26b‧‧‧汲

32‧‧‧gate contacts

34‧‧‧Power rail contacts

36‧‧‧汲pole contacts

42‧‧‧ distribution line

44, 46‧‧‧ energy rail

52‧‧‧Input contacts

62‧‧‧ input line

64‧‧‧Interconnection lines

Claims (20)

A semiconductor device comprising: a first source configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage source; a second source Is configured to connect a second power rail to a second impurity region, the second power rail coupled to a second voltage source, the first and second voltage sources being different; a gate located at the same a first and second impurity regions; a first drain on the first impurity region; a second drain on the second impurity region; and an interconnect line connected to the first A drain and the second drain form the interconnect to form at least one closed loop. The semiconductor device of claim 1, wherein the interconnect is higher than the first and second sources, the gate, and the first and second drains. The semiconductor device of claim 1, wherein the gate extends in a first direction, and the interconnect includes a first interconnect portion that is U-shaped, and a second portion that extends in the first direction An interconnect portion that is higher than the first interconnect portion. The semiconductor device of claim 3, wherein the first interconnect portion further comprises a third mutual extension extending toward one side of the first and second drains a wiring portion, and a fourth interconnect portion extending toward the other side of the first and second drains, the fourth interconnect portion being higher than the third interconnect portion. The semiconductor device of claim 1, wherein the first impurity region comprises an N-type impurity region, and the second impurity region comprises a P-type impurity region. The semiconductor device of claim 1, wherein the first voltage source is configured to provide a supply voltage, the second voltage source configured to provide a ground voltage. The semiconductor device of claim 1, further comprising: an active fin structure protruding from a substrate, wherein the first and second impurity regions are located within the active fin structure. The semiconductor device of claim 7, further comprising: a gate insulating layer between the gate and the active fin structure; and a spacer on the active fin structure and located at the gate On one side of the spacer, the gate insulating layer extends along a sidewall of the spacer. The semiconductor device of claim 1, further comprising: a bridge line, and the interconnect line includes a first interconnect portion forming a first closed loop, and a portion spaced apart from the first interconnect portion Second interconnect The second interconnect portion forms a second closed loop that is connected to the first interconnect portion and the second interconnect portion. The semiconductor device of claim 9, wherein the bridge line is higher than the first and second interconnect portions. The semiconductor device of claim 1, further comprising: another interconnect line connected to the first drain and the second drain, the other interconnect is U-shaped; and a bridge connection The interconnect line forming the at least one closed loop and the other interconnect line being U-shaped. A semiconductor device comprising: a first transistor; a second transistor different from the first transistor; and an interconnect connected to each of the first and second transistors The output terminal and a circuit component are formed, and the interconnection forms at least one closed loop. The semiconductor device of claim 12, wherein the first transistor comprises a p-type metal oxide semiconductor (PMOS) transistor, the second transistor comprising an n-type metal oxide semiconductor (NMOS) transistor. The semiconductor device of claim 12, wherein the source of the first transistor is configured to receive a first voltage, the source of the second transistor being configured to receive a second voltage different than the first voltage. The semiconductor device of claim 14, wherein the first voltage comprises a supply voltage and the second voltage comprises a ground voltage. The semiconductor device of claim 12, wherein the circuit component comprises a resistor, At least one of a capacitor, an inductor, a diode, and a transistor. The semiconductor device of claim 12, wherein the first transistor and the second transistor are connected in series between a first power rail and a second power rail. The semiconductor device of claim 17, wherein the first transistor comprises a plurality of first transistors connected in parallel, the second transistors comprising a plurality of second transistors connected in parallel. The semiconductor device of claim 17, wherein the first power rail is configured to receive a supply voltage, the second power rail configured to receive a ground voltage. The semiconductor device of claim 12, wherein the semiconductor device is an inverter.