TW201344881A - Semiconductor integrated structure - Google Patents

Abstract

The present invention provides an integrated structure including a substrate, an ILD layer, a transistor and a resistor. The substrate includes a resistor region and an active region. The ILD layer is disposed directly on the substrate. The transistor is disposed in the active region in the ILD layer wherein the transistor includes a metal gate. The resistor is disposed in the resistor region above the ILD layer, wherein the resistor directly contacts the ILD layer.

Description

Semiconductor integrated structure

The present invention relates to an integrated structure of a semiconductor, and more particularly to an integrated structure of a semiconductor, the structure of which can simultaneously integrate a transistor of a metal gate and a resistor.

In the semiconductor industry, in order to improve the operational efficiency of the transistor, there has been a way of using metal as a transistor to control the gate. The metal gate has the advantages of low resistance and no depletion effect, and can improve the shortcomings such as poor operation performance caused by the use of high-resistance polysilicon material in the conventional gate. The metal gate can be roughly divided into a gate first process and a gate last process, wherein the back gate process is in accordance with the thermal budget of the metal material and provides a wider material selection. Gradually replaced the front gate process.

In addition, in the integrated circuit, it is often necessary to add settings of other circuit components such as resistors to perform functions such as voltage stabilization or noise filtering. The main body of the resistor is generally made of polycrystalline germanium, doped regions or metal oxides.

Due to the high complexity of the integrated circuit process and the high precision of various component products, in addition to trying to improve the process technology, the demand for process integration is also an important part in the pursuit of improvement in yield. Reduce process steps while increasing productivity. Therefore, there is still a need in the industry for a method of fabricating a transistor that successfully integrates a resistor and has a metal gate.

According to an embodiment of the invention, the present invention provides an integrated structure comprising a substrate, an inner dielectric layer, a transistor, and a resistor. A resistive region and an active region are defined on the substrate. The inner dielectric layer directly covers the substrate. The transistor is disposed in the active region in the inner dielectric layer, and the transistor includes a metal gate. A resistor is disposed in the resistive region on the inner dielectric layer and the resistor directly contacts the inner dielectric layer.

According to another embodiment of the present invention, the present invention provides an integrated structure including a substrate, an inner dielectric layer, a transistor, a resistor, a dummy resistor, and a contact plug. The substrate defines a resistive region and an active region. The inner dielectric layer directly covers the substrate. The transistor is disposed in the active region in the inner dielectric layer, and the transistor includes a metal gate. The resistor is disposed in the resistive region on the inner dielectric layer and directly contacts the inner dielectric layer. The dummy resistor is disposed in the resistive region in the inner dielectric layer, and at least one metal layer is disposed in the dummy resistor. The contact plug passes through the resistor and directly contacts the metal layer in the dummy resistor.

According to still another embodiment of the present invention, the present invention provides an integrated structure. The integrated structure includes a substrate, an inner dielectric layer, a transistor, and a resistor. The substrate defines a resistive region and an active region. The inner dielectric layer directly covers the substrate. A transistor is disposed in the active region of the inner dielectric layer, and the transistor includes a metal gate. The resistor is disposed in a resistive region in the inner dielectric layer, wherein the resistor comprises a U-shaped metal layer.

The integrated structure of the present invention is fabricated together with the process of a conventional metal gate transistor, so that multiple steps can be omitted and manufacturing costs can be saved.

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.

Please refer to FIG. 1 to FIG. 6 , which are schematic diagrams showing the steps of forming a resistor in the first embodiment of the present invention. As shown in Fig. 1, a substrate 300 is first provided. The substrate 300 may be a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI). Base, etc., but not limited to the above. An active region 400 is defined on the substrate 300 for subsequent formation of a transistor and a resistive region 500 for subsequent formation of a resistor. The substrate 300 has a plurality of shallow trench isolation (STI) 302, wherein a portion of the shallow trench isolation 302 surrounds the active region 400, and a portion of the shallow trench isolation 302 is formed in the resistive region 500. Then, a plurality of semiconductor processes are performed to form a transistor 402 in the active region 400, and a dummy resistor 502 is simultaneously formed in the resistance region 500. In one embodiment of the invention, the transistor 402 has a dielectric layer 404, a sacrificial layer 406, a cap layer 408, a sidewall sub-410, and a source/drain region 412; and the dummy resistor 502 also has a dielectric. A layer 504, a sacrificial layer 506, a cap layer 508, and a sidewall spacer 510. In a preferred embodiment of the present invention, dielectric layer 404 and dielectric layer 504 are, for example, hafnium oxide (SiO ₂ ), sacrificial layer 406 and sacrificial layer 506 are, for example, polysilicon, and cap layer 408 and cap layer 508 are, for example, tantalum nitride ( SiN), the sidewall spacer 410 and the sidewall spacer 510 are, for example, a single layer or a multilayer structure of a material such as tantalum nitride, and the source/drain region 412 is formed in the substrate 300 with a suitable dopant. It should be noted that the material of each element of the transistor 402 of the present embodiment is not limited to the foregoing, and the transistor 402 of the embodiment may also include other structures, such as a salicide layer or other layers or layers. The protective film or the like is well known to those skilled in the art and will not be described herein. After the transistor 402 and the dummy resistor 502 are formed, a contact etch stop layer (CESL) 304 is then formed over the substrate 300 over the transistor 402 and the dummy resistor 502.

As shown in FIG. 2, an inter-layer dielectric (ILD) 306 is formed on the contact hole etch stop layer 304. In one embodiment, the inner dielectric layer 306 is, for example, yttrium oxide (SiO ₂ ), doped yttrium oxide tetraethoxy decane (TEOS), plasma enhanced tetraethoxy decane (PETEOS), or other low Dielectric layer of dielectric constant. Then, a planarization process, such as a chemical mechanical polish (CMP) process or an etch process or a combination of the two, is performed to sequentially remove portions of the inner dielectric layer 306 and portions. The contact hole etch stop layer 304, a portion of the sidewall spacer 410, a portion of the sidewall spacer 510, and completely remove the cap layer 408 and the cap layer 508 until the sacrificial layer 406 in the transistor 402 and the dummy resistor 502 are exposed. Sacrificial layer 506. Then, a dry etching process and/or a wet etching process is performed to remove the sacrificial layer 406 in the transistor 402 and the sacrificial layer 506 in the dummy resistor 502 to form the first trench 414 and the resistive region 500 in the active region 400, respectively. A second trench 514 is formed in the middle. In another embodiment of the invention, the dielectric layer 404 and the dielectric layer 504 may also be selectively removed.

As shown in FIG. 3, a high dielectric constant layer 308 and a metal layer 310 are integrally formed on the substrate 300. The high dielectric constant layer 308 and the metal layer 310 are sequentially filled in the first trench 414 and the second trench 514, and completely fill the first trench 414 and the second trench 514. In a preferred embodiment of the present invention, the high dielectric constant layer 308 is, for example, hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon (hafnium silicon). Oxynitride, HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta ₂ O _{5 )} Zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO), strontium bismuth tantalate (SrBi ₂ Ta) ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) or barium strontium titanate (BaxSr _1-x TiO ₃ , BST). The metal layer 310 is, for example, aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide ( TiC), tantalum nitride (TaN), titanium tungsten (Ti/W) or a single or composite metal layer such as titanium and titanium nitride (Ti/TiN). In other embodiments of the present invention, one or more barrier layers (not shown) may be selectively formed between the high dielectric constant layer 308 and the metal layer 310 according to the electrical requirements of the transistor 402. At least one work function metal layer (not shown). Finally, a planarization process is performed to remove the high dielectric constant layer 308 and the metal layer 310 outside the first trench 414 and the second trench 514 such that the top surface of the metal layer 310 is aligned with the inner dielectric layer 306. At this time, a U-shaped high dielectric constant layer 308 is formed on the surfaces of the first trench 414 and the second trench 514, respectively.

As shown in FIG. 4, a first dielectric layer 312 is formed on the substrate 300 to cover and directly contact the inner dielectric layer 306, and a conductive layer 314 and a second dielectric layer 316 are sequentially formed. In a preferred embodiment of the present invention, the first dielectric layer 312 is, for example, niobium or oxygen doped or undoped tantalum carbide having a thickness of approximately 200 angstroms to 300 angstroms; and the conductive layer 314 is, for example, any conductive material such as It is titanium nitride having a thickness of approximately 20 angstroms to 60 angstroms; and the second dielectric layer 316 is, for example, tantalum nitride having a thickness of approximately 300 angstroms to 600 angstroms.

As shown in FIG. 5, an etching process is performed to remove the second dielectric layer 316 and the conductive layer 314 outside the resistance region 500. For example, a patterned photoresist layer (not shown) may be formed first, and the photoresist layer is patterned to perform an etching process for the mask such that the second dielectric layer 316 is vertically aligned with the conductive layer 314.

As shown in FIG. 6, an interlayer dielectric layer 318 is formed on the substrate 300, and a planarization process can be selectively performed. Finally, a plurality of contact plugs 320 are formed in the interlayer dielectric layer 318 and the second dielectric layer 316, wherein at least two contact plugs 320 directly contact the conductive layer 314, and at least two contact plugs 320 contact the source. / bungee zone 412. In this way, a resistive structure 321a can be formed on the inner dielectric layer 306. As shown in FIG. 6, the resistor structure 321a is directly disposed on the dummy resistor 502, that is, on the inner dielectric layer 306. The resistive structure 321a has a conductive layer 314 and has a sandwich structure of "first dielectric layer 312 - conductive layer 314 - second dielectric layer 316" above and below, wherein the second dielectric layer 316 is vertically aligned with the conductive layer 314.

In other embodiments, the position of the resistive structure 321a can also be adjusted depending on the product design. Please refer to FIG. 7, which is a schematic diagram showing the steps of forming an integrated structure in the second embodiment of the present invention. As shown in FIG. 7, the integrated structure of the semiconductor includes a transistor 402 and a resistor structure 321a. The transistor 402 is disposed in the inner dielectric layer 306 in the active region 400. The resistor structure 321a is disposed in the resistor region 500 and disposed directly on the inner dielectric layer 306, but is not directly disposed on the dummy resistor 502, that is, the resistor structure 321a and the shallow trench isolation 302 have an inner portion. Layer dielectric layer 306, preferably, has only inner dielectric layer 306.

Please refer to FIG. 8 to FIG. 14 , which are schematic diagrams showing the steps of forming an integrated structure in the third embodiment of the present invention. After the structure as shown in FIG. 1 is formed, as shown in FIG. 8, a patterned photoresist layer 322 is formed on the substrate 300. The opening of the patterned photoresist layer 322 will be located in the resistive region 500, and the width of the opening is less than the width of the sacrificial layer 506.

Next, as shown in FIG. 9, with the patterned photoresist layer 322 as a mask, an etching process is performed to remove the exposed contact hole etch stop layer 304, the cap layer 508, the sacrificial layer 506, and the dielectric layer 504 until exposed. A shallow trench isolation 302 in the substrate 300 is exited, and a third trench 324 is formed in the sacrificial resistor 502. It should be noted that the sidewalls on both sides of the third trench 324 further have a sacrificial layer 506 and a dielectric layer 504, respectively.

After the patterned photoresist layer 322 is removed, as shown in FIG. 10, an inner dielectric layer 306 is entirely formed on the substrate 300. The inner dielectric layer 306 overlies the contact hole etch stop layer 304 and completely fills the third trench 324. In one embodiment, the inner dielectric layer 306 is, for example, hafnium oxide, doped yttria tetraethoxy decane, plasma enhanced tetraethoxy decane, or other low dielectric constant dielectric layer. Then, a planarization process, such as a chemical mechanical planarization process or an etching process or a combination of the two, is performed to sequentially remove a portion of the inner dielectric layer 306 and a portion of the contact hole etch stop layer 304. A portion of the sidewalls 410, a portion of the sidewalls 510, and the cap layer 408 and the cap layer 508 are completely removed until the sacrificial layer 406 in the transistor 402 and the sacrificial layer 506 in the dummy resistor 502 are exposed.

As shown in FIG. 11, a dry etching and/or wet etching process is performed to completely remove the sacrificial layer 406 and the sacrificial layer 506. Finally, the high dielectric constant layer 308 and the metal layer 310 are filled, and a planarization process is performed to make the top surface of the metal layer 310 and the inner dielectric layer 306 high. As shown in FIG. 12, a first dielectric layer 312 is formed on the substrate 300 to cover and directly contact the inner dielectric layer 306, and a conductive layer 314 and a second dielectric layer 316 are sequentially formed. Then, as shown in FIG. 13, an etching process (not shown) is performed to remove the second dielectric layer 316 and the conductive layer 314 outside the resistance region 500, so that the second dielectric layer Electrical layer 316 is vertically aligned with conductive layer 314.

As shown in FIG. 14, an interlayer dielectric layer 318 is entirely formed on the substrate 300, and a planarization process can be selectively performed. Finally, a plurality of contact plugs 320 are formed, wherein at least two contact plugs 320 pass through the interlayer dielectric layer 318, the second dielectric layer 316, the conductive layer 314, the first dielectric layer 312, and are respectively contacted. In the metal layer 310 in the resistive region 500, at least two contact plugs 320 will contact the source/drain regions 412. As a result, a resistive structure 321b can be formed on the inner dielectric layer 306. As shown in FIG. 13, the resistor structure 321b is directly disposed on the inner dielectric layer 306. The resistor structure 321b has a conductive layer 314 and has a sandwich structure of "first dielectric layer 312 - conductive layer 314 - second dielectric layer 316" above and below. A feature of this embodiment is that the contact plug 320 contacts the metal layer 310 in the dummy resistor 502. Since the thickness of the conductive layer 314 is thin, it is difficult to align the contact plug 320 on the conductive layer 314. Therefore, in this embodiment, by contacting the contact plug 320 to the metal layer 310, on the one hand, the accuracy of the alignment can be increased, and on the other hand, the resistance of the resistor can be increased.

Please refer to FIG. 15 to FIG. 19, which are schematic diagrams showing the steps of forming a resistor in the fourth embodiment of the present invention. After passing through the steps of FIGS. 1 to 3, referring to FIG. 15, an interlayer dielectric layer 325 is formed on the substrate 300, for example, cerium oxide (SiO ₂ ) or doped cerium oxide tetraethoxy. The ruthenium (TEOS) layer or the same material as the first dielectric layer 312 described above has a thickness of substantially 200 angstroms to 400 angstroms.

Next, as shown in FIG. 16, a lithography and etching process is performed to remove the interlayer dielectric layer 325 in the resistive region 500 to form a patterned interlayer dielectric layer 327. The patterned interlayer dielectric layer 327 exposes at least the underlying metal layer 310.

As shown in FIG. 17, a wet etching and/or dry etching process is performed to partially remove the metal layer 310 in the resistive region 500, and a fourth trench 326 is formed in the resistive region 500. In a preferred embodiment of the invention, the metal layer 310 is etched to a uniform thickness, for example 20 to 60 angstroms, to form a U-shaped structure. It is noted that the barrier layer (not shown), the work function metal layer (not shown) and the high dielectric constant layer 308 under the metal layer 310 are preferably formed because a metal layer 310 having a partial thickness remains. It is not removed. In addition, another embodiment of the embodiment can also remove the metal layer 310 to leave a barrier layer (not shown), a work function metal layer (not shown), and a high dielectric. Constant layer 308.

As shown in FIG. 18, a second interlayer dielectric layer 328 is formed over the substrate 300. The second interlayer dielectric layer 328 overlies the metal layer 310 and completely fills the fourth trench 326 in the resistive region 500. Finally, as shown in FIG. 19, a plurality of contact plugs 320 are formed, wherein at least two contact plugs 320 pass through the fourth interlayer dielectric layer 328 and contact the metal layer 310 or the barrier in the resistance region 500. Layer (not shown) or work function metal layer. In this way, a resistor structure 321c can also be formed in the resistor region 500. The resistor structure 321c has a sandwich structure of "high dielectric constant layer 308 - metal layer 310 - fourth interlayer dielectric layer 328", and the metal layer 310 Will have a U-shaped profile.

The invention provides different integrated structures and a manufacturing method thereof, which can integrate the traditional metal gate transistor process and the resistance process, so that multiple steps can be omitted and the manufacturing cost can be saved.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

300. . . Base

302. . . Shallow trench isolation

304. . . Contact hole etch stop layer

306. . . Inner dielectric layer

308. . . High dielectric constant layer

310. . . Metal layer

312. . . First dielectric layer

314. . . Conductive layer

316. . . Second dielectric layer

318. . . Interlayer dielectric layer

320. . . Contact plug

321a. . . Resistance structure

321b. . . Resistance structure

321c. . . Resistance structure

322. . . Patterned photoresist layer

324. . . Third ditches

325. . . Interlayer dielectric layer

326. . . Fourth ditches

327. . . Patterned interlayer dielectric layer

328. . . Second interlayer dielectric layer

400. . . Active zone

500. . . Resistance zone

402. . . Transistor

502. . . Virtual resistor

404,504. . . Dielectric layer

406,506. . . Sacrificial layer

408,508. . . Cover

410,510. . . Side wall

412. . . Source/bungee area

414. . . First ditches

514. . . Second ditches

1 to 6 are schematic views showing the steps of forming a resistor in the first embodiment of the present invention.

Fig. 7 is a view showing the steps of forming a resistor in the second embodiment of the present invention.

8 to 14 are views showing the steps of forming a resistor in the third embodiment of the present invention.

15 to 19 are views showing the steps of forming a resistor in the fourth embodiment of the present invention.

300. . . Base

302. . . Shallow trench isolation

304. . . Contact hole etch stop layer

306. . . Inner dielectric layer

308. . . High dielectric constant layer

310. . . Metal layer

312. . . First dielectric layer

314. . . Conductive layer

316. . . Second dielectric layer

318. . . Interlayer dielectric layer

320. . . Contact plug

321a. . . Resistance structure

400. . . Active zone

500. . . Resistance zone

402. . . Transistor

502. . . Virtual resistor

404,504. . . Dielectric layer

406,506. . . Sacrificial layer

408,508. . . Cover

410,510. . . Side wall

412. . . Source/bungee area

Claims (20)

An integrated structure comprising: a substrate defining a resistive region and an active region; an inner dielectric layer directly overlying the substrate; and a transistor disposed in the inner dielectric layer a region, and the transistor includes a metal gate; and a resistor disposed in the resistor region on the inner dielectric layer, and the resistor directly contacts the inner dielectric layer. The integrated structure of claim 1, wherein the resistor comprises a first dielectric layer, a conductive layer, and a second dielectric layer. The integrated structure of claim 2, wherein the second dielectric layer is vertically aligned with the conductive layer. The integrated structure of claim 2, further comprising a contact plug passing through the second dielectric layer and contacting the conductive layer. The integrated structure of claim 2, wherein the first dielectric layer is in direct contact with the inner dielectric layer. The integrated structure of claim 1, further comprising a dummy resistor disposed in the resistor region in the inner dielectric layer and disposed directly under the resistor, wherein the dummy resistor comprises a metal layer and A high dielectric constant layer, and the high dielectric constant layer comprises a U-shaped cross section. The integrated structure of claim 1, wherein the inner dielectric layer is only between the resistor and the substrate. The integrated structure of claim 1, further comprising a shallow trench isolation disposed in the substrate of the resistive region. An integrated structure comprising: a substrate defining a resistive region and an active region; an inner dielectric layer directly overlying the substrate; and a transistor disposed in the inner dielectric layer a region, and the transistor includes a metal gate; a resistor disposed in the resistive region on the inner dielectric layer and directly contacting the inner dielectric layer; a dummy resistor disposed in the inner layer In the resistance region in the electrical layer, at least one metal layer is disposed in the dummy resistor; and a contact plug passes through the resistor and directly contacts the metal layer in the dummy resistor. The integrated structure of claim 9, wherein the resistor comprises a first dielectric layer, a conductive layer, and a second dielectric layer. The integrated structure of claim 10, wherein the second dielectric layer is vertically aligned with the conductive layer. The integrated structure of claim 9, wherein the dummy resistor has two of the metal layers, and the inner dielectric layer is between the two metal layers. The integrated structure according to claim 12, further comprising two high dielectric constant layers respectively disposed between the two metal layers and the substrate, wherein the high dielectric constant layer has a U-shaped cross section. The integrated structure of claim 9 further comprising a shallow trench isolation disposed in the substrate of the resistive region. An integrated structure comprising: a substrate defining a resistive region and an active region; an inner dielectric layer directly overlying the substrate; and a transistor disposed in the inner dielectric layer a region, and the transistor includes a metal gate; and a resistor disposed in the resistor region in the inner dielectric layer, wherein the resistor has a U-shaped cross section. The integrated structure of claim 15, further comprising a trench disposed in the resistance region, wherein the resistor is disposed in the trench. The integrated structure of claim 15, wherein the resistor further comprises a high dielectric constant layer disposed in the trench, and the high dielectric constant layer has a U-shaped cross section. The integrated structure of claim 15, wherein the resistor has a U-shaped metal layer. The integrated structure of claim 18, further comprising a contact plug passing through the inner dielectric layer and contacting the U-shaped metal layer. The integrated structure of claim 15 further comprising a shallow trench isolation disposed in the substrate of the resistive region.