TW201337875A - Display apparatus - Google Patents

Abstract

A display apparatus including a display panel, a first driving circuit and a second driving circuit. The first driving circuit is electrically connected to an image source and the display panel. The second driving circuit is electrically connected to the image source, the first driving circuit and the display panel. The first driving circuit and the second driving circuit receive a connected training data from the image source. The second driving circuit informs the first driving circuit when the second driving circuit is in the receiving ready state. The first driving circuit set a receiving ready flag when the first driving circuit and the second driving circuit are in the receiving ready state. The image source outputs a video data according to the receiving ready flag. The first driving circuit and the second driving circuit drive the display panel according to the video data.

Description

Display device

The present invention relates to a display device, and more particularly to a display device that avoids signal collision problems.

Based on advances in integrated circuit processes and manufacturing cost pressures, drive wafers, timing controllers, and power management wafers used in large-size liquid crystal displays are moving toward integrated design. In the integrated display device, it is roughly classified into a series type and a multi-drop type according to a connection structure between drive circuits.

In the tandem integrated display device, the driving circuit is presented in series, so the image source can correspond to a driving circuit in the liquid crystal display to transmit signals and data, that is, the line corresponding to the image source and the traditional non-integrated display device. similar. However, in order to enable data and signals to be transmitted between the driving circuits, a transmission interface is disposed between the two adjacent driving circuits, so that the manufacturing cost of the display device and the overall power consumption are increased.

In the multi-level integrated display device, each driving circuit is electrically connected to the image source, thereby providing a simpler structure for transmitting data and signals to reduce the hardware cost of the display device. However, due to the difference in line impedance, the multi-stage architecture is prone to distortion of data and signals, and needs to support bidirectional in response to display port specifications or embedded display port (eDP) specifications. In the transmission protocol, since each driving circuit operates alone, when the image source communicates with each driving circuit, there may be a problem of signal collision, so that the image source cannot confirm or misidentify the state of the display device, and thus may cause the display device to Display Error.

The present invention provides a display device in which a first driving circuit sets a receiving ready flag when the first driving circuit and the second driving circuit are in a ready state, and the image source knows the state of the display device by receiving a ready flag to avoid Signal conflicts.

The invention provides a display device comprising a display panel, a first driving circuit and a second driving circuit. The first driving circuit is electrically connected to the image source and the display panel. The second driving circuit is electrically connected to the image source, the first driving circuit and the display panel. The first driving circuit and the second driving circuit receive a connection training data from the image source, and the second driving circuit notifies the first driving circuit after receiving the ready state, the first driving circuit is in the first driving circuit and the second driving When the circuit is in the ready state, the receiving ready flag is set, and the image source outputs a video data according to the set receiving ready flag, and the first driving circuit and the second driving circuit drive the display panel according to the video data.

Based on the above, in the display device of the embodiment of the present invention, the second driving circuit notifies the first driving circuit after entering the receiving ready state, and the first driving circuit sets the receiving when the first driving circuit and the second driving circuit are in the receiving ready state. The flag is ready so that the image source can correctly know the status of the display device and avoid signal collisions.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a schematic diagram of a display device in accordance with an embodiment of the present invention. Referring to FIG. 1 , in the embodiment, the display device 100 is electrically connected to the image source 10 , and the display device 100 includes a display panel 110 , a first driving circuit 120 , and a second driving circuit 130 , wherein the first driving circuit 120 is electrically The image source 10 and the display panel 110 are connected. The second driving circuit 130 is electrically connected to the image source 10 , the first driving circuit 120 , and the display panel 110 .

In this embodiment, to ensure that the driving circuit (eg, 120, 130) can correctly receive the video data D_V, the image source 10 transmits the connection training data D_trn to the first driving circuit 120 and the second driving circuit before transmitting the video data D_V. 130. After receiving the connection training data D_trn from the image source 10, the first driving circuit 120 and the second driving circuit 130 adjust the timing of the received data according to the connection training data D_trn, that is, the first driving circuit 120 and the second driving circuit 130 are based on The status of the connection received by the training data D_trn is judged as whether or not the status is received. When the second driving circuit 130 is in the receiving ready state, that is, the second driving circuit 130 can correctly receive the data, the second driving circuit 130 notifies the first driving circuit 120. When the first driving circuit 120 is in the receiving ready state and receiving the notification of the second driving circuit 130, that is, the first driving circuit 120 and the second driving circuit 130 are all in the receiving ready state, the first driving circuit 120 is set to receive ready. Flag RF.

The image source 10 confirms the state of the first driving circuit 120 and the second driving circuit 130, that is, the state of the display device 100, according to the reception ready flag RF. When the receiving ready flag RF is set, the first driving circuit 120 and the second driving circuit 130 (ie, the display device 100) can correctly receive the data, so the image source 10 outputs the video data according to the received receiving flag RF. D_V. Next, the first driving circuit 120 and the second driving circuit 130 drive the display panel 110 according to the video data D_V. The display panel 110 can be a liquid crystal display panel, and the image source 10 can be a video player or a personal computer, and the invention is not limited thereto.

In the present embodiment, the receiving ready flag RF is set in the first driving circuit 120, but the position of receiving the ready flag RF in other embodiments of the present invention is not limited thereto, and may be based on the knowledge of those in ordinary skill in the art. change. Moreover, since the reception ready flag RF indicates whether the first driving circuit 120 and the second driving circuit 130 can correctly receive data, the image source 140 can continue to transmit or periodically transmit connection training before the reception ready flag RF is set. The data D_trn is transmitted to the first driving circuit 120 and the second driving circuit 130 to ensure that the first driving circuit 120 and the second driving circuit 130 can correctly receive the video data D_V. In the embodiment, the connection training data D_trn and the video data D_V transmitted by the image source 140 are all in accordance with the display port specification, but the invention is not limited thereto.

2 is a schematic diagram of a display device in accordance with another embodiment of the present invention. Referring to FIG. 2 , in the embodiment, the display device 20 is electrically connected to the image source 10 , and the display device 200 includes a display panel 210 , a first driving circuit 220 , a second driving circuit 230 , and a memory unit 240 . The first driving circuit 220 includes a first instruction receiver 222, a first data receiver 224, a first control unit 226, a flag setting unit 228, a first source driver SD1, and a first timing controller TC1. The second driving circuit 230 includes a second command receiver 232, a second data receiver 234, a second control unit 236, a second source driver SD2, and a second timing controller TC2. The source driver and timing control of this embodiment The device is divided into two components, but is not limited thereto, that is, the source driver can be integrated with the timing controller as a single component, which will not be discussed here.

The first command receiver 222 is electrically connected to the image source 10, the receiving ready flag RF, and the first control unit 226. The first data receiver 224 is electrically connected to the image source 10 and the first timing controller TC1. The flag setting unit 228 is electrically connected to the first data receiver 224, the second data receiver 234 of the second driving circuit 230, and the receiving ready flag RF. The first control unit 226 is electrically connected to the memory unit 240, the first data receiver 224, the second control unit 236 of the second driving circuit 230, and the reception ready flag RF. The first timing controller TC1 is electrically connected to the first source driver SD1. The first source driver SD1 is electrically connected to the display panel 210. The second command receiver 232 is electrically connected to the image source 10 and the second control unit 236. The second data receiver 234 is electrically connected to the image source 10 and the second timing controller TC2. The second source driver SD2 is electrically connected to the display panel 210.

In the embodiment, when the display device 200 is powered on, the first control unit 226 can obtain the receiving setting data D_tn from the memory unit 240 to set the receiving interface parameter of the first data receiver 224 according to the receiving setting data D_tn (for example, the terminal impedance). value). Moreover, the first control unit 226 transmits the received setting data D_tn to the second driving circuit 230, and the second control unit 236 sets the interface parameter (for example, the terminal impedance value) of the second data receiver 234 according to the received setting data D_tn.

When the display device 20 is electrically connected to the image source 10, the first control unit 226 of the first driving circuit 220 passes the extended display identification data (EDID) D_edid obtained from the memory unit 240, and transmits the extended display identification data D_edid through the first The command receiver 222 transmits to the image source 10. Then, the image source 10 can output the connection training instruction S_trn according to the extended display identification data D_edid. At this time, the first command receiver 222 and the second command receiver 232 receive the connection training command S_trn from the image source 10 through the command line 260, and transmit the connection training command S_trn to the first control unit 226 and the second control, respectively. Unit 236. And, the first command receiver 222 transmits the state of receiving the ready flag RF to the image source 10. Next, the first control unit 226 sets the data receiving parameter of the first data receiver 224 according to the connection training instruction S_trn, and the first control unit 236 sets the data receiving parameter of the second data receiver 234 according to the connection training instruction S_trn (for example, the data transmission rate) And the number of data channels).

After the image source 10 outputs the connection training command S_trn, the image source 10 outputs the connection training data D_trn, and the first data receiver 224 and the second data receiver 234 receive the connection training data from the image source 10 via the data line 250. D_trn. When the first data receiver 224 is in the receive ready state, that is, the first data receiver 224 can correctly receive the connection training data D_trn, the first data receiver 224 outputs the first reception ready signal S_mset. When the second data receiver 234 is in the receive ready state, that is, the second data receiver 234 can correctly receive the connection training data D_trn, the second data receiver 234 outputs the second reception ready signal S_sset.

After the flag setting unit 228 receives the first receiving ready signal S_mset and the second receiving ready signal S_sset, the flag setting unit 228 sets the receiving ready flag RF according to the first receiving ready signal S_mset and the second receiving ready signal S_sset. The first receiving ready signal S_sset is a signal indicating that the first data receiver 224 (equivalent to the second driving circuit 220) is in the receiving ready state, and the second receiving ready signal S_sset is indicating the second data receiver 234 (equivalent to the second The drive circuit 230) is a signal that receives the ready state.

After the reception ready flag RF is set, the image source 10 outputs the video data D_V. The first data receiver 224 and the second data receiver 234 respectively receive the corresponding video data D_V via the data line 250. The first data receiver 224 converts the corresponding video data D_V into the first display data D_M and transmits it to the first timing controller TC1, so that the first timing controller TC1 controls the first source according to the first display data D_M. The display panel 210 is driven by the driver SD2. The first data receiver 224 converts the corresponding video data D_V into the second display data D_S and transmits it to the second timing controller TC2, so that the second timing controller TC2 controls the second source driver SD2 according to the second display data D_S. The display panel 210 is driven.

In the embodiment of the present invention, the receiving ready flag RF may be composed of a physical component (such as a memory component), but the receiving ready flag RF may also be a node voltage, that is, the receiving ready flag RF may be a flag. The voltage of the output of the unit 228 is set, which can be designed by a person skilled in the art, and the embodiment of the present invention is not limited thereto.

Since the reception ready flag RF indicates whether the first data receiver 224 and the second data receiver 234 can correctly receive data, the image source 140 can be continuously transmitted or periodically transmitted before the reception ready flag RF is set. The data D_trn is transmitted to the first driving circuit 120 and the second driving circuit 130, and the image source 140 can adjust the amplitude and/or driving capability of the signal transmitting the connection training data D_trn to avoid the first data receiver 224 and the second data receiver. 234 The connection training data D_trn cannot be correctly received due to the signal amplitude of the transmission connection training data D_trn being too small or the driving ability being too low.

On the other hand, the first data receiver 224 and the second data receiver 234 fail to correctly receive the connection training data D_trn, which may be caused by improper setting of the receiving interface parameters of the first data receiver 224 and the second data receiver 234. Here, the receiving interface parameter is exemplified by the terminal impedance value, and it is assumed that the first data receiver 224 includes the first terminal impedance unit 224R and the second data receiver 234 includes the second terminal impedance unit 234R. In an embodiment of the present invention, the connection training data D_trn and the video data D_V can be transmitted through the differential signal. According to the circuit design of the differential signal, the first terminal impedance unit 224R is connected in parallel with the second terminal impedance unit 234R, and is first. The sum of the terminal impedance value of the terminal impedance unit 224R and the terminal impedance value of the second terminal impedance unit 234R remains unchanged.

In general, when designing the terminal impedance value of the first termination impedance unit 224R and the termination impedance value of the second termination impedance unit 236R, the line impedance of the data line 250 is ignored. However, in actual application, the line impedance of the data line 250 affects the effects of the first data receiver 224 and the second data receiver 234 receiving the connection training data D_trn and the video data D_V, so that the first data receiver 224 and the second data are obtained. One of the receivers 234 may not correctly receive the connection training data D_trn and cannot enter the reception ready state, that is, the flag setting unit 228 receives only one of the first reception ready signal S_mset and the second reception ready signal S_sset.

When one of the first data receiver 224 and the second data receiver 234 fails to enter the reception ready state, it should be the impedance of the terminal impedance value of the first terminal impedance unit 224R and the terminal impedance value of the second terminal impedance unit 236R. If the matching is improper, the terminal impedance value of the first terminal impedance unit 224R and the terminal impedance value of the second terminal impedance unit 236R can be adjusted, so that the first data receiver 224 and the second data receiver 234 can correctly receive the connection at the same time. The training data D_trn is similar or identical even if the equivalent impedance values transmitted to the first data receiver 224 and the second data receiver 234 are connected to the training data D_trn.

In other words, when the reception ready flag RF is not set, the first control unit 226 may adjust the terminal impedance value of the first termination impedance unit 224R of the first data receiver 224 and notify the second control unit 236, and the second control unit 236 Then, the terminal impedance value of the second terminal impedance unit 236R of the second data receiver 234 is synchronously adjusted so that the sum of the terminal impedance value of the first terminal impedance unit 224R and the terminal impedance value of the second terminal impedance unit 234R is maintained. That is, the equivalent terminal impedance value from the image source 10 end remains unchanged.

Moreover, when the first data receiver 224 and the second data receiver 234 receive the connection training data D_trn at the same time, the first control unit 226 can set the terminal impedance value of the first terminal impedance unit 224R and the second terminal impedance unit 236R. The terminal impedance value is stored in the memory unit 240 for loading when the display device 200 is turned on next time. Since the first control unit 226 and the second control unit 236 synchronously adjust the terminal impedance values of the first terminal impedance unit 224R and the second terminal impedance unit 234R, the first control unit 226 can understand the terminal of the second terminal impedance unit 236R through the timing. The impedance value, but in other embodiments, the terminal impedance value of the second terminal impedance unit 236R can be transmitted back through the second control unit 236, which may be changed according to the circuit design, and the embodiment of the present invention is not limited thereto. .

3 is a circuit diagram of the first terminal impedance unit and the second terminal impedance unit of FIG. 2 according to an embodiment of the invention. Referring to FIG. 2 and FIG. 3, it is assumed here that the first terminal impedance unit 224R and the second terminal impedance unit 234R have the same circuit structure and are corresponding differential signals, and the first terminal impedance unit 224R is taken as an example here, and The second termination impedance unit 234R is substantially the same as the first termination impedance unit 224R, and therefore will not be described again.

In the present embodiment, the first termination impedance unit 224R includes first switches 302, 304, 306, 608, first resistors 312, 314, 316, 318, second switches 322, 324, 326, 328 and a second resistor 332. , 334, 336, 338. The first switch 302, 304, 306, 608 is turned on according to the first impedance adjustment signal S_t1 of the first control unit 226. The first resistors 312, 314, 316, 318 are respectively connected in series with the corresponding switches of the first switches 302, 304, 306, 608 between the first signal pin dp1 of the first data receiver 224 and the receiving bias voltage V_rx, wherein The impedance values of the first resistors 312, 314, 316, 318 are at least one different.

Similarly, the second switch 322, 324, 326, 328 conducts one of the first control unit 226 according to the second impedance adjustment signal S_t2 of the first control unit 226. The second resistors 332, 334, 336, 338 are respectively connected in series with the corresponding switches of the second switches 622-628 in the second signal pin dn1 of the first data receiver 224 and the receiving bias voltage V_rx, wherein each second The impedance values of the resistors 632 to 638 are also different from each other. Wherein, based on impedance matching, the first resistors (eg, 312, 314, 316, 318) in series with the first switch (eg, 302, 304, 306, 608) that are turned on have the same impedance value as the second switch that is turned on (322). , 324, 326, 328) impedance values of the second resistors (eg, 332, 334, 336, 338) in series. According to the above, the second terminal impedance unit 234 is electrically connected between the first signal pin and the second signal pin of the second data receiver 234 by referring to the circuit, wherein the first signal pin and the second signal are The pins receive the differential signal pair respectively.

4 is a circuit diagram of the flag setting unit of FIG. 2 in accordance with an embodiment of the present invention. Referring to FIG. 2 and FIG. 3, in the embodiment, the flag setting unit 228 includes a gate 410, wherein the output end of the gate 410 is electrically connected to receive the ready flag RF for setting the reception ready flag RF, and And an input end of the gate 410 for receiving the first receiving ready signal S_mset and the second receiving ready signal S_sset, respectively. Moreover, the first receiving ready signal S_mset and the second receiving ready signal S_sset are respectively a high logic level, so when the AND gate 410 receives the first receiving ready signal S_mset and the second receiving ready signal S_sset, the AND gate 410 outputs High logic level to set the receive ready flag RF.

In summary, in the display device of the embodiment of the present invention, the first data receiver of the first driving circuit generates a first receiving ready signal after entering the receiving ready state, and the second data receiver of the second driving circuit is receiving and receiving. After the ready state, a second receiving ready signal is generated, and the flag setting unit sets the receiving ready flag when receiving the first receiving ready signal and the second receiving ready signal, so that the image source can correctly know the state of the display device and Avoid situations where signal collisions occur. And, when the reception ready flag is not set, the first control unit of the first driving circuit can adjust the terminal impedance value of the first data receiver, and the second control unit of the second driving circuit can adjust the second data receiver The terminal impedance value is to avoid improper termination impedance values affecting the transmission of connected training data.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Image source

100, 200. . . Display device

110, 210. . . Display panel

120, 220. . . First drive circuit

130, 230. . . Second drive circuit

222. . . First instruction receiver

224. . . First data receiver

224R. . . First terminal impedance unit

226. . . First control unit

228. . . Flag setting unit

232. . . Second instruction receiver

234. . . Second data receiver

234R. . . Second terminal impedance unit

236. . . Second control unit

240. . . Memory unit

250. . . Data line

260. . . Command line

302, 304, 306, 608. . . First switch

312, 314, 316, 318. . . First resistance

322, 324, 326, 328. . . Second switch

332, 334, 336, 338. . . Second resistance

410. . . Gate

Dp1. . . First signal pin

Dn1. . . Second signal pin

D_edid. . . Extended display identification data

D_M. . . First display data

D_S. . . Second display data

D_tn. . . Receiving setting data

D_trn. . . Connection training materials

D_V. . . Video material

RF. . . Receive ready flag

S_mset. . . First receive ready signal

S_sset. . . Second receive ready signal

S_t1. . . First impedance adjustment signal

S_t2. . . Second impedance adjustment signal

S_trn. . . Connection training signal

SD1. . . First source driver

SD2. . . Second source driver

TC1. . . First timing controller

TC2. . . Second timing controller

V_rx. . . Receiving bias

1 is a schematic diagram of a display device in accordance with an embodiment of the present invention.

2 is a schematic diagram of a display device in accordance with another embodiment of the present invention.

3 is a circuit diagram of the first terminal impedance unit and the second terminal impedance unit of FIG. 2 according to an embodiment of the invention.

4 is a circuit diagram of the flag setting unit of FIG. 2 in accordance with an embodiment of the present invention.

10. . . Image source

200. . . Display device

210. . . Display panel

220. . . First drive circuit

222. . . First instruction receiver

224. . . First data receiver

224R. . . First terminal impedance unit

226. . . First control unit

228. . . Flag setting unit

230. . . Second drive circuit

232. . . Second instruction receiver

234. . . Second data receiver

234R. . . Second terminal impedance unit

236. . . Second control unit

240. . . Memory unit

250. . . Data line

260. . . Command line

D_edid. . . Extended display identification data

D_M. . . First display data

D_S. . . Second display data

D_tn. . . Receiving setting data

D_trn. . . Connection training materials

D_V. . . Video material

RF. . . Receive ready flag

S_mset. . . First receive ready signal

S_sset. . . Second receive ready signal

S_trn. . . Connection training signal

SD1. . . First source driver

SD2. . . Second source driver

TC1. . . First timing controller

TC2. . . Second timing controller

Claims (10)

A display device includes: a display panel; a first driving circuit electrically connecting an image source and the display panel; and a second driving circuit electrically connecting the image source, the first driving circuit and the display panel The first driving circuit and the second driving circuit receive a connection training data from the image source, and the second driving circuit notifies the first driving circuit after receiving the ready state, where the first driving circuit is The first driving circuit and the second driving circuit are configured to receive a receiving ready flag when receiving the ready state, and the image source outputs a video data according to the receiving ready flag, and the first driving circuit and the second driving circuit are configured according to the The video material drives the display panel. The display device of claim 1, wherein the first driving circuit and the second driving circuit set data receiving of the first driving circuit and the second driving circuit according to a connection training instruction from the image source. And the connection training command is outputted to the first driving circuit and the second driving circuit prior to the connection training data. The display device of claim 2, wherein the image source transmits the connection training command to the first driving circuit and the second driving circuit through a command line. The display device of claim 2, further comprising a memory unit electrically connected to the first driving circuit, wherein the first driving circuit obtains a receiving setting data from the memory unit to set the first driving circuit Receiving interface parameters, and the first driving circuit outputs the receiving setting data to the second driving circuit to set a receiving interface parameter of the second driving circuit. The display device of claim 4, wherein the first driving circuit comprises: a first command receiver electrically connecting the image source and the receiving ready flag to receive the connection training command and Receiving the status of the ready flag is transmitted to the image source; a first data receiver is electrically connected to the image source to receive the connection training data and the video data, and when the first data receiver is in the receiving ready state, outputting a a first receiving ready signal, and converting the video data into the first display data; a flag setting unit electrically connecting the first data receiver and the second driving circuit to obtain the first receiving ready signal and the a second receiving ready signal of the second driving circuit is configured to set the receiving ready flag, wherein the second receiving ready signal is to indicate that the second driving circuit is in a receiving ready state; a first control unit is electrically connected to the memory unit The first command receiver, the first data receiver, and the second drive circuit to obtain the receiving setting data from the memory unit, and The receiving setting data is transmitted to the second driving circuit, the first control unit sets the data receiving parameter of the first data receiver according to the connection training instruction, and the first control unit sets the first data receiving according to the receiving setting data. The receiving interface parameter of the device; and a first timing controller electrically connected to the display panel for driving the display panel. The display device of claim 5, wherein the flag setting unit comprises: a gate, an output end of the gate is electrically connected to the receiving ready flag, and the plurality of inputs of the gate are respectively Receiving the first receive ready signal and the second receive ready signal. The display device of claim 4, wherein the second driving circuit comprises: a second command receiver electrically connected to the image source to receive the connection training command; a second data receiver, The image source and the flag setting unit are connected to receive the connection training data and the video data, and when the second data receiver is in the receiving ready state, output the second receiving ready signal to the flag Setting a unit, and converting the video data into a plurality of second display materials; a second control unit electrically connecting the first control unit, the second command receiver, the second data receiver, the second The control unit sets the data receiving parameter of the second data receiver according to the connection training instruction, the second control unit sets the receiving interface parameter of the second data receiver according to the receiving setting data; and a second timing controller, The display panel is connected to the display panel. The display device of claim 7, wherein the first data receiver comprises a first terminal impedance unit, and the second data receiver comprises a second terminal impedance unit, when the reception ready flag is not set The first control unit adjusts a terminal impedance value of the first terminal impedance unit and notifies the second control unit, so that the second control unit adjusts a terminal impedance value of the second terminal impedance unit, wherein the first terminal The impedance unit is connected in parallel with the second terminal impedance unit, and the sum of the terminal impedance value of the first terminal impedance unit and the terminal impedance value of the second terminal impedance unit remains unchanged. The display device of claim 8, wherein the first terminal impedance unit and the second terminal impedance unit respectively comprise: a plurality of first switches, according to the first control unit or the second control unit The first impedance adjustment signal is turned on; and the plurality of first resistors are respectively connected in series with the corresponding first switch and a first signal pin and a receiving bias of the first data receiver or the second data receiver Between the pressures; the plurality of second switches are turned on according to a second impedance adjustment signal of the first control unit or the second control unit; and the plurality of second resistors are respectively connected in series with the corresponding second switch Between the second signal pin of the first receiver or the second receiver and the receiving bias; wherein the first resistor connected in series with the first resistor has the same impedance value as the second switch that is turned on The impedance value of the second resistor connected in series. The display device of claim 4, wherein the first driving circuit stores the receiving interface parameters of the first driving circuit and the second driving circuit in the memory unit when the receiving ready flag is set To replace the receiving setting data.