TW201327777A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The present invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure is formed in a first conductive type substrate, which has an upper surface. The semiconductor structure includes: a protected device, at least an annulate buried trench, and at least an annulate doped region. The protected device is formed in the substrate. The buried trench is formed below the upper surface with a first depth, and the buried trench surrounds the protected device from top view. The doped region is formed below the upper surface with a second depth, and the doped region surrounds the buried trench from top view. The second depth is not less than the first depth.

Description

Semiconductor structure and method of manufacturing same

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure for improving a breakdown protection voltage and a method of fabricating the same.

Please refer to FIG. 3, which shows an equipotential line simulation of the prior art guard ring structure under reverse bias. The guard ring structure is typically coupled to a ground potential or float for the purpose of protecting a protected component (not shown) surrounded by the guard ring structure. In detail, when the protected component is operated, if there is no guard ring structure on the periphery of the protected component, when the peripheral well region of the protected component is reversely biased, the equipotential line in the depletion region will be outside the protected component. Forming a dense tip, the electric field can withstand the physical structure of the protected component. Therefore, its crash protection voltage is relatively low.

As shown in FIG. 3, the prior art guard ring structure includes a buried trench 23 and a doped region 25 for mitigating the equipotential lines on the periphery of the protected component, so that the electric field is lowered, and the voltage that the protected component can withstand increases, thereby increasing its Crash protection voltage.

However, with the need for component application and area miniaturization, the crash protection voltage is increasingly difficult to maintain.

In view of the above, the present invention is directed to the above-mentioned deficiencies of the prior art, and proposes a semiconductor structure and a manufacturing method thereof, which can increase the breakdown protection voltage of the protected component without increasing the component area and the excessive process steps, thereby increasing the protection component. The scope of application can be integrated into the process of low voltage components.

It is an object of the present invention to provide a semiconductor structure and a method of fabricating the same.

In order to achieve the above object, the present invention provides a semiconductor structure formed in a first conductive type substrate having an upper surface, the semiconductor structure comprising: a protected element formed on the first conductive The at least one first annular buried groove is formed below the upper surface, and the first annular buried groove surrounds the protected element, and the first annular buried groove is from the upper view a surface having a first depth; and at least one annular doped region formed below the upper surface, the annular doped region surrounding the first annular buried trench, and the ring is viewed from a top view The conductive type of the doped region is a second conductivity type, and the annular doped region has a second depth downward from the upper surface; wherein the second depth is not less than the first depth.

In another aspect, the present invention also provides a semiconductor structure manufacturing method, including: providing a first conductive type substrate having an upper surface; forming a protected component in the first conductive type substrate; forming at least one An annular buried channel is below the upper surface of the substrate. The first annular buried trench surrounds the protected component from a top view, and the first annular buried trench has a first depth from the upper surface. And forming at least one annular doping region below the upper surface, as viewed from a top view, the doped region surrounds the first annular buried trench, and the conductive type of the annular doped region is a second conductive type And the annular doped region has a second depth from the upper surface; wherein the second depth is not less than the first depth.

In a preferred embodiment, the protected element preferably comprises a high voltage component.

In the above embodiment, the semiconductor structure further includes a second conductive type substrate under the first conductive type substrate, wherein the high voltage component is an insulated gate bipolar transistor (IGBT). The second conductive type substrate is used as a collector of the IGBT.

In another preferred embodiment, the annular doping region preferably includes: at least one second annular buried trench formed under the upper surface, wherein the second annular buried trench surrounds the upper annular surface a first annular buried trench; and at least one doped doped region corresponding to the second annular buried trench formed in the first conductive type substrate outside the second annular buried trench, below the upper surface The second annular buried channel is covered.

In the above embodiment, the second annular buried trench and the first annular buried trench are preferably formed by the same process step, and the coated doped region is implanted with accelerated ions at different angles by ion implantation technology.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

Referring to Figures 1A-1F, a first embodiment of the present invention is shown. 1A-1E is a cross-sectional view showing the manufacturing process of the present embodiment; and FIG. 1F is a top view showing the semiconductor structure of the present embodiment. As shown in FIG. 1A, a substrate 11 is first provided, such as, but not limited to, an N-type epitaxial layer formed on a P-type germanium substrate (not shown). Next, under the upper surface 111 of the substrate 11, at least one annular groove 131 is formed as shown in the cross-sectional view of FIG. 1B. The annular trench 131 is formed, for example but not limited to, by a portion of the same process step in forming a shallow trench isolation (STI) structure in the same substrate. Next, an oxide layer 132 is formed on the upper surface 111 of the substrate 11, as shown in FIG. 1C. Thus, an insulating layer is formed on the inner sidewall and the bottom of the annular trench 131. Here, the depth of the annular groove 131 is calculated from the upper surface 111 of the substrate 11, and is a depth d1 as shown in the drawing. Next, inside the annular trench 131 covered by the oxide layer 132, for example, but not limited to, a P-type or N-type polysilicon material is filled to form an annular buried trench 13 as shown in Fig. 1D.

Next, a photoresist is formed, for example, by a lithography technique to define a region (not shown) to be implanted with impurities, and a P-type impurity is implanted in the form of an accelerated ion in an ion implantation technique. In the region, at least one annular doping region 15 is formed, and the annular doping region 15 is located below the upper surface 111 of the substrate 11, as shown in section 1E of the cross-sectional view. The depth of the annular doped region 15 is the depth d2 as shown in the figure from the upper surface 111 of the substrate 11. It should be noted that the depth d2 is not less than the aforementioned depth d1 .

Fig. 1F shows a top view of the semiconductor structure of the present embodiment. The plurality of annular buried trenches 13 surround the protected element 17 and the plurality of annular doped regions 15 surround the annular buried trenches 13. The protected component 17 is, for example but not limited to, a high voltage component, and the high voltage component is, for example but not limited to, an insulated gate bipolar transistor (IGBT). It should be noted that the cross-sectional view shown in Figs. 1A-1E is, for example, a cross-sectional view taken along the line AA' in Fig. 1F.

The depth d2 is not less than the depth d1 , which is the focus of the present invention. From the cross-sectional view of FIG. 1E, the preferred embodiment is that the depth d2 is greater than the depth d1 . An advantage of this arrangement is that the breakdown protection voltage of the protected component 17 can be increased in terms of component specifications.

Fig. 2A-2C shows a second embodiment of the present invention. As shown in FIG. 2A, a substrate 11 is first provided, such as, but not limited to, an N-type epitaxial layer formed on a P-type germanium substrate (not shown). Next, under the upper surface of the substrate 11, at least one annular trench 131 is formed. The annular trench 131 is formed, for example, but not limited to, by the same process steps in which the STI structure is formed in the same substrate. Next, on the upper surface of the substrate 11, an oxide layer 132 is formed, which forms an insulating layer on the inner side wall and the bottom of the annular trench 131. Here, the depth of the annular groove 131 is the depth d1 as shown in the figure from the upper surface of the substrate 11. Next, the photoresist 351 is formed by a lithography technique as a mask to define a region to be implanted with impurities, and an ion implantation technique is used to implant P-type impurities into the defined region in the form of accelerated ions to form at least A cladding doped region 352 is disposed under the upper surface of the substrate 11, as shown in section 2B of the cross-sectional view. The depth of the cladding doped region 352 is calculated from the upper surface of the substrate 11 to be the depth d2 as shown in FIG. 2B. It should be noted that the depth d2 is not less than the aforementioned depth d1 . After removing the photoresist 351, the inside of the annular trench 131 covered by the oxide layer 132, for example but not limited to being filled with a P-type or N-type polysilicon material, forms a ring as shown in FIG. 2C. The buried channel 13 and the annular buried groove 35.

Different from the first embodiment, the doped region 352 of the present embodiment is different from the doped region 15 of the first embodiment. One is that the doped region 352 of the present embodiment is within the defined region. The periphery of the annular groove 131 is doped with P-type impurities to cover the selected annular groove 131. This method has the advantages of reducing the difficulty of accelerating the penetration of ions through the deep substrate depth in the ion implantation technique; One difference is that in the present embodiment, when the cladding doping region 352 is formed by the ion implantation technique, it is necessary to implant the accelerated P-type impurity ions at different angles, as indicated by the dotted arrows in the figure, to achieve the required impurities. distributed.

The first embodiment and the second embodiment have lower isoelectric contour density than the prior art, and represent an electric field in the embodiment of the present invention in the same operating situation, that is, when the component is turned on or off. Small, so it can withstand higher voltages, in other words, the breakdown protection voltage is larger. Please refer to Figures 3, 4, and 5 for an isobaric line simulation of the semiconductor structure (guard ring structure) at three different depths d1 and depth d2 under reverse bias. According to Figures 3, 4, and 5, it is apparent that when the depth d1 is larger (as in the prior art shown in Fig. 3), equal to (as in the embodiment of the invention shown in Fig. 4), and less than (e.g., The embodiment of the present invention shown in Fig. 5) is an equipotential line simulation of the semiconductor structure (guard ring structure) under reverse bias at a depth d2 . According to the results of the simulation, the reverse biases that can be withstood by the semiconductor structures shown in Figs. 3, 4, and 5 are 408V, 496V, and 507V, respectively. From this point of view, the collapse protection voltage of the component can be significantly increased by the present invention.

In other words, please refer to Figures 3, 4, and 5 at the same time. It can be seen that the embodiment of the present invention has a smaller voltage contour density than the prior art, and represents that the P-type substrate 10 is electrically operated under the same operation conditions. When the N-type substrate 11 is electrically connected to a positive voltage to form a reverse voltage, the electric field of the embodiment of the present invention is small, and thus can withstand a higher voltage, and the breakdown protection voltage is large.

Figure 6 shows a more specific embodiment of the protected component of the semiconductor structure of the present invention. As shown, the protected component includes, for example but is not limited to, a high voltage component, N-channel IGBT 19, including a P-body 191, an emitter 193. , gate 195, and collector 197. Wherein, the N-type substrate 10 is electrically connected to the collector 197 of the IGBT 19, and when the IGBT 19 is reverse biased, that is, the collector 197 is electrically connected to a negative voltage, and the P-type substrate 11 is electrically connected to a positive voltage, the present invention is utilized. The semiconductor structure can increase the breakdown protection voltage.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep well areas, may be added without affecting the main characteristics of the components; for example, lithography is not limited to reticle technology, and may include electron beam lithography; The annular buried trench 13 shown in the second embodiment and the annular trench 131 in the annular buried trench 35 are formed by the same process. One of the embodiments may be formed by using different processes as long as the depth d2 is not less than The result of the depth d1 is sufficient; as another example, similar to the description of the first embodiment, other embodiments can also be applied to other N-type doped regions 352 or 15 when applied to N-type cladding doping. In the case of the region 352 or 15, the relevant P-type and N-type impurities may be interchanged. The above and other equivalent variations are intended to be covered by the scope of the invention.

10,11. . . Substrate

13,23. . . Buried tank

15,25,352. . . Doped region

17. . . Protected component

19. . . IGBT

191. . . Ontology

193. . . Emitter

195. . . Gate

197. . . Collector

111. . . Upper surface

131. . . Trench

132. . . Oxide layer

351. . . Photoresist

D1, d2 . . . depth

The first embodiment shows a first embodiment of the present invention.

Fig. 2A-2C shows a second embodiment of the present invention.

Figures 3, 4, and 5 show the equipotential line simulation of the semiconductor structure (guard ring structure) at three different depths d1 and depth d2 under reverse bias.

Figure 6 shows a more specific embodiment of the protected component of the semiconductor structure of the present invention.

11. . . Substrate

13. . . Buried tank

15. . . Doped region

D1, d2 . . . depth

Claims (10)

a semiconductor structure formed in a first conductive type substrate, the first conductive type substrate having an upper surface, the semiconductor structure comprising: a protected element formed in the first conductive type substrate; at least one first ring a buried trench formed under the upper surface, the first annular buried trench surrounding the protected component, and the first annular buried trench has a first depth from the upper surface; At least one annular doped region is formed under the upper surface, and the annular doped region surrounds the first annular buried trench, and the conductive type of the annular doped region is a second conductive And the annular doped region has a second depth from the upper surface; wherein the second depth is not less than the first depth. The semiconductor structure of claim 1, wherein the protected component comprises a high voltage component. The semiconductor structure of claim 2, further comprising a second conductive type substrate under the first conductive type substrate, wherein the high voltage component is an insulated gate bipolar transistor (IGBT) The second conductive type substrate is electrically connected to the collector of the IGBT. The semiconductor structure of claim 1, wherein the annular doped region comprises: at least one second annular buried trench formed under the upper surface, viewed from a top view, the second annular buried The trench surrounds the first annular buried trench; and at least one doped doped region corresponding to the second annular buried trench is formed in the first conductive type substrate on the periphery of the second annular buried trench Below the surface, the second annular buried channel is covered. The semiconductor structure of claim 4, wherein the second annular buried trench is formed by the same process step as the first annular buried trench, and the coated doped region is formed by ion implantation technology at different angles. Implantation accelerates ion formation. A semiconductor structure manufacturing method comprising: providing a first conductive type substrate having an upper surface; forming a protected component in the first conductive type substrate; forming at least one first annular buried trench on the upper surface of the substrate Bottom view, the first annular buried trench surrounds the protected component, and the first annular buried trench has a first depth downward from the upper surface; and at least one annular doped region is formed Below the upper surface, viewed from a top view, the doped region surrounds the first annular buried trench, and the conductive type of the annular doped region is a second conductivity type, and the annular doped region is from the The upper surface is downward and has a second depth; wherein the second depth is not less than the first depth. The method of fabricating a semiconductor structure according to claim 6, wherein the protected component comprises a high voltage component. The semiconductor structure manufacturing method of claim 7, further comprising forming a second conductivity type substrate under the first conductivity type substrate, wherein the high voltage component is an insulate gate bipolar transistor , IGBT), the second conductive type substrate is electrically connected to the collector of the IGBT. The method of fabricating a semiconductor structure according to claim 6, wherein the forming the at least one annular doping region comprises: forming at least one second annular buried trench below the upper surface, as viewed from above, The second annular buried trench surrounds the first annular buried trench; and at least one cladding doped region is formed, and the first conductive type substrate is corresponding to the second annular buried trench at the periphery of the second annular buried trench The second annular buried trench is covered under the upper surface. The semiconductor structure manufacturing method of claim 9, wherein the second annular buried trench and the first annular buried trench are formed by the same process step, and the coated doped region is formed by ion implantation technology Accelerated ion formation is implanted at different angles.