TW201312419A - Touch controllers, methods thereof, and devices having the touch controllers - Google Patents

Abstract

An operating method of a touch controller includes receiving a plurality of currents through a plurality of channels, respectively, sensing a first current among the plurality of currents and extracting the sensed first current as a first control current and converting a charge corresponding to a difference between the first control current and a second current among the plurality of currents into an output voltage.

Description

Touch controller, method thereof, and device having the same

Example embodiments of the inventive concept relate to a touch controller, and more particularly to a touch controller for removing display noise in a display common electrode, a method of operating the same, and a touch controller Device.

The demand for touchable electronic devices is increasing. The touchable electronic device includes a touch display panel for sensing a touch. Touching the display panel then includes sensor electrodes for measuring changes in capacitance values.

Capacitive sensing is to sense a touch by utilizing a change in capacitance value. When a finger or conductive stylus approaches the sensor electrode, the capacitance value changes. The change in capacitance value can be measured by the sensor electrodes, and the change in the capacitance value can be converted to the positions of the X-axis and the Y-axis.

Touching the display panel includes displaying a common electrode to display an image. As the thickness of the touch display panel becomes thinner, the display noise generated in the display common electrode may affect the touch sensing. Display noise may result from displaying the material, structure, or displayed image of the common electrode.

An example embodiment provides a method of operating a touch controller, comprising: receiving each of a plurality of currents via each of a plurality of channels; sensing a first current of the plurality of currents and extracting the sensed The first current is used as the first control current; and the charge corresponding to the difference between the first control current and the second current is converted into an output voltage, and the second current is in the Among the multiple currents.

According to an example embodiment, the operating method of the touch controller may further include: selecting respective channels of the first current and respective channels of the second current in response to the selection signal.

Converting to an output voltage includes converting a current difference between the second current and the first control current to an output voltage.

According to an example embodiment, the operating method of the touch controller may further include: compensating for a mismatch between the plurality of parasitic elements in response to the output voltage, the plurality of parasitic elements being located at the display common electrode and sensing Between the electrodes.

Compensating for the mismatch between the plurality of parasitic elements includes comparing the output voltage to the comparison voltage and outputting a plurality of selection bits according to the comparison result. And compensating for a mismatch by selecting at least one of the plurality of capacitors based on the plurality of select bits and compensating for a mismatch based on the selected at least one capacitor.

According to an example embodiment, the sensed second current is converted and extracted as a second control current; and a current difference between the second control current and the first control current is converted to the output voltage.

An example embodiment consistent with the inventive concept provides a touch controller including: a plurality of pins, each of which is coupled to each of a plurality of channels; a selector for responding to a selection signal And selecting two channels among the plurality of channels; and, a differential sensing block, the differential sensing block configured to convert the charge into an output voltage, the charge corresponding to each of the two channels Floating first current and second current The difference between.

The differential sensing block includes: a current conveyor configured to sense a first current and extract the sensed first current as a control current; and a charge amplifier, the charge amplifier It is configured to convert a current difference between the second current and the control current into an output voltage.

The current transmitter includes: a current replica circuit. The unity gain buffer amplifier includes: a unity gain buffer amplifier and a first input configured to receive a first current; a second input configured to receive an alternating voltage; and a second input coupled to the first input The first output. The current replica circuit includes a second output, the current replica circuit for extracting the control current based on a plurality of control voltages output from a unity gain buffer amplifier.

The current replica circuit includes a sourcing circuit and a sinking circuit. The source circuit and the drain circuit are connected in series between a power supply node of the unity gain buffer amplifier and a ground node.

Each of the source circuit and the drain circuit is controlled by the plurality of control voltages. The control current is the current difference between the current flowing in the drain circuit and the current flowing in the source circuit. When a plurality of sensors connected to the plurality of channels are not touched, the output voltage is a reference voltage.

According to an example embodiment, the touch controller may further include: a mismatch compensation block, the mismatch compensation block being connected to the display common electrode, the mismatch compensation block being configured to respond to the output voltage And the compensation shows the common electricity A mismatch between the plurality of parasitic elements between the pole and the sensor electrode. The mismatch compensation block includes: a capacitor array including a plurality of capacitors; and a bit generator, the select bit generator configured to compare the output voltage with the comparison voltage to select a plurality of At least one of the capacitors, and a plurality of selection bits are generated based on the comparison result.

The select bit generator includes: a comparator configured to compare the comparison voltage to an output voltage and output a comparison signal; and successive approximation register (SAR) control logic, the successive approximation The memory control logic is configured to generate a plurality of select bits in response to the comparison signal. The successive approximation register control logic generates a compensated clock signal and supplies the compensated clock signal to the source driver.

Another example embodiment consistent with the inventive concept provides a touch controller including: a plurality of pins, each of which is connected to a plurality of channels; a first current transmitter, the first current transmitter is grouped State to sense a first current flowing in one of the plurality of channels, and extract the sensed first current as a first control current; a second current transmitter configured to sense Detecting a second current flowing in the other of the plurality of channels and extracting the sensed second current as a second control current; and a charge amplifier configured to be the first A current difference between the control current and the second control current is converted to an output voltage.

According to an example embodiment, the touch controller may further include: a plurality of driving pins connected to the plurality of driving channels; and an integrated circuit configured to pulse the symbols Signal Signal) is supplied to each of the plurality of drive channels.

The first current transmitter includes: a current replica circuit. The unity gain buffer amplifier includes: a unity gain buffer amplifier and an inverting input configured to receive a first current; a non-inverting input configured to receive a reference voltage; and, coupled to the inverting terminal Output. The current replica circuit is configured to extract the first control current based on a plurality of control voltages output from a unity gain buffer amplifier.

The current replica circuit includes a source circuit and a drain circuit. The source circuit and the drain circuit are connected in series between a power supply node of the unity gain buffer amplifier and a ground node. Each of the source circuit and the drain circuit is configured to operate based on the plurality of control voltages.

The second current transmitter includes: a unity gain buffer amplifier and a current replica circuit. The unity gain buffer amplifier includes an inverting input configured to receive a second current, a non-inverting input configured to receive a reference voltage, and an output coupled to the inverting terminal. The current replica circuit is configured to extract the second control current based on a plurality of control voltages output from a unity gain buffer amplifier.

The current replica circuit includes a plurality of current mirrors each connected between a power supply node of the unity gain buffer amplifier and a ground node. Each of the plurality of current mirrors is configured to operate based on the plurality of control voltages.

An example embodiment consistent with the inventive concept provides a touch display system including: a touch display panel; and a touch controller, The touch controller is connected to the touch display panel by a plurality of channels.

The touch controller includes: a current transmitter that senses a first current flowing through a plurality of currents of each of the plurality of channels, and extracts the sensed first current as a control current And a charge amplifier that converts a difference between the control current and a second one of the plurality of currents into an output voltage. The touch display system is a portable device.

Another example embodiment discloses a touch display system including: a display panel configured to generate a plurality of currents via a plurality of channels, respectively; an integrated circuit, the integrated circuit coupled to the a plurality of channels, the integrated circuit including a differential sensor configured to receive a first current associated with the first channel and a second current associated with the second channel, to generate A charge corresponding to a difference between the first current and the second current, and converting the charge into an output voltage.

The integrated circuit further includes a mismatch compensator configured to compensate for parasitic capacitance in the display panel based on the output voltage.

The mismatch compensator includes: a bit selection generator configured to receive the output voltage, compare an output voltage to a comparison voltage, and generate a plurality of selection bits based on the comparison And a capacitor array configured to select at least one of the plurality of capacitors based on the plurality of select bits to compensate for parasitic capacitance.

The mismatch compensator is configured to selectively change a capacitance between the sensor electrode and the display common electrode to compensate for parasitic electricity in the display panel Rong.

The first channel is adjacent to the second channel.

The above and other features and advantages will become more apparent from the detailed description of embodiments of the invention. The above described features and advantages of the present invention will be more apparent from the following description.

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings in which FIG. However, the example embodiments may be embodied in many different forms and should not be construed as being limited to the example embodiments described herein. Rather, the examples are provided so that this disclosure will be thorough and complete, and the scope of the example embodiments will be fully conveyed by those skilled in the art. In the figures, the size and relative sizes of layers and regions may be exaggerated for clarity. The same numbers always refer to the same component.

It will be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or the intervening element can be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, the intervening element is absent. The term "and/or" as used herein includes any and all groups of one or more of the associated listed items, and may be abbreviated as "/".

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, such elements are not limited by the terms. These terms are only used to distinguish between different components. For example, without departing from the teachings of the present invention In this case, the first signal may be referred to as a second signal, and the second signal may also be referred to as a first signal.

The terminology used herein is for the purpose of describing the particular embodiments, As used herein, the singular forms " " " " " It should be further understood that the terms "comprising" and "comprising", "the" One or more other features, regions, integers, steps, operations, components, components, and/or groups thereof are added.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning meaning meaning It should be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the related art and/or application, and should not be idealized or too formal. Meaning is explained unless it is explicitly defined as such.

1 is a plan view of a touch display system including a touch controller in accordance with an example embodiment of the inventive concept. Referring to FIG. 1, the touch display system 1 is a portable device such as a smart phone, a cellular phone, a tablet PC, a laptop computer, or an MP3 player. (MP3 player). The touch display system 1 includes a touch display panel 10, an integrated circuit 40, and a host controller 70.

A plurality of sensors are arranged in the touch display panel 10 as a matrix of rows and columns. Each row of sensors and each column of sensors is coupled to each of a plurality of channels Chx1 to Chxm and Chy1 to Chyn, where m and n are natural numbers.

2 is a block diagram of the integrated circuit illustrated in FIG. 1. Referring to FIGS. 1 and 2, the integrated circuit 40 includes a touch controller 50 and a display driver 60.

The touch controller 50 includes an analog front end (AFE) 100, a memory 53, a micro control unit (MCU) 51, and a control logic block 55.

The AFE 100 is connected to a plurality of channels Chx1 to Chxm and Chy1 to Chyn, and receives each current via these channels Chx1 to Chxm and Chy1 to Chyn. The AFE 100 processes each of these currents and outputs a digital signal. The memory 53 stores a digital signal output from the AFE 100 or a digital signal processed by the MCU 51.

The MCU 51 processes the digital signal output from the AFE 100. For example, the MCU 51 calculates touch coordinates based on the digital signals output from the AFE 100 and transmits the touch coordinates to the host controller 70. MCU 51 and control logic block 55 can be in communication with host controller 70. Control logic block 55 may receive timing control signals (eg, horizontal sync signals and vertical sync signals) from timing control logic block 67 via host controller 70.

The display driver 60 includes a source driver 61, a gate driver 63, a memory 65, a timing control logic block 67, and a power generator 69.

The source driver 61 is responsive to output from the timing control logic block 67. The control signal produces grayscale data for driving the display panel. According to an example embodiment, the source driver 61 can be supplied by the compensated clock signal CALCK from the touch controller 50. The gate driver 63 continuously scans the gate line of the display panel in response to a control signal output from the timing control logic block 67. The memory 65 stores the display material.

Timing control logic block 67 is generated for controlling source driver 61 and gate driver 632k7

Timing control signals (eg, horizontal sync signals and vertical sync signals). Timing control logic block 67 can be in communication with host controller 70. The power generator 69 generates power in response to a timing control signal output from the timing control logic block 67.

3 is a cross-sectional view of the touch display panel illustrated in FIG. 1. Referring to FIGS. 1 through 3, the touch display panel 10 includes a sensor electrode 10-1 and a display common electrode 10-2.

The sensor electrode 10-1 can be implemented with Indium Tin Oxide (ITO). The sensor electrode 10-1 includes a plurality of sensors.

When a person touches at least one of the plurality of sensors, a capacitance value CSIG is generated between the sensor electrode 10-1 and the human finger. The touch can be sensed by using the capacitance value CSIG. That is, the current output from the sensor electrode 10-1 will sense the capacitance value CSIG. This type of capacitive sensing is self-capacitance sensing.

A vertical parasitic element Cv is formed between the sensor electrode 10-1 and the display common electrode 10-2. According to an example embodiment, the vertical parasitic element Cv may be referred to as a parasitic capacitance, a vertical parasitic element, or a vertical parasitic capacitance.

As the touch display panel 10 is gradually thinned or the touch display panel 10 is gradually enlarged, the parasitic element Cv is also enlarged. As the parasitic element Cv becomes larger, the display noise may affect the touch sensing more. Therefore, there is a need for a method of removing display noise. The display noise may be generated by displaying the material or structure of the common electrode 10-2 or the image to be displayed.

4 is a block diagram of the analog front end illustrated in FIG. 2. Referring to FIGS. 1 through 4, the AFE 100 includes: a plurality of pins PIN1 to PINh, where h is a natural number; a selector 110, a differential sensing block 120, and a low pass filter (LPF) 121, an analog to digital converter (ADC) 123, and a finite impulse response (FIR) filter 125.

Each of these pins PIN1 to PINh is connected to each of the plurality of channels Chx1 to Chxm and Chy1 to Chyn. For example, multiple channels of Chx1 to Chxm are row-related channels, and multiple channels such as Chy1 to Chyn are column-related channels.

The selector 110 selects two channels among the plurality of channels Chx1 to Chxm and Chy1 to Chyn in response to the selection signal SEL. For example, the selector 110 may be in multiple channels in the order of (Chx1, Chx2), (Chx2, Chx3), (Chx3, Chxm), (Chy1, Chy2), (Chy2, Chy3), and (Chy3, Chyn). Two channels PCH and NCH are selected from Chx1 to Chxm and Chy1 to Chyn. According to an example embodiment, the selector 110 may be in the order of (Chx1, Chx2), (Chx1, Chx3), (Chx1, Chxm), (Chy1, Chy2), (Chy1, Chy3), and (Chy1, Chyn). Pass Two channels PCH and NCH are selected in the channels Chx1 to Chxm and Chy1 to Chyn.

The differential sensing block 120 converts the charge into an output voltage Vout corresponding to a difference between the first current SIGi and the second current SIGj flowing in each of the two channels NCH and PCH, and the output The output voltage Vout is described. The differential sensing block 120 can remove the display noise appearing in the common electrode 10-2 by differentially sensing two of the plurality of channels NCH and PCH. The detailed operation of the differential sensing block 120 will be explained in detail in FIGS. 5 and 6.

The LPF 121 reduces noise elements in the output voltage Vout. The ADC 123 converts the output voltage into a digital signal, which is an analog signal. The FIR filter 125 is used to remove noise of the digital signal.

FIG. 5 is a block diagram of the differential sensing block illustrated in FIG. 4. Referring to FIGS. 4 and 5 , the differential sensing block 120 includes a current transmitter 145 and a charge amplifier 150 .

The current transmitter 145 senses the first current SIGi and extracts the sensed first current SIGi as the control current CC. The current transmitter 145 can include a unity gain buffer amplifier 130 and a current replica circuit 140.

The unity gain buffer amplifier 130 includes an operational amplifier 131. The operational amplifier 131 includes a first input terminal IN1 that receives the first current SIGi, a second input terminal IN2 that receives the first AC voltage Vin1, and a first output terminal ON1 that is coupled to the first input terminal IN1. The first input terminal IN1 is an inverting terminal, and the second input terminal IN2 is a non-inverting terminal.

According to the characteristics of the unity gain buffer amplifier 130, the first input terminal IN1 and the second input terminal IN2 have the same voltage as each other. That is, when the first alternating voltage Vin1 is applied to the second input terminal IN2, the first alternating voltage Vin1 is applied to the first input terminal IN1. The first current SIGi is generated by the first alternating voltage Vin1. The first alternating voltage Vin1 can be supplied by a voltage generator (not shown). When a human finger or a conductive pen touches the touch display panel 10, the first current SIGi senses the capacitance value CSIG, the parasitic element Cv, and the display noise.

Since the voltage output from the first output terminal ON1 follows the voltage of the first input terminal IN1, the unity gain buffer amplifier 130 can also be referred to as a voltage follower.

FIG. 6 is a circuit diagram of the current transmitter illustrated in FIG. 5. Referring to FIGS. 5 and 6, the current transmitter 145 includes a unity gain buffer amplifier 130 and a current replica circuit 140. The unity gain buffer amplifier 130 includes an operational amplifier 131. The operational amplifier 131 is explained in detail in FIG. 1 of the "CIRCUIT AND METHODS FOR IMPROVING SLEW RATE OF DIFFERENTIAL AMPLIFIER", which is entitled "CIRCUIT AND METHODS FOR IMPROVING SLEW RATE OF DIFFERENTIAL AMPLIFIER". The entire contents are hereby incorporated by reference in their entirety, the entire disclosure of which is hereby incorporated.

The current replica circuit 140 generates a control current CC based on the plurality of control voltages CS1 and CS2 output from the operational amplifier 131. The current replica circuit 140 includes a source circuit MP2 and a drain circuit MN2, and the source circuit MP2 and the drain circuit MN2 are connected in series between the power supply node VDD and the ground node VSS. The source circuit MP2 can be implemented by a PMOS transistor, and The pole circuit MN2 can be embodied by an NMOS transistor.

Each of the plurality of transistors MP1, MP2, MN1, and MN2 has the same size (length and width). The first transistor MP1 and the third transistor MP2 are controlled by the first control voltage CS1, and the second transistor MN1 and the fourth transistor MN2 are controlled by the second control voltage CS2. Therefore, the current IPD1 flowing in the first transistor MP1 is the same as the current IPD2 flowing in the third transistor MP2, and the current IND1 flowing in the second transistor MN1 is the same as the current IND2 flowing in the fourth transistor MN2.

The current SIGi flowing from the first input terminal IN1 to the first output terminal ON1 will be the same as the difference between the current IPD1 flowing in the first transistor MP1 and the current IND1 flowing in the second transistor MN1. This can be expressed as shown in Equation 1.

[Equation 1] SIGi=IND1-IPD1

The control current CC is the same as the difference between the current IPD2 flowing in the third transistor MP2 and the current IND2 flowing in the fourth transistor MN2. This can be expressed as shown in Equation 2.

[Equation 2] CC=IND2-IPD2

By adding the third transistor MP2 and the fourth transistor MN2 and sensing the first current SIGi, the sensed first current SIGi extracted from the node CON will be extracted as the control current CC.

Referring to FIG. 5, charge amplifier 150 includes an operational amplifier, such as 151. The operational amplifier 151 includes: receiving the second current SIGj and controlling the electricity The third input terminal IN3 of the current difference (SIGj-CC) between the streams CC, the fourth input terminal IN4 receiving the second AC voltage Vin2, and the second output terminal ON2. Further, the charge amplifier 150 includes a feedback resistor Rf and a feedback capacitor Cf connected in parallel between the third input terminal IN3 and the second output terminal ON2.

The charge amplifier 150 transmits a charge corresponding to a current difference (SIGj-CC) between the second current SIGj and the control current CC to the feedback capacitor Cf, and generates an output voltage Vout corresponding to the voltage passing through the feedback capacitor Cf. The charge amplifier 150 can be referred to as a charge to voltage converter.

When the touch display panel 10 is not touched, the ideal output voltage Vout is the reference voltage. For example, the reference voltage can be 0 volts. However, there may be a mismatch between the plurality of parasitic elements Cv depending on the manufacturing procedure. The output voltage Vout may not be the reference voltage. Accordingly, AFE 100 may further include mismatch compensation block 200 for compensating for mismatch between multiple parasitic elements Cv. The mismatch compensation block 200 is connected to the pin PINo, which is connected to the display common electrode 10-2.

FIG. 7 is a block diagram of the mismatch compensation block illustrated in FIG. 4. Referring to FIGS. 4, 5, and 7, the mismatch compensation block 200 includes a capacitor array 210 and a selection bit generator 220.

The capacitor array 210 is connected to the first input terminal IN1 and the third input terminal IN3, and is connected to the pin PINo, which is connected to the display common electrode 10-2. The capacitor array 210 includes a plurality of capacitors C, 2C, ... and 16C and a plurality of switches 211, 213, 215, 217 and 219. Multiple The capacitance values of each of the capacitors C, 2C, ..., and 16C are different from each other. Each of these switches 211, 213, 215, 217, and 219 can be implemented with a transmission gate. According to an example embodiment, the number of these capacitors C, 2C, ... and 16C and the number of these switches 211, 213, 215, 217 and 219 may vary.

The selection bit generator 220 compares the output voltage Vout with the comparison voltage, and outputs a plurality of selection bits, such as Q0 to Q5, according to the comparison result, to select a plurality of capacitors C, 2C, ..., and 16C. At least one.

The selection bit generator 220 includes a comparator 221 and a successive approximation register (SAR) control logic 223. The comparator 221 includes a first input terminal that receives the comparison voltage, a second input terminal that receives the output voltage Vout, and an output terminal that outputs the comparison signal COMP. For example, the comparison voltage is the ground voltage.

When the output voltage Vout is higher than the comparison voltage (for example, 0 volts), the comparator 221 outputs the comparison signal COMP having a high level. When the output voltage Vout is lower than the comparison voltage (for example, 0 volts), the comparator 221 outputs the comparison signal COMP having a low level.

The SAR control logic 223 sets one of the plurality of selected bits Q0 to Q5 in response to the comparison signal COMP, moves to the next bit and sets the next bit. The plurality of selection bits /Q0, /Q1, /Q2, /Q3, and /Q4 are opposite phase elements of the plurality of selected bits Q0, Q1, Q2, Q3, and Q4.

For example, first, the most significant bit Q5 of the plurality of selection bits Q0 to Q5 is set to "1", and the remaining bits Q4 to Q0 are set to "0". Therefore, the switch 211 is turned on, and the remaining switches 213, 215, 217 and 219 are turned off.

When the comparison signal COMP is at the high level, the SAR control logic 223 holds the most significant bit Q5 at "1" and the next bit Q4 at "1". Therefore, the switches 211 and 219 are turned on.

When the comparison signal COMP is at the low level, the SAR control logic 223 resets the most significant bit Q5 to "0" and sets the next bit Q4 to "1". Therefore, the switch 211 is turned off, and the switches 213 and 219 are turned on.

After the switch 219 is turned on with one of the switches 211 and 213, the differential sensing block 120 outputs an output voltage Vout by performing a differential sensing operation on the first current SIGi and the second current SIGj. The comparator 221 compares the output voltage Vout with the comparison voltage, and performs a comparison operation, thereby outputting the comparison signal COMP. The SAR control logic 223 sets the selection bit Q4 to "1" or "0" based on the comparison signal COMP, and performs a bit setting operation to set the next bit Q3 to "1".

The differential sensing operation of the differential sensing block 120, the comparison operation of the comparator 221, and the bit setting operation of the SAR control logic 223 are repeatedly performed until the least significant bit Q0 is determined. Therefore, the mismatch of the parasitic elements can be compensated. The differential sensing operation of the differential sensing block 120, the comparison operation of the comparator 221, and the bit setting operation of the SAR control logic 223 may be defined as a mismatch compensation operation.

The SAR control logic 223 generates a compensated clock signal CALCK and outputs a compensated clock signal CALCK to the source driver 61. The compensated clock signal CALCK can be generated in response to an internal compensation clock enable signal (not shown).

The source driver 61 supplies the source signal VRSC to the display common electrode 10-2 via the pin PINs in response to the compensation clock signal CALCK. The display voltage VCOM is supplied to the display common electrode 10-2 in response to the source signal VRSC. The mismatch compensation operation can be performed by supplying the display voltage VCOM to the display common electrode 10-2.

When the display voltage VCOM is supplied to the display common electrode 10-2, the first alternating current voltage Vin1 and the second alternating current voltage Vin2 illustrated in FIG. 5 may be reference voltages.

FIG. 8 is a timing chart for explaining the mismatch compensation operation illustrated in FIG. Referring to FIGS. 4, 7, and 8, the SAR control logic 223 generates a compensated clock signal CALCK and outputs a compensated clock signal CALCK to the source driver 61.

The source driver 61 outputs the source signal VRSC to the display common electrode 10-2 in response to the compensation clock signal CALCK. The source signal VRSC has a slew by the parasitic capacitance Cs formed between the source driver 61 and the display common electrode 10-2. The display voltage VCOM is supplied to the display common electrode 10-2 in response to the source signal VRSC.

The differential sensing block 120 outputs an output voltage Vout in response to the display voltage VCOM. When the touch display panel 10 is not touched, the ideal output voltage Vout is the reference voltage. By performing a mismatch compensation operation, the output voltage Vout can be close to the reference voltage.

Each bit value of these selected bits Q0, Q1, Q2, Q3, and Q4 can be changed by performing a mismatch compensation operation.

FIG. 9 is a diagram for explaining an operation method of the analog front end illustrated in FIG. flow chart. Referring to FIGS. 4 through 9, the selector 110 selects two channels PCH and NCH among the plurality of channels Chx1 to Chxm, Chy1 to Chyn in response to the selection signal SEL (S10).

The first current SIGi and the second current SIGj flowing in each of the two channels NCH and PCH are used to sense the capacitance value CSIG, the parasitic element Cv, and display noise.

The current transmitter 145 senses the first current SIGi and extracts the sensed first current SIGi as the control current CC (S20). The charge amplifier 150 transmits a charge corresponding to the difference (SIGj-CC) between the second current SIGj and the control current CC to the feedback capacitor Cf, and generates an output voltage Vout corresponding to the voltage passing through the feedback capacitor Cf (S30). Therefore, the display noise can be removed.

When the touch display panel 10 is not touched, the ideal output voltage Vout is a reference voltage. However, due to a mismatch between the plurality of parasitic elements Cv, the output voltage Vout may not be the reference voltage. Therefore, a mismatch compensation operation may be more desirable to compensate for the mismatch between the plurality of parasitic elements Cv. The mismatch compensation block 200 compensates for a mismatch between the plurality of parasitic elements Vc (S40).

10 is a plan view of a touch display system in accordance with another example embodiment of the inventive concept, the touch display system including a touch controller. Referring to Fig. 10, the touch display system 1-1 is a portable device such as a smart phone, a cellular phone, a tablet PC, a laptop computer or an MP3 player. The touch display system 1-1 includes a touch display panel 11 and an integrated circuit (IC) 40-1. Touching the display panel 11 includes the sensor electrode 10-3 in common with the display Electrode 10-4.

The sensor electrode 10-3 includes a plurality of sensors having a diamond pattern. Each of the plurality of drive channels X0 to Xp (where p is a natural number) is connected to a plurality of sensors configured in columns. According to an example embodiment, the plurality of drive channels X0 to Xp may be referred to as a plurality of horizontal channels. A pulse signal from the IC 40-1 is supplied to each of the plurality of drive channels X0 to Xp. The pulse signal can be a sign pulse.

Each of the plurality of sensing channels Y0 to Yq (where q is a natural number) is connected to a plurality of sensors configured in a row. According to an example embodiment, the plurality of sensing channels Y0 to Yq may be referred to as a plurality of vertical channels. Each current is output via a plurality of sensing channels Y0 to Yq. A mutual capacitance node MC is formed at an intersection of each of the plurality of driving channels and each of the plurality of sensing channels.

11 is a block diagram of the touch display panel illustrated in FIG. Referring to FIGS. 10 and 11, when a finger or a conductive pen touches the sensor electrode 10-3, the capacitance value changes at the mutual capacitance node MC. Therefore, the integrated circuit 40-1 can extract the touch coordinates according to the change in the capacitance value. This type of conductive sensing is measured as mutual capacitance sensing.

A parasitic element may be formed between the sensor electrode 10-3 and the display common electrode 10-4. The larger the parasitic element becomes, the more the display noise can affect the touch sensitivity. Therefore, it is necessary to remove the method of displaying noise.

FIG. 12 is a block diagram of the integrated circuit illustrated in FIG. Referring to FIGS. 10 and 12, the integrated circuit 40-1 includes an AFE 100-1, an MCU 51-1, a memory 53-1, and a control logic block 55-1.

The AFE 100-1 includes an AFE controller 101-1, a driver 103-1, and a receiver 110-1. The driver 103-1 supplies a pulse signal (for example, a voltage) to each of the plurality of driving channels X0 to Xp via a plurality of driving pins PX1 to PXp (where p is a natural number). The operation of the receiver 110-1 will be explained in detail in FIG.

The AFE controller 101-1 controls the driver 103-1 or the receiver 110-1. For example, the AFE controller 101-1 can control the driver 103-1 to supply a pulse signal (eg, a voltage) to each of the plurality of drive channels X0 to Xp.

The memory 53-1 stores a digital signal output from the AFE 100-1 or a digital signal processed by the MCU 51. The MCU 51-1 calculates the touch coordinates by using the digital signals output from the AFE 100-1, and transmits the touch coordinates to the host controller 50-1. Control logic block 55-1 can receive control signals for controlling touch operations, such as horizontal sync signals and vertical sync signals, from display driver 60-1.

The display driver 60-1 includes a source driver 61-1, a gate driver 63-1, a memory 65-1, a timing controller logic block 67-1, and a power generator 69-1.

The operations and functions of each of the components 61-1, 63-1, 65-1, 67-1, and 69-1 of the display driver 60-1 and each component 61, 63 of the display driver 60 illustrated in FIG. 2, The operations of 65, 67, and 69 are similar to those of the functions, so a detailed explanation of this section is omitted.

FIG. 13 is another example embodiment of a block diagram of the integrated circuit illustrated in FIG. Referring to FIG. 10 and FIG. 13, according to an example embodiment, an integrated body The path 40-1 may include a touch controller 50-1 and a display driver 60-2. The touch controller 50-1 includes an AFE 100-2, an MCU 51-2, a memory 53-2, and a control logic block 55-2.

The AFE 100-2 includes an AFE controller 101-2, a driver 103-2, and a receiver 110-2. The operation and function of each component 100-2, 51-2, 53-2, 55-2, 101-2, 103-2 or 110-2 and each component 100-1, 51- illustrated in FIG. The operations and functions of 1, 53-1, 55-1, 101-1, 103-1, or 110-1 are similar, and thus a detailed explanation of this portion is omitted.

The display driver 60-2 includes a source driver 61-2, a gate driver 63-2, a memory 65-2, a timing control logic block 67-2, and a power generator 69-2. The operation and function of each component 61-2, 63-2, 65-2, 67-2 or 69-2 of the display driver 60-2 and each component 61, 63 of the display driver 60 illustrated in FIG. 2, The operation of 65, 67 or 69 is similar to the function, so a detailed explanation of this part is omitted.

14 is a block diagram of the receiver illustrated in FIG. Referring to FIG. 12 and FIG. 14, the receiver 110-1 includes: a plurality of pins PY1 to PYq; a plurality of unity gain buffer amplifiers 130-1, 130-2, ..., and 130-q; and a plurality of first current replicas. Circuits 140-1, 140-2, ... and 140-(q-1); a plurality of second current replica circuits 160-1, 160-2, ... and 160-(q-1); Charge amplifiers 150-1, 150-2, ... and 150-r, where r is a natural number.

Each of the plurality of pins PIN1 to PINh is connected to each of the plurality of sensing channels Y0 to Yq. The first current SI1 and the second current SI2 are received via the plurality of pins PIN1 to PINh. The first current transmitter 135-1 senses the first current SI1 and extracts the sensed first current SI1 as the first A control current CC1.

FIG. 15 is a block diagram of the first current transmitter illustrated in FIG. 14. Referring to FIGS. 14 and 15, the current transmitter 135-1 includes a unity gain buffer amplifier 130-1 and a first current replica circuit 140-1.

The unity gain buffer amplifier 130-1 includes an operational amplifier 131-1. The operational amplifier 131-1 includes an inverting terminal receiving the first current SI1, a non-inverting terminal connected to the ground, and an output terminal connected to the inverting terminal. The operation of the first current replica circuit 140-1 is similar to the operation of the current replica circuit 140 illustrated in FIG. 6, and thus a detailed explanation of this portion is omitted.

Each of the first current SIGi and the control current CC illustrated in FIG. 6 corresponds to each of the first current SI1 and the first control current CC1 in FIG. Although the non-inverting terminal IN2 of the operational amplifier 131 is connected to the first alternating voltage Vin1 in FIG. 6, the non-inverting terminal of the operational amplifier 131-1 is connected to the reference voltage in FIG. For example, the reference voltage can be a ground voltage.

The second current transmitter 135-2 senses the second current SI2 and extracts the sensed second current SI2 as the second control current CC2. The detailed operation of the second current transmitter 135-2 will be explained in FIG.

The charge amplifier 150-1 converts the current difference (CC2-CC1) between the first control current CC1 and the second control current CC2 into an output voltage Vout. Each of the first current SI1 and the second current SI2 includes display noise transmitted by the parasitic element. By converting the current difference between the first control current CC1 and the second control current CC2 into the output voltage Vout1, the display noise can be removed.

The charge amplifier 150-1 includes an output terminal connected to the inverting terminal of the first current replica circuit 140-1 and the second current replica circuit 160-1, the non-inverting terminal connected to the ground, and the output output voltage Vout1. Further, the charge amplifier 150-1 includes a feedback resistor Rf and a feedback capacitor Cf connected in parallel between the inverting terminal and the output terminal.

The receiver 110-1 further includes an analog/digital converter ADC and an FIR filter. An ADC (not shown) converts the output voltage output from each of the charge amplifiers 150-1, 150-2, ..., or 150-r into a digital signal. The FIR filter is configured to remove noise of the digital signal. The digital signal with the noise removed is transmitted to the MCU 51-1.

16 is a block diagram of the second current transmitter illustrated in FIG. Referring to FIGS. 14 and 16, the second current transmitter 135-2 includes a unity gain buffer amplifier 130-2 and a second current replica circuit 160-1.

The unity gain buffer amplifier 130-2 includes an inverting input terminal that receives the second current SI2, a non-inverting input terminal that receives the ground voltage, and an output terminal that is coupled to the inverting terminal. The unity gain buffer amplifier 130-2 includes an operational amplifier 131-2. The operational amplifier 131-2 is similar to the operational amplifier 131 illustrated in FIG. 6, and thus a detailed explanation of this portion is omitted. The non-inverting terminal of the operational amplifier 131-2 is connected to ground.

Similar to the first current SIGi of FIG. 6, the second current SI2 is equal to the difference between the current ISP1 flowing in the operational amplifier 131-2 and the current ISN1. The second current SI2 can be expressed as shown in Equation 3.

[Equation 3] SI2=ISP1-ISN1

The current ISP1 is a current flowing in the first transistor P1 in response to the first control voltage CS3, and the current ISN1 is a current flowing in the second transistor N1 in response to the second control voltage CS4.

The second current replica circuit 160-1 outputs the second control current CC2 based on the plurality of control voltages CS3 and CS4 output from the unity gain buffer amplifier 130-2. The second current replica circuit 160-1 includes a first current mirror 160-2 and a second current mirror 160-3. Each of the first current mirror 160-2 and the second current mirror 160-3 is connected between the power supply node VDD and the ground node VSS. Each of the first current mirror 160-2 and the second current mirror 160-3 includes a plurality of transistors P2, P3, P4, N2, N3, and N4.

The current ISN4 that replicates the current ISP2 flowing in one side of the first current mirror 160-2 flows in the other side of the first current mirror 160-2 in response to the first control voltage CS3. The current ISP4 that replicates the current ISN2 flowing in one side of the second current mirror 160-3 flows in the other side of the second current mirror 160-3 in response to the second control voltage CS4.

The second control current CC2 can be expressed as shown in Equation 4.

[Equation 4]-CC2=ISN4-ISP4

The size (length and width) of each of the plurality of transistors MP1, MP2, MN1, and MN2 is identical to each other. The first transistor P1 and the third transistor P2 are controlled by the third control voltage CS3, and the second transistor N1 and the fourth transistor N2 are controlled by the fourth control voltage CS4. Therefore, the amount of current ISP1 flowing in the first transistor P1 is the same as the amount of current ISP2 flowing in the third transistor P2, and the current flowing in the second transistor N1 The amount of the flow ISN1 is the same as the amount of the current ISN2 flowing in the fourth transistor N2.

According to the current mirroring, the amount of current ISN4 is the same as the amount of current ISP2, and the amount of current ISP4 is the same as the amount of current ISN2. Therefore, the amount of current ISN4 is the same as the amount of current ISP1, and the amount of current ISP4 is the same as the amount of current ISN1.

The second current SI2 sensed is extracted as the second control current CC2 by connecting the plurality of current mirrors 160-3 and 160-4 to the unity gain buffer amplifier 130-2 and sensing the second current SI2.

Figure 17 is a flow chart for explaining the operation method of the receiver illustrated in Figure 14. Referring to FIGS. 14 to 17, the receiver 110-1 receives the first current SI1 and the second current SI2 (S10).

The first current transmitter 135-1 senses the first current SI1 and extracts the sensed first current SI1 as the first control current CC1 (S20). The second current transmitter 135-2 senses the second current SI2 and extracts the sensed second current SI2 as the second control current CC2 (S30).

The charge amplifier 150-1 transmits a charge corresponding to the current difference (CC2-CC1) between the first control current CC1 and the second control current CC2 to the feedback capacitor Cf, and generates an output voltage corresponding to the voltage passing through the feedback capacitor Cf. Vout (S40). Therefore, the display noise can be removed.

A touch controller according to an example embodiment of the inventive concept, a method of operating the same, and a device having the touch controller can remove a display at a common electrode by differentially sensing two of the plurality of channels Show noise. In addition, a touch controller according to an example embodiment of the inventive concept, The method of operation and the device having the touch controller can remove noise due to mismatch between parasitic elements by compensating for mismatch between parasitic elements.

While the example embodiment has been particularly shown and described with reference to the embodiments of the embodiments of the invention Make various changes.

1‧‧‧Touch display system

1-1‧‧‧Touch display system

10‧‧‧Touch display panel

10-1‧‧‧Sensor electrode

10-2‧‧‧Display common electrode

10-3‧‧‧Sensor electrode

10-4‧‧‧Display common electrode

11‧‧‧Touch display panel

40‧‧‧Integrated circuit

40-1‧‧‧Integrated circuit

50‧‧‧Touch controller

50-1‧‧‧Host Controller

51‧‧‧Micro Control Unit (MCU)

51-1‧‧‧Micro Control Unit

51-2‧‧‧Micro Control Unit

53‧‧‧ memory

53-1‧‧‧ memory

53-2‧‧‧ Memory

55‧‧‧Control logic block

55-1‧‧‧Control logic block

55-2‧‧‧Control logic block

60‧‧‧ display driver

60-1‧‧‧ display driver

60-2‧‧‧ display driver

61‧‧‧Source Driver

61-1‧‧‧Source Driver

61-2‧‧‧Source Driver

63‧‧‧gate driver

63-1‧‧‧ Gate Driver

63-2‧‧‧ Gate Driver

65‧‧‧ memory

65-1‧‧‧ memory

65-2‧‧‧ memory

67‧‧‧Sequence Control Logic Block

67-1‧‧‧ Timing Controller Logic Block

67-2‧‧‧Sequence Control Logic Block

69‧‧‧Power generator

69-1‧‧‧Power generator

69-2‧‧‧Power generator

70‧‧‧Host Controller

70-1‧‧‧Host Controller

100‧‧‧ analog front end (AFE)

100-1‧‧‧ analog front end

100-2‧‧‧ analog front end

101-1‧‧‧AFE Controller

101-2‧‧‧AFE Controller

103-1‧‧‧ drive

103-2‧‧‧ drive

110‧‧‧Selector

110-1‧‧‧ Receiver

110-2‧‧‧ Receiver

120‧‧‧Differential sensing block

121‧‧‧Low-pass filter

123‧‧‧ Analog/Digital Converter

125‧‧‧Limited impulse response filter

130‧‧‧Unity Gain Buffer Amplifier

130-1 to 130-q‧‧‧ unity gain buffer amplifier

131‧‧‧Operational Amplifier

131-1‧‧‧Operational Amplifier

131-2‧‧‧Operational Amplifier

135-1‧‧‧First Current Transmitter

135-2‧‧‧Second current transmitter

140‧‧‧current replica circuit

140-1~140-(q-1), CCC‧‧‧ first current replica circuit

145‧‧‧current transmitter

150‧‧‧Charger amplifier

150-1~150-r‧‧‧Charger amplifier

151‧‧‧Operational Amplifier

160-1~160-(q-1), CCCB‧‧‧second current replica circuit

200‧‧‧ mismatch compensation block

210‧‧‧ capacitor array

211‧‧‧Switch

213‧‧‧Switcher

215‧‧‧Switch

217‧‧‧Switcher

219‧‧‧Switcher

220‧‧‧Select bit generator

221‧‧‧ comparator

223‧‧‧Sequential approximation register control logic

C~16C‧‧‧ capacitor

CALCK‧‧‧compensated clock signal

CC‧‧‧Control current

CC1‧‧‧First control current

CC2‧‧‧second control current

CC2-CC1‧‧‧ Current difference

Cf‧‧‧ feedback capacitor

Chx1 to Chxm‧‧‧ channels

Chy1 to Chyn‧‧ channel

COMP‧‧‧ comparison signal

CON‧‧‧ node

Cs‧‧‧ parasitic capacitance

CS1‧‧‧First control voltage

CS2‧‧‧second control voltage

CS3‧‧‧First control voltage / third control voltage

CS4‧‧‧Second control voltage / fourth control voltage

C _SIG ‧‧‧Capacitance

Cv‧‧‧ parasitic components

IN1‧‧‧ first input

IN2‧‧‧ second input

IN3‧‧‧ third input

IN4‧‧‧ fourth input

IND1‧‧‧ current

IND2‧‧‧ current

IPD1‧‧‧ Current

IPD2‧‧‧ Current

ISN1‧‧‧ Current

ISN2‧‧‧ current

ISN4‧‧‧ Current

ISP1‧‧‧ Current

ISP2‧‧‧ Current

ISP4‧‧‧ current

MC‧‧‧ mutual capacitance node

MN1‧‧‧second transistor

MN2‧‧‧4th transistor

MP1‧‧‧first transistor

MP2‧‧‧ third transistor

N1‧‧‧second transistor

N2‧‧‧ fourth transistor

N3‧‧‧O crystal

N4‧‧‧O crystal

NCH‧‧ channel

ON1‧‧‧ first output

ON2‧‧‧ second output

P1‧‧‧First transistor

P2‧‧‧ third transistor

P3‧‧‧O crystal

P4‧‧‧O crystal

PCH‧‧ channel

PIN1 to PINh‧‧‧ pin

PINo‧‧‧ pin

PINs‧‧‧ pin

PX1 to PXp‧‧‧ drive pin

PY1 to PYq‧‧‧ pin

Q0~Q5‧‧‧Select bit

/Q0~/Q5‧‧‧Select bit

Rf‧‧‧ feedback resistor

SEL‧‧‧Selection signal

SI1‧‧‧First current

SI2‧‧‧second current

SIGi‧‧‧First current

SIGj‧‧‧second current

SIGj-CC‧‧‧ current difference

VCOM‧‧‧ display voltage

VDD‧‧‧ power node

Vin1‧‧‧First AC voltage

Vin2‧‧‧second AC voltage

Vout‧‧‧ output voltage

VSS‧‧‧ Grounding node

X0 to Xp‧‧‧ drive channel

Y0 to Yq‧‧‧ sensing channel

1 is a plan view of a touch display system including a touch controller in accordance with an example embodiment of the inventive concept.

2 is a block diagram of the integrated circuit illustrated in FIG. 1.

3 is a cross-sectional view of the touch display panel illustrated in FIG. 1.

4 is a block diagram of the analog front end illustrated in FIG.

FIG. 5 is a block diagram of the differential sensing block illustrated in FIG. 4.

FIG. 6 is a circuit diagram of the current transmitter illustrated in FIG. 5.

FIG. 7 is a block diagram of the mismatch compensation block illustrated in FIG. 4.

FIG. 8 is a timing chart for explaining the mismatch compensation operation illustrated in FIG.

FIG. 9 is a flow chart for explaining the operation method of the analog front end illustrated in FIG. 4.

10 is a plan view of a touch display system in accordance with another example embodiment of the inventive concept, the touch display system including a touch controller.

11 is a block diagram of the touch display panel illustrated in FIG.

FIG. 12 is an example embodiment of a block diagram of the integrated circuit illustrated in FIG.

FIG. 13 is another example embodiment of a block diagram of the integrated circuit illustrated in FIG.

14 is a block diagram of the receiver illustrated in FIG.

FIG. 15 is a block diagram of the first current transmitter illustrated in FIG. 14.

16 is a block diagram of the second current transmitter illustrated in FIG.

Figure 17 is a flow chart for explaining the operation method of the receiver illustrated in Figure 14.

10-1‧‧‧Sensor electrode

10-2‧‧‧Display common electrode

51‧‧‧Micro Control Unit

61‧‧‧Source Driver

100‧‧‧ analog front end

110‧‧‧Selector

120‧‧‧differential sensing block

121‧‧‧Low-pass filter

123‧‧‧ Analog/Digital Converter

125‧‧‧Limited impulse response filter

200‧‧‧mismatch compensation block

Chx1‧‧ channel

Chyn‧‧‧ channel

Cs‧‧‧ parasitic capacitance

Cv‧‧‧ parasitic components

IN1‧‧‧ first input

IN3‧‧‧ third input

NCH‧‧ channel

PCH‧‧ channel

PIN1 to PINh‧‧‧ pin

PINo‧‧‧ pin

PINs‧‧‧ pin

SEL‧‧‧Selection signal

SIGi‧‧‧First current

SIGj‧‧‧second current

Vout‧‧‧ output voltage

Claims (29)

A method for operating a touch controller, comprising: receiving a plurality of currents through a plurality of channels respectively; sensing a first current of the currents and extracting the sensed first current as a first control current; A charge corresponding to a difference between the first control current and a second one of the currents is converted into an output voltage. The method of claim 1, further comprising: selecting respective channels of the first current and respective channels of the second current in response to the selection signal. The method of claim 1, wherein the converting to the output voltage comprises converting a current difference between the second current and the first control current to the output voltage. The method of claim 1, further comprising: compensating for a mismatch between the plurality of parasitic elements between the common electrode and the sensor electrode in response to the output voltage. The method of claim 4, wherein the compensating for the mismatch between the parasitic elements comprises: comparing the output voltage with a comparison voltage, and outputting a plurality of selection bits according to the comparison result; Selecting at least one of the plurality of capacitors by selecting the bits; and compensating for the mismatch based on the selected at least one capacitor. The method of claim 1, wherein the converting comprises: extracting the sensed second current as a second control current; converting the current difference between the second control current and the first control current For this output voltage. A touch controller comprising: a plurality of pins, each of the pins being connected to one of a plurality of channels; a selector for selecting two of the channels in response to the selection signal; and a difference A motion sensing block configured to convert a charge to an output voltage corresponding to a difference between a first current flowing in each of the two channels and a second current. The touch controller of claim 7, wherein the differential sensing block comprises: a current transmitter configured to sense the first current and extract the sensed one a current as a control current; and a charge amplifier configured to convert a current difference between the second current and the control current to the output voltage. The touch controller of claim 8, wherein the current transmitter comprises: a unity gain buffer amplifier, the unity gain buffer amplifier comprising a first input configured to receive the first current, the group a second input receiving the alternating voltage, and a first output connected to the first input; A current replica circuit comprising a second output for extracting the control current based on a plurality of control voltages output from the unity gain buffer amplifier. The touch controller of claim 9, wherein the current replica circuit comprises: a source circuit and a drain circuit, wherein the source circuit and the drain circuit are connected in series to a power node of the unity gain buffer amplifier; Between the ground node and the ground node, wherein each of the source circuit and the drain circuit is configured to operate based on the control voltages. The touch controller of claim 10, wherein the control current is a difference between a current flowing in the drain circuit and a current flowing in the source circuit. The touch controller of claim 7, wherein the charge amplifier is configured to use a reference voltage if a plurality of sensors connected to each of the channels are not touched This output voltage is output. The touch controller of claim 7, further comprising: a mismatch compensation block, the mismatch compensation block being connected to the display common electrode, the mismatch compensation block being configured to respond to the output The voltage compensates for a mismatch between the plurality of parasitic elements between the display common electrode and the sensor electrode. a touch controller as described in claim 13 of the patent application, wherein The mismatch compensation block includes: a capacitor array including a plurality of capacitors; and a selection bit generator configured to compare the output voltage with the comparison voltage, and selecting the comparison result according to the comparison result At least one of the capacitors and a plurality of select bits are generated. The touch controller of claim 14, wherein the select bit generator comprises: a comparator configured to compare the comparison voltage with the output voltage and output a comparison signal; and successively Approximate register (SAR) control logic configured to generate the plurality of selection bits in response to the comparison signal. The touch controller of claim 15, wherein the successive approximation register control logic is configured to generate a compensated clock signal and supply the compensated clock signal to the source driver. A touch controller includes: a plurality of pins, each of the pins being connected to a plurality of channels; a first current transmitter configured to sense a flow in one of the channels a first current, and extracting the sensed first current as a first control current; a second current transmitter configured to sense a flow in the other of the channels Two currents, and extracting the sensed second current as a second control current; and a charge amplifier configured to control the first control The current difference between the flow and the second control current is converted to an output voltage. The touch controller of claim 17, further comprising: a plurality of driving pins, the driving pins being connected to the driving channels, and an integrated circuit configured to A symbol pulse signal is supplied to each of the drive channels. The touch controller of claim 17, wherein the first current transmitter comprises: a unity gain buffer amplifier, the unity gain buffer amplifier comprising an inverting input configured to receive the first current, a non-inverting input configured to receive a reference voltage and an output coupled to the inverting terminal; and a current replica circuit configured to output a plurality of control voltages from the unity gain buffer amplifier The first control current is extracted. The touch controller of claim 19, wherein the current replica circuit comprises: a source circuit and a drain circuit, wherein the source circuit and the drain circuit are connected in series to a power node of the unity gain buffer amplifier; Between the ground node and the ground node, wherein each of the source circuit and the drain circuit is configured to operate based on the plurality of control voltages. The touch controller of claim 17, wherein the second current transmitter comprises: a unity gain buffer amplifier comprising an inverting input configured to receive the second current, a non-inverting input configured to receive a reference voltage, and an output coupled to the inverting terminal; A current replica circuit configured to extract the second control current based on a plurality of control voltages output from the unity gain buffer amplifier. The touch controller of claim 21, wherein the current replica circuit comprises: a plurality of current mirrors each connected between a power node of the unity gain buffer amplifier and a ground node, wherein the current Each of the current mirrors is configured to operate based on the plurality of control voltages. A touch display system comprising: a touch display panel; and a touch controller connected to the touch display panel by a plurality of channels, wherein the touch controller comprises a current transmitter, The current transmitter is configured to sense a first current of a plurality of currents flowing through each of the plurality of channels and extract the sensed first current as a control current; and a charge amplifier, the charge The amplifier is configured to convert a charge corresponding to a difference between the control current and a second one of the currents to an output voltage. a touch display system as described in claim 23, The touch display system is a portable device. A touch display system includes: a display panel configured to generate a plurality of currents through a plurality of channels respectively; an integrated circuit coupled to the plurality of channels, the integrated circuit including a differential sensor configured to receive a first current associated with the first channel and a second current associated with the second channel to generate a first current and the second current The difference between the charges and converts the charge into an output voltage. The touch display system of claim 25, wherein the integrated circuit further comprises: a mismatch compensator configured to compensate for parasitic capacitance in the display panel based on the output voltage . The touch display system of claim 26, wherein the mismatch compensator comprises: a bit selection generator configured to receive the output voltage, compare the output voltage and compare And generating a plurality of select bits based on the comparison; and a capacitor array configured to select at least one of the plurality of capacitors based on the plurality of select bits to compensate for the parasitic capacitance. The touch display system of claim 26, wherein the mismatch compensator is configured to selectively change a capacitance between the sensor electrode and the display common electrode to compensate for parasitics in the display panel capacitance. The touch display system of claim 25, wherein the first channel and the second channel are adjacent.