TW201123537A - Light emitting devices with embedded void-gap structures through bonding of structured materials on active devices - Google Patents

Abstract

A method of fabricating optoelectronic devices with embedded void-gap structures on semiconductor layers through bonding is provided. The embedded void-gaps are fabricated on a semiconductor structure by bonding a patterned layer or slab onto a flat surface, or by bonding a flat layer or slab onto a patterned surface. The void-gaps can be filled with air, gases, conductive or dielectric materials, or other substances, in order to provide better isolation of optical modes from dissipative regions, or better light extraction properties.

Description

201123537 VI. Description of the Invention: [Technical Field] The present invention relates to structured materials for obtaining better light-emitting diodes and lasers through high extraction efficiency or better isolation of active layers from metal electrodes, and in particular There is a light-emitting device having an embedded void structure via a bonded structural material on an active device. This application claims to be "LIGHT EMITTING DEVICES WITH EMBEDDED AIR GAP STRUCTURES THROUGH BINDING" on August 28, 2009, by James S. Speck, Claude CA Weisbuch and Elison de Nazareth Matioli, in accordance with 35 USC Section 119(e). OF STRUCTURED MATERIALS ON ACTIVE DEVICES", the right of the application and the US Provisional Application No. 61/238,003, the assignee number 30794.310-US-P1 (2009-494-1), which is incorporated by reference. The way is incorporated in this article. This application is related to the following patents, publications, and applications: U.S. Patent No. 7,723,745, issued May 25, 2010, issued on June 5, 2008, as US Patent Publication No. 2008/0128737, February 13, 2008, as US Utility Application No. 12/03 0,697, filed by Claude CA Weisbuch, Aurelien JF David, James S. Speck, and Steven P. DenBaars, entitled "HORIZONTAL EMITTING, VERTICLE EMITTING, BEAM SHAPED, DISTRIBUTED FEEDBACK (DFB) LASERS BY GROWTH OVER A PATTERNED SUBSTRATE", attorney profile number 30794.121-US-C 1 (2005-144-2), which is one of the US Patent No. 7,345,298, US Patent 150459.doc 201123537

No. 7,345,298 was issued on March 18, 2008, and was published on August 31, 2006 as US Patent Publication 2006/0194359, and on February 28, 2005 as US Utility Application No. 11/067,957 by Claude CA. Application by Weisbuch, Aurelien JF David, James S. Speck and Steven P_ DenBaars, entitled "HORIZONTAL EMITTING, VERTICAL EMITTING, BEAM SHAPED, DISTRIBUTED FEEDBACK (DFB) LASERS BY GROWTH OVER A PATTERNED SUBSTRATE", Agent File Number 2005-144 -1(30794.1 21-US-01); US Utility Application No. 12/822,888, filed on June 24, 2010 by Claude CA Weisbuch and Shuji Nakamura, entitled "HORIZONTAL EMITTING, VERTICAL EMITTING, </ br> </ br> No. 7,768,024 was issued on August 3, 2010, and was published as US Patent Publication No. 2007/0125995 on June 7, 2007. December 4, 2006, as US Utility Application No. 1 1/633, 148, filed by Claude CA Weisbuch and Shuji Nakamura, named "IMPROVED HORIZONTAL EMITTING, VERTICAL EMITTING, BEAM SHAPED, DISTRIBUTED FEEDBACK (DFB) LASERS FABRICATED BY GROWTH OVER A PATTERNED SUBSTRATE WITH MULTIPLE OVERGROWTH", attorney profile number 2005-72 1-2 (30794.143-US-U1), which is claimed at 150459 according to 35 USC Section 119(e). doc 201123537 December 2, 2005 by US Provisional Application No. 60/741,935, entitled "IMPROVED HORIZONTAL EMITTING, VERTICAL EMITTING, BEAM SHAPED, DISTRIBUTED FEEDBACK (DFB) LASERS FABRICATED BY GROWTH OVER A PATTERNED SUBSTRATE WITH MULTIPLE OVERGROWTH" by Claude CA Weisbuch and Shuji Nakamura , agent file number 30794.143-US-P1 (2005-721);

U.S. Utility Application No. 12/834,453, filed on July 12, 2010 by Aurelien JF David, Claude CA Weisbuch, and Steven P. DenBaars, entitled "HIGH EFFICIENCY LIGHT EMITTING DIODE (LED) WITH OPTIMIZED PHOTONIC CRYSTAL EXTRACTOR", the agent's file number 2005-1 98-3 (30794.126-US-C1), which is one of the US Patent Publication No. 2009/0305446, and the US Patent Publication No. 2009/0305446 is in 2009. Announced on the 10th of August, on August 13th, 2009, as US Utility Application No. 12/541,061, applied by Aurelien JF David, Claude CA Weisbuch and Steven Den DenBaars, named "HIGH EFFICIENCY LIGHT EMITTING DIODE (LED WITH OPTIMIZED PHOTONIC CRYSTAL EXTRACTOR, agent file number 2005-198-2 (30794.126-US-Dl), which is a division of US Patent No. 7,582,910, and US Patent No. 7,582,910 is September 1, 2009 The certificate was issued on August 31, 2006 as US Patent Publication No. 2006/0192217, and on February 28, 2005 as US Utility Application No. 11/067,956 by Aurelien JF. David, Claude CA Weisbuch and Steven P. DenBaars filed an application entitled "HIGH EFFICIENCY 150459.doc 201123537 LIGHT EMITTING DIODE (LED) WITH OPTIMIZED PHOTONIC CRYSTAL EXTRACTOR", Agent File Number 2005-198-1 (30794.126-US-01 );

U.S. Utility Application No. 12/793,862, filed on June 4, 2010 by Claude C_A. Weisbuch, Aurelien J. F. David, James S. Speck, and Steven P. DenBaars, entitled "SINGLE OR MULTI -COLOR HIGH EFFICIENCY LIGHT EMITTING DIODE (LED) BY GROWTH OVER A PATTERNED SUBSTRATE", attorney profile number 2005-145-3 (3 0794.122-US-C2), which is one of the US patents No. 7755,096, USA Patent No. 7755,096 was issued on July 1, 2010, and was published as US Patent Publication No. 2008/0087909 on April 17, 2008, and as a US utility application on October 24, 2007. Case No. 1 1/923, 414 was filed by Claude CA Weisbuch, Aurelien J. F. David, James S. Speck and Steven P. DenBaars, entitled "SINGLE OR MULTI-COLOR HIGH EFFICIENCY LIGHT EMITTING DIODE (LED) BY GROWTH OVER A PATTERNED SUBSTRATE", agent file number 2005-145-2 (30794.122-US-Cl), which is one of the US patents No. 7,291,864, and US Patent No. 7,291,864 issued on November 6, 2007. , on September 14th, 2006 as a US special The publication of the publication 2006/0202226 was filed on February 28, 2005 as US Utility Application No. 11/067,910 by Claude CA Weisbuch, Aurelien JF David, James S. Speck and Steven P. DenBaars. SINGLE OR MULTI-COLOR HIGH EFFICIENCY LIGHT EMITTING DIODE (LED) BY GROWTH OVER 150459.doc 201123537 A PATTERNED SUBSTRATE", Agent File Number 2005-145-1 (30794.122-US-C1); and US Provisional Application No. 61/ No. 367239, filed on July 23, 2010 by Elison de Nazareth Matioli, Claude CA Weisbuch, James S. Speck and Evelyn L. Hu, entitled "OPTOELECTRONIC DEVICES WITH EMBEDDED VOID STRUTURES", Agent File Number 2009 -493-l (30794.385-US-Pl); All of these references are incorporated herein by reference. [Prior Art] The present invention relates to the improvement and fabrication of semiconductor light-emitting diodes (LEDs) and lasers by means of buried grating mirrors and photonic crystals (PhC), and more particularly, the substrate A new structure obtained by growth on the grating and photonic crystal patterning, as described in the above-referenced patents, publications and applications. Such a cross-reference is also directed to a method for incorporating a low refractive index layer into a growth structure in accordance with the patent, publication and application, wherein the low refractive index layer helps to confine light to the vertical direction. The purpose of this layer is to reduce or prohibit light that cannot be efficiently extracted by a surface PhC, as described in US Patent Publication No. 2006/0192217, which is incorporated herein by reference. mold. In a typical PhC LED, the buffer layer and the active layer are typically made of GaN, the low refractive index confinement layer is made of AlGaN, and the quantum well (QW) is made of GalnN, as in US Patent Publication No. 2006/0192217 The number (which is incorporated herein by reference). This structure is different from a typical double heterostructure LED (where two low refractive index layers are used on both sides of the active area to limit the carriers in the active layer to 150459.doc 201123537). In U.S. Patent Publication No. 2/6/922, filed hereby incorporated herein by reference in its entirety, in its entirety, in the &lt;RTIgt; Helps launch into and with

PhC is in a mode of light guided by strong interactions. As used in double heterostructure LEDs, placing another low refractive index layer between the active layer and phc will limit the mode around the active layer and prevent the modes from overlapping the phc, thus avoiding δ 玄 PhC The guide mode is effectively diffracted into the air. The confinement layer can also be obtained via a lateral epitaxial overgrowth (LEO) of one of the nitride-based materials on a patterned growth mask layer, as disclosed in US Patent Publication No. 2008/0087909, which is incorporated herein by reference. As described in this article). In this case, the composite layer comprising the masking material and the overgrown material constitutes a low refractive index confinement layer and it can also function as a light extraction PhC by appropriate design. In in-plane lasers, the laser mode typically interacts extremely strongly with the metal top electrode, resulting in propagation losses that increase the threshold current and reduce power efficiency. Doping the semiconductor contact layer can also cause propagation losses, especially P-type doped contact layers (see, for example, s. Uchida et al., IEEE J〇urnai 〇f).

Selected Topics In Quantum Electronics, Vol. 9, No. 5, September/October 2, pp. 1252, which is incorporated herein by reference. Typically, an optical confinement layer is used to limit the laser mode away from the metal top electrode and the contact layer. The confinement layers have a refractive index that is lower than the refractive index of the active layer, and thus slightly restricts light waves from entering the active layer, thereby causing the laser mode to interact more strongly with one of the active materials (eg, reducing the laser radiation) Limit current) and cause the mold to be weaker with one of the contact layers and the electrodes for I50459.doc 201123537. However, there are several compromises. A thick, high refractive index (meaning high energy bandgap) confinement layer (e.g., made of AK}aN material) with well-defined properties also has poor current conduction properties, resulting in increased device resistance and operating voltage. In addition, if due to the lattice mismatch between AlGaN and other materials of the structure, it is difficult to achieve the growth of the yttrium-containing material without introducing large misalignment, degree or uniform crack. Due to these limitations, the refractive index and thickness of the confinement layer in the laser have insufficient limiting properties and they cause overflow of one of the laser modes and interaction of the laser mode with the metal electrode. A better confinement layer of the laser can be obtained via a nitride-based material based on a patterned growth mask layer, such as U.S. Patent Publication Nos. 2006/0194359 and 2007/0125995 (which are incorporated by reference). The manner is as described in this document). Due to the high refractive index difference between the masking material (which may even be air), extremely good limiting properties can be obtained, while the perforations of the masking material contain good conductive semiconductor materials while preserving good electrical conductivity properties. Although it can be incorporated by reference to various growth techniques such as LEO (see, for example, U.S. Patent Publication Nos. 2006/0194359, 2007/0125995, 2006/0192217, and 2008/0087909, hereby incorporated herein by reference. The embedded dielectric structure is obtained, but the various structures of interest can also be obtained by directly incorporating a passive structured material on the active LED structure, as described in more detail in this application. SUMMARY OF THE INVENTION In order to overcome the limitations of the above-mentioned prior art, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present disclosure discloses various bonding techniques and structures for obtaining semiconductor devices. Structured layer. The pattern of the structured layers can be random or periodic and configured in one, two or three dimensions. Providing a combination of 锄; 生1古由, ο. k A simple method of optoelectronic devices with embedded void structures on structured semiconductor materials. In particular, the interstitial voids are fabricated on a semiconductor structure by bonding a patterned material sheet on a flat semiconductor surface or by bonding a flat panel to a patterned structure. The voids may be filled with air, a conductive material or a dielectric material and may be advantageously used for optoelectronics for several reasons, such as better isolation of the light film from the consumable area of the laser or better light extraction properties of the LED. Device application. This is an easy manufacturing method because it only contains a combination of materials. This is a planar and manufacturable method for embedded void structures. Air or other materials can be used to fill the gap. Multiple combinations may prove useful for a given application or implementation. [Embodiment] Reference is made to the drawings, in which like reference characters In the following description of the preferred embodiments, reference to the accompanying drawings It will be appreciated that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention. SUMMARY 150459.doc 201123537 The present invention describes a method of producing an embedded void structure (such as void PhC) of an optoelectronic device, wherein the void structures are embedded in one or more of a top or bottom surface that is subsequently bonded to the active device structure. In layers. &quot;void&quot; as used herein is intended to mean voids, gaps, holes, perforations, and the like that are created in one or more layers of a structure. The gap can be filled with air, a rolled body, a conductive material, a dielectric material, or other substance. Moreover, the voids may comprise a polygonal, cylindrical or spherical feature portion 'a randomly shaped feature portion, a randomly distributed feature portion, a periodic or quasi-periodic distribution shaped feature portion. Furthermore, the voids can be arranged in a one-dimensional (10)), two-dimensional (2D) or three-dimensional (four) pattern. The voids may also be formed by continuous joining, by connecting holes, by connecting posts or by both connecting holes and connecting posts. These and further aspects of the invention are described in detail below. The operation of the concepts developed in the present invention relies on refractive index differences. A void pattern is created in the layer of material to be joined and the resulting void is left empty or filled with a material having a refractive index different from that of the material layer or active device structure to achieve this property. The growth of the embedded material on certain regions, such as dielectrics, is not used to form voids by the methods disclosed herein. Alternatively, in the present invention, the voids are naturally formed during bonding because the bonded layers have been patterned prior to being bonded to the active device structure or because the bonded systems are solid on one of the patterned surfaces of the active device structure. . Although the present invention discloses a simple method, the resulting structural growth retention can produce one planar aspect at low cost. Technical Description A characteristic portion of one of the gap-based devices (such as LEDs or lasers) that typically has a lower refractive index than the surrounding material. It is mainly used for two purposes. The first objective is to provide an optical limit due to the lower average refractive index of the layer comprising the voids. Figure 1 is a schematic illustration of an emissive mode in a thick active layer PhC LED structure. The LED structure 100 includes a sapphire substrate 1〇2, 1〇4, a quantum well layer 106, and a PhC 108. A guided mode comprising two low-order modes, ip, ip, and a higher-order mode 114, is also shown. Because the LED 100 does not have a void layer ', the optical modes 110, 112, 114 are widely delocalized on the structure 1 and the low-order guided modes 110, 112 and the light extraction structure (such as PhC 108) are weakly mutually effect. In particular, the lower order modes 丨, 1 丨 2 have a smaller overlap with one of the PhCs 108, so that the extraction of the guided modes 11 〇, 112 is inefficient. Figure 2 is a schematic illustration of one of the emissive modes in an active layer phc LED structure having an AlGaN optical confinement layer. The LED structure 200 includes a sapphire substrate 202, a GaN layer 204, an AlGaN optical confinement layer 206, a quantum well layer 208, and a PhC 210. A guided mode of emitted light is also shown, comprising two lower order modes 212, 2 14 and a higher order mode 216. There are three types of molds that are excited by quantum emission from the quantum well 208: a lower order guided mode 212 positioned below the AlGaN optical confinement layer 206, which has a small overlap with one of the PhC 2 1 0 and is subsequently Extremely poorly extracted, but at the same time, they are weakly excited only by the quantum wells 208 having a poor overlap with them, etc.; a lower order mode 214 positioned over the AlGaN optical confinement layer 206, which will be associated with the PhC 210 The interaction of the strong 150459.doc 12 201123537 occurs and will therefore be efficiently extracted; the higher order mode 2 1 6 is not restricted to the eight 10 &amp; 1^ optical confinement layer 206 and is it equivalent? 11€210 overlaps well, so it is well extracted. In particular, the inclusion of the AlGaN optical confinement layer 206 selects the emission 214 that is well extracted by the surface PhC 210 from the quantum well. Fig. 3 is a schematic view showing one of the laser structures having the size values of the active layer and the AlGaN optical confinement layer. The laser structure 300 includes a substrate 302, a buffer layer 304, a GaN n-type contact layer 306, a bottom metal electrode 308, an AlGaN optical confinement layer 3 10, 3 12, a GaN layer 314, a quantum well layer 316, and a GaN p. The contact layer 318 and the top metal electrode 32 are. Optical laser wave 322 is also shown. The AlGaN optical confinement layers 3 10, 3 12 are low refractive index layers (for laser limited purposes, lasers are more demanding for them). In particular, as shown in Figure 3, for an in-plane laser, the AlGaN optical confinement layers 310, 312 help to limit the light surrounding the luminescent quantum well 316 for two purposes: the laser mode and the quantum The interaction between the wells is enhanced, resulting in a larger modal gain and, therefore, a threshold current. The mold system is constrained away from the doped contact layer and electrode ' to reduce modal propagation losses. The optical limit for achieving such a low refractive index is limited to the optical limit achieved. (IV) In the GaN-based system, the Huanhe system is strictly limited by metallurgical constraints (in the south A1 percentage or larger thickness, strain causes misalignment or cracking ), thus resulting in a smaller refractive index contrast and less than an optical limit. Therefore; the high refractive index contrast brought about by the voids is the most popular. The second purpose of the low-refractive-index layer relies on: randomization of light through multiple reflections in the LED under geometrical optical conditions, such as diffraction effects (PhC extraction) or 150459.doc •13-201123537 The ability to efficiently extract light. In lasers, these patterns can be used to make hole mirrors, wavelength selection (such as by distributed feedback (DFB) lasers), or vertical emission (% of surface emission with second-order Bragg reflection (DBR) mirrors In-plane laser image 4 is a schematic diagram of a laser structure incorporating an embedded dielectric patterned layer that acts as a top confinement layer and ultimately possesses phc properties. The laser structure 400 includes a substrate 402, a buffer layer 4 4. A bottom metal electrode 4A6, an A1GaN optical confinement layer 408, a GaN layer 41A, a quantum well layer 412, a dielectric pattern mask 4U, and a top metal electrode 416. Optical laserization is also shown. A low refractive index layer is made of a dielectric material. Because there is no metallurgical constraint, the patterned layer 41 is as thick as required to ensure good optical confinement. (i.e., U.S. Patent Publication No. 2/6/194,359, No. 2007/0125995, and No. 7, the entire disclosure of which is incorporated herein by reference) Or dielectric optoelectronic devices However, these methods are based on the sin-patterned layer (made of dielectric or semiconductor) on the t-semiconductor epitaxial growth; therefore, the fabrication of such devices is a more complex red-making process, which includes an initial growth step, Next, one of the patterns is fabricated to form a step and then, another growth step. : A modified inlaid patterned structure manufacturing method by bonding a patterned material to an active device is proposed. Invention: The device manufactures decoupling from the patterned layer, which allows for a more flexible design of the material of the filling pattern hole, the period, shape, size and depth of the circular hole. Further, 胄The process steps of the active device and the patterned material are separated (and possibly parallel) to make the overall process more robust and less sensitive to problems in individual steps. Figure 5 is an incorporated void feature portion in accordance with the present invention. A schematic diagram of one of the laser structures in which the patterned features are produced in a portion of the material prior to bonding the material to the active semiconductor structure. The radiation structure 5〇〇 includes a substrate 5〇2, a buffer layer 5〇4, a bottom metal electrode,

An AlGaN optical confinement layer 508, a GaN layer 51, a quantum well layer 512, a bonded patterned material layer 514, and a top metal electrode 516, wherein the GaN layer can include a plurality of locations above and below the quantum well layer 512 The doped or doped layers and the quantum well layer 512 itself may comprise a stack of layers (and also for the devices described below). Optical laser wave 518 is also shown. The bonded patterned material layer 514 can be bonded to the top or bottom surface of a semiconductor structure comprising an active layer 512 and can also be incorporated into a metal layer 516 that serves as an electrode. Several configurations can be considered for the patterned layer incorporated into the active device structure. The pattern of the bonded layers can be periodic, quasi-periodic or random. A periodic lattice will form an embedded photonic crystal structure which may be useful due to its photonic bandgap properties and its diffraction properties. Quasi-periodic patterns (such as the Penrose lattice) can potentially increase the direction in which diffraction occurs. This will make the light emission of the optoelectronic device more omnidirectional. A completely random lattice can also be produced. In this case, light guided due to the light scattering of the embedded pattern randomizes the guided light' thereby increasing the light extraction efficiency of the optoelectronic device. 150459.doc 15 201123537 Figure 6 is a schematic illustration of one of the laser or LED structures incorporating embedded void features in accordance with the present invention, wherein the void pattern is within a submicron size range to extract light via a diffraction effect. The laser structure 6A includes a substrate 602, a buffer layer 604, a bottom metal electrode 606, an AlGaN optical confinement layer 608, a GaN layer 610, a quantum well layer 612, a bonded patterned material layer 614, and a top metal electrode 616. Optical laser wave 618 is also shown. The period of the pattern in layer 614 may also vary depending on the application in question. In the case of a diffraction application (electromagnetic wave diffraction method), the order of the period should be one-half wavelength of light generated by the optoelectronic device. For GaN-based LEDs, this would correspond to a period of hundreds of nanometers. 7 is a schematic illustration of one of the LED structures incorporating an embedded void structure in accordance with the present invention, wherein the void features are set to a size of microns or greater for geometrical optical effects (ie, via randomization via semiconductor initials). The structure and the light that is transmitted by the combined material) extracts light. The laser structure 700 includes a substrate 702, a buffer layer, a bottom metal electrode 〇6, an AlGaN optical confinement layer 708, a Ga_710, a quantum well layer 712' combined with a patterned material layer 714, and a top metal electrode 716. The emitted light 718 is also shown. The shape of the embedded features in the combined patterned material layer 714 is altered to illustrate other possible embodiments of the present invention. The voids or holes in the patterned layer 7U may have any shape. = For example, a polygonal, cylindrical or spherical hole is suitable for use as a diffractive object or as an embedded structure for scattering objects. In the case of light scattering applications (geometric optics), the size of the embedded voids can be very large, on the order of a few micrometers or more (which is illustrated in Figures 5 and 7). 1 150459.doc 201123537 Several configurations can be generated that include an embedded periodic structure via the incorporation of a patterned material. Figure 8 is a schematic illustration of one of the LED structures incorporated into an embedded void structure in accordance with the present invention where light is extracted via geometric optical effects and the substrate has been removed. The laser structure 800 includes a bottom metal electrode 8A2, a GaN layer 804, a lining 80 layer, a bonded patterned material layer 808 comprising a conductive transparent material, and a top metal electrode 810. The emitted light 812 is also shown. This embodiment shows that after removing the substrate to expose the underside of the active device structure, the patterned layer 808 is bonded to the top surface of the active device structure, thereby avoiding any light emission to the substrate. Figure 9 is a diagram of one of the led structures incorporating an embedded void structure in accordance with the present invention, which is not intended to extract light through geometric optical effects, wherein the substrate has been removed, and in a two step by a double deposition or bonding material A void is obtained (deposited or bonded to a first layer having one of the patterned pores, followed by deposition or bonding of a second layer on top of the first layer). The laser structure 9A includes a bottom metal electrode 902, a GaN layer 904, a quantum well layer 906, a combined patterned material layer 9〇8 comprising a conductive transparent material, and bonded or deposited on the patterned layer 908. The top metal electrode 91 is. This embodiment demonstrates that other layers can be bonded or grown on top of the patterned layer 908. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of one of the led structures incorporated into an embedded void structure in accordance with the present invention in which the substrate has been removed and subsequently thinned to a sub-micron thickness, followed by bonding of the patterned material on the top and bottom surfaces. Led structure Included - bottom metal electrode view, bonded patterned material layer 1004, GaN layer secret, quantum well layer, combined patterned material I50459.doc -17- 201123537 layer 1010 and top metal electrode 1012. Lizhan does not learn the laser wave 1014 first. This embodiment shows a thin active portion having a plurality of embedded void structures on the top and bottom surfaces thereof by the members of the patterned layer 1〇〇4, wherein the embedded void structures are used to increase the guide The mode diffracts and/or maintains the guided light away from the interface deposited by the metal (depletion) contacts 1() 2, 1012. In addition, multiple patterned layers can be combined on top of each other to form a particular configuration of the embedded void structure. For example, after removing the substrate and the thinned structure, the bonding process can be repeated twice or more on each side of the active device, resulting in a thin layer containing a void-containing void structure on both the top and bottom surfaces. Figure 11 is a schematic view of one of the LED structures in accordance with the present invention, wherein two or more patterned layers are stacked via bonding and precisely offset to form a three-dimensional (3D) ) Periodic structure (5) Photonic crystal). The LED structure hoo comprises a substrate 11〇2, a buffer layer 11〇4, a bottom metal electrode 1106, an AlGaN optical confinement layer 11〇8, a GaN layer ul〇, a quantum well layer 1112, a combined patterned material layer “” and The top metal electrode m6 also exhibits emitted light 1118. In this embodiment, the patterned layer 1114 includes a plurality of sub-layers of patterned material having a plurality of voids, each of which is relative to other sub-layers Positioning and offsetting to form a three-dimensional (3D) photonic crystal structure. Figure 12 is a schematic illustration of a led structure incorporating one of the embedded void structures in accordance with the present invention, wherein the combined patterned layer comprises a frequency converter material. 1200 includes a bottom metal electrode 丨2^, Ga]S^12〇4, an amount 150459.doc •18·201123537 subwell layer 1206, including voids (represented by squares) and light conversion elements (indicated by dots) The patterned patterned material layer 12A8 and the top metal electrode 1210 are also shown. The emitted light 1212 is also shown. The frequency of the light 1212 introduced into the patterned layer 12A8 is converted, thereby producing a combined color light, such as white light. The The embedded void enhances the extraction of both the converted light and the initial emitted light. Figure 13 is a schematic diagram of one of the led structures incorporating the concepts from Figures u and 12. The LED structure 13A includes a bottom metal electrode 13 2. The GaN layer 134, the quantum well layer i306, the patterned patterned material layer 13〇8 and the top metal electrode 13 1 0 including both the void (indicated by a rectangle) and the light converting element (indicated by dots). The emitted light 1 3 12 is displayed. Some of the light generated by the optoelectronic device can also be introduced into the patterned layer. The patterning can be controlled by varying the layer thickness or the depth of the object in the pattern (ie, the void or hole). The amount of guided light in the layer. The frequency of the guided light in the patterned layer can be varied, thereby causing the white light emitting optoelectronic device (or any other color axis) to be active in the patterned layer (4) (4) Elements (such as dyes, quantum dots, phosphors, or GahAlAsp-based materials) that convert portions of light into other frequencies (which are combined to produce initial light that is emitted by the device to produce binary, ternary, or any His color combination, including white). The guided light in the combined layer interacts with the inverter (in the same layer) with very good phase PL light and the amount of guided light (or thickness of the patterned layer) The control is provided in the control of the color mixing in the optical device (as shown in FIG. 11)... In this case, the combined patterned layer should be doubled: Better interaction of light and one of the conversion elements enhances light conversion and improves light extraction by,,, or scattering. 150459.doc 19 201123537. Optimized by using a patterned layer of conductive material Both the electrical and optical properties of the optoelectronic device are 逡K + * push μ ~ 叮 崎 透明 transparent conductor or + conductor, such as ΙΤ0 or Ζη0. For better current injection, a thin conductive layer is placed between the active device structure and the bonded patterned layer. A doped semiconductor layer can also be used as the bonded patterned layer, and an electrical contact is placed on the doped semiconductor layer. Due to the high refractive index contrast, when the holes in the patterned layer are filled with voids or voids, a higher optical diffraction is obtained. Other materials may be used to fill the holes of the patterned layer to enhance certain properties of the layer. For example, a hole in the patterned layer may be partially or completely filled with a dielectric material, a transparent conductive material, a metal material, a semiconductor material, or a variable frequency material. The patterned material can be bonded to its active region (light-emitting layer) which is flat or patterned-semiconductor. A patterned active area means that the patterned apertures reach at least the luminescent layer. The patterned aperture may extend partially or completely through the active area. Figure 14 is a schematic illustration of one of the LED structures in accordance with the present invention, wherein the patterning means produces a Phc and a flat layer is bonded over the mc. The lED structure 1400 includes a substrate 14 〇 2, a buffer layer 14 〇 4, a bottom metal electrode 1406, an AlGaN optical confinement layer 1408, a GaN layer 1410, a quantum well layer 1412, and a combined flat material layer 1 * 14. The planar layer 1414 can be any material such as a conductor, insulator, metal or semiconductor. For example, the bonded material may be a flat siC layer to be bonded to one of the patterned layers or substrates (such as GaN, ZnO or ITO) previously deposited on other materials of the device 150459.doc •20· 201123537 14丨 4. Electrical contacts in the structure can be fabricated on either side of the structure. One or more layers of any of a variety of electrically conductive materials may be placed on or under the bonded material, which may be on the top or bottom surface (or any other surface) of the device. Process Steps Figure 15 is a flow chart showing the steps of a process performed in accordance with a preferred embodiment of the present invention. Specifically, the process steps include an improved manufacturing method of one of the embedded pattern structures. Block 1500 represents the steps of fabricating an active device structure. Block 15〇2 represents the step of making at least one layer. The idea is to perform steps 15〇〇 and 1502 in parallel. Block 1504 illustrates the step of bonding the active device structure to the layer, wherein one or more embedded voids are formed at the interface (where the surface of the active device structure is bonded to the surface of the layer). In one embodiment, the surface of the layer is patterned and the surface of the active device structure is flattened. The surface of the active device structure is patterned and the surface of the layer is flat. ~ A substrate can be removed from the structure of the active device to expose the surface of the active device structure. Additionally, one or more layers of the active U. structure may be thinned after the substrate is removed and before the surface of the layer 2 is bonded to the surface of the active device structure. The voids may be filled with air, gas, conductive material or a dielectric material needle. Further, the voids may have an average refractive index lower than one of the layers. The same layer can have an average refractive index lower than that of the active device structure. 150459.doc -21 201123537 The voids may comprise polygonal, cylindrical or spherical features. In addition, the voids may include: a randomly shaped feature portion, a randomly distributed feature portion, or a periodic or quasi-periodic distribution shaped feature portion. Again, the voids can be configured in a one-dimensional pattern, a two-dimensional pattern, or a three-dimensional pattern. Further, the voids may be: continuously connected; formed by connecting holes; formed by connecting posts; or formed by both connecting holes and connecting posts. Block 1504 may also represent additional manufacturing steps. For example, one or more additional layers may be stacked or stacked on the layer bonded to the active device structure. Additionally, one or more conductive layers may be placed on one or the top surface of the active device structure. Additionally, one or more conductive layers can be placed between the layer and the active device structure. Block 1506 represents the fabrication of one of the devices using steps 1500, 1502, and 1504. In particular, the block represents an optoelectronic device having an embedded void structure that includes an active device structure bonded to at least one of the layers, wherein an interface (where one surface of the active device structure is bonded to one surface of the active layer) Forming one or more embedded voids. For example, the optoelectronic device can be a light emitting diode (LED) or a laser. REFERENCES The following references are hereby incorporated by reference: [1] T.A. Truong, L.M. Campos, E. Matioli, I. Meinel, C.J. Hawker, C.A. &quot;Weisbuch and P.M. Petroff, "Light extraction from

GaN-based light emitting diode structures with a noninvasive two-dimensional photonic crystal", "Applied Physics Letters 94, 023101, 2009". 150459.doc -22- 201123537 [2] S. Uchida et al., IEEE Journal Of Selected Topics In Quantum Electronics, Vol. 9, No. 5, September/October 2003, p. 1252. [3] U.S. Patent Publication No. 2006/0192217. [4] U.S. Patent Publication No. 2008/0087909. [5] U.S. Patent Publication No. 2, 06/0194359. [6] U.S. Patent Publication No. 20/01/0125995. Conclusion This concludes the description of the preferred embodiment of the invention. The above description of one or more embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the invention is not to be BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of an emissive mode in a thick active layer PhC LED structure; FIG. 2 is a schematic diagram of an emissive mode in an active layer PhC LED structure having an AlGaN optical confinement layer; 3 is a schematic diagram of one of the laser structures having the size values of the active layer and the AlGaN optical confinement layer; FIG. 4 is incorporated into one of the embedded dielectric patterning layers that serves as the top confinement layer and eventually possesses one of the PhC properties. Figure 1 is a schematic diagram of one of the laser structures incorporating one of the embedded void features, wherein the patterned features are bonded to the active semi-conductor 150459.doc -23· 201123537 Previously produced in a portion of the material; Figure 6 is a schematic diagram of a laser or LED structure incorporating one of the embedded void features, wherein the void pattern is in the submicron size range to extract light via the diffraction effect; A schematic diagram of an LED structure incorporating one of the embedded void structures, wherein the void features are set to a size of microns or greater to extract light via geometric optical effects; A schematic diagram of an LED structure incorporating one of the embedded void structures, wherein light is extracted via a geometric optical effect and the substrate has been removed; FIG. 9 is a schematic diagram of an LED structure incorporating one of the embedded void structures, wherein the optical effect is via /3⁄4 Knowing the light 'the substrate has been removed, and the voids are obtained in two steps by double deposition or bonding material (the first one deposited or bonded with patterned air holes); Figure 10 is incorporated into the embedded void A schematic diagram of one of the LED structures in which the substrate has been removed and then the semiconductor is thinned to a submicron thickness, and then a patterned material is bonded to the bottom surface; FIG. 11 is a schematic diagram of an LED structure incorporating one of the embedded void structures,

Stacking and accurately offsetting two or more patterned layers by combination to form a three-dimensional (3D) periodic structure; S FIG. 12 is a schematic diagram of a coffee structure incorporated into an embedded void structure, combined with patterning The layer comprises the frequency converter material; FIG. 13 is a schematic diagram incorporating one of the concepts from FIG. 9 and FIG. 12; FIG. 13 is a schematic diagram of one of the LED structures in which FIG. 14 is a patterned LED device. 24-201123537 generates a PhC and incorporates a flat layer on the PhC; and FIG. 15 is a flow chart showing one of the process steps performed in accordance with a preferred embodiment of the present invention. [Main component symbol description] 100 LED (Light Emitting Diode) structure 102 Sapphire substrate 104 GaN layer 106 Quantum well layer 108 PhC (photonic crystal) 110 Low order mode 112 Low order mode 114 High order mode 200 LED structure 202 Sapphire substrate 204 GaN layer 206 AlGaN optical confinement layer 208 quantum well layer

210 PhC 212 Low order mode 214 Low order mode 216 High order mode 300 Laser structure 302 Substrate 304 Buffer layer 150459.doc -25- 201123537 306 GaN n-type contact layer 308 Bottom metal electrode 310 AlGaN optical confinement layer 312 AlGaN optical confinement layer 314 GaN layer 316 quantum well layer 318 GaN p-type contact layer 320 top metal electrode 322 optical laser wave 400 laser structure 402 substrate 404 buffer layer 406 bottom metal electrode 408 AlGaN optical confinement layer 410 GaN layer 412 quantum well layer 414 dielectric Pattern mask 416 top metal electrode 418 optical laser wave 500 laser structure 502 substrate 504 buffer layer 506 bottom metal electrode 508 AlGaN optical confinement layer -26-150459.doc 201123537 510 GaN layer 512 quantum well layer 514 combined patterning Material layer 516 top metal electrode 518 optical laser wave 600 laser structure 602 substrate 604 buffer layer 606 bottom metal electrode 608 A1 GaN optical confinement layer 610 GaN layer 612 quantum well layer 614 combined patterned layer 616 top metal electrode 618 optical Laser wave 700 laser structure 702 substrate 704 buffer layer 706 bottom gold Dependent electrode 708 AlGaN optical confinement layer 710 GaN layer 712 quantum well layer 714 combined patterned layer 716 top metal electrode 150459.doc -27· 201123537 718 800 802 804 806 808 810 812 900 902 904 906 908 910 1000 1002 1004 1006 1008 1010 1012 1014 1100 Emitted light laser structure bottom metal electrode GaN layer quantum well layer combined patterned material layer top metal electrode emitted light laser structure bottom metal electrode GaN layer quantum well layer combined patterning Material layer top metal electrode LED structure bottom metal electrode combined patterned material layer GaN layer quantum well layer combined patterned material layer top metal electrode optical laser wave LED structure substrate 1102 201123537 1104 buffer layer 1106 bottom metal electrode 1108 AlGaN Optical confinement layer 1110 GaN layer 1112 quantum well layer 1114 bonded patterned material layer 1116 top metal electrode 1118 emitted light 1200 LED structure 1202 bottom metal electrode 1204 GaN layer 1206 quantum well layer 1208 bonded patterned material layer 1210 Top metal electrode 1212 is emitted 1300 LED structure 1302 bottom metal electrode 1304 GaN layer 1306 quantum well layer 1308 combined patterned material layer 1310 top metal electrode 1312 emitted light 1400 LED structure 1402 substrate 150459.doc -29- 201123537 1404 buffer layer 1406 bottom metal electrode 1408 AlGaN optical confinement layer 1410 GaN layer 1412 quantum well layer 1414 combined flat material layer • 30- 150459.doc

Claims (1)

201123537 VII. Patent Application Range: 1. A method of manufacturing an optoelectronic device having an embedded void structure, comprising: bonding an active device structure to at least one layer, wherein one or more embedded &amp; Wherein the active I-junction-junction is bonded to the surface of one of the layers - the interface of 2. The method of claim 1, wherein the surface of the layer is patterned and the surface of the active device structure The surface is flat, or wherein the surface of the active device structure is patterned and the surface of the layer is flat. 3. The method of claim 1, wherein the layer comprises an electrical conductor, a transparent conductor, a semiconductor or a metal. 4. The method of claimants' further comprising stacking or stacking a plurality of additional layers bonded to the layer of the «Hi active device structure. The method of claim 1 wherein the substrate is removed from the active device structure to expose the surface of the active device structure. 6. The method of claim 5, wherein the one or more layers are thinned after the substrate is removed and before the surface of the active device structure is bonded to the surface of the active device structure. 7. The method of claim 1, wherein the voids are filled with air, a body, a piece of material, a conductive material or a dielectric material. 8. The method of claim 7, wherein the voids have an average refractive index that is lower than one of the layers. &lt; X. 9. The method of claim 1 wherein the layer has an average refractive index lower than the structure of the active device. 150459.doc 201123537 10. The method of claimants, wherein the voids enclose a polygonal, cylindrical or spherical feature portion. 11. The method of claim 1, wherein the voids comprise: a characteristic portion of the random shape, a characteristic portion of the random distribution, or a characteristic portion of the periodic or quasi-periodic distribution shaping. 12. The method of claim 1, wherein the voids are configured in a one-prong pattern, a quasi-pattern or a two-dimensional pattern. 13. The method of claimant, wherein the voids are: formed by a continuous connection, formed by a connecting hole, formed by a connecting post, or formed by both the connecting hole and the connecting post. 14. The method of claim 1, wherein one or more of the conductive layers are placed on a bottom or top surface of the active device structure. 15. The method of claim 1, wherein one or more conductive layers are placed between the layer and the active device structure. 16. The method of claim </ RTI> wherein the optoelectronic device is a light emitting diode (LED) or a laser. 17. Apparatus for manufacturing using the method of claim 1. 18. An optoelectronic device having an embedded void structure, comprising: an active device structure coupled to at least one layer, wherein one or more embedded voids are formed therein - a surface system of the active device structure is bonded thereto One of the surfaces of one of the layers is at the interface. 19. The device of claim 18, wherein the surface of the layer is patterned and the surface of the active device structure is flat, or wherein the surface of the active device structure is patterned And the surface of the layer is flat. 20. The device of claim 18, wherein the layer comprises an electrical conductor, a transparent conductor 'semiconductor or metal. 21. The device of claim 18, further comprising a plurality of additional layers stacked or stacked on the layer bonded to the active device structure. 22. The device of claim 18, wherein the substrate is removed from the active device structure to expose the surface of the active device structure. 23. The device of claim 22, wherein one or more layers of the active device structure are thinned after the substrate is removed and before the surface of the layer is bonded to the surface of the active device structure. One unit of air. 24. The apparatus of claim 18, wherein the gap of the towel is filled with an air body, a conductive material or a dielectric (four). The device of claim 18, wherein the voids have a refractive index lower than the average of the layers. 26. The device as claimed, the average refractive index. The layer of hail has a lower than the structure of the active device. The layer includes a polygon, a cylinder 27. The device of claim 18, or a spherical feature portion. 28. The voids of claim 18, wherein the four voids comprise: a characteristic portion of a random shape, a randomly distributed feature portion, or a characteristic portion of a periodic or quasi-periodic distribution shape. The apparatus of claim 18, wherein the apparatus is configured in a one-dimensional two-dimensional pattern or a three-dimensional pattern. The pattern of claim 18, wherein the gaps are formed by continuous connection, formed by connecting holes, formed by connecting posts, or formed by both connecting holes and connecting posts. 31. The device of claim 18, wherein one or a conductive layer is placed on a bottom or top surface of the active device structure. 32. The device of claim 18, wherein one or more conductive layers are disposed between the layer and the active device structure. 33. The device of claim 18, wherein the optoelectronic device is a light emitting diode (LED) or a laser. 150459.doc