201113959 六、發明說明： 【發明所屬之技術領域] 本發明係有關一種封裝結構之製法，尤指一種能提高 整體產•與降低整體成本之封裝結構之製法。 【先前技術】 為滿足半導體封裝件高積集度（Integration)以及微型 化(Miniaturization)的封裝需求，並提供給多數主被動元件 及線路連接用之封襞基板，已經逐漸由單層板演變成多層 板’以在有限的空間下，藉由層間連接技術（lnterjayer connection)來擴大電路板上可利用的佈線面積，且能配合 南電子在、度之積體電路(Integrated circuit)需求。 習知之多層電路板係於一核心板及對稱形成於其兩 側之線路增層結構所組成，但因使用核心板將導致導線長 度及整體結構厚度增加，而難以滿足電子產品功能不斷提 升且體積卻不小的需求’遂發展出無核心層 結構之電路板’以符合縮短導線長度及降低整體結構厚 度、及因應高頻化、微小化的趨勢要求。 而在現行覆晶式（flip chip)半導體封裝技術中，係 將半導體晶片之作用面接置在一封裝基板上，而該半導體 S曰片之作用面上設有複數電極墊，於該封裝基板之頂面具 有複數包性接觸墊，且藉由焊料凸塊以對應電性連接該些 电極墊與電性接觸墊’令該半導體晶片電性連接至該封裝 基板。 相車乂於傳統的打線接合（wire bond )技術，覆晶技術 1Π375 4 201113959 之特徵在於半導體晶片與封裝基板間的電性連接係直接以 焊料凸塊為之而非一般之金線，而此種覆晶技術之優點在 於能提高封裝密度以降低封裝元件尺寸；同時，該種覆晶 技術不需使用長度較長之金線，因而能降低阻抗，以提高 電性功能。 習知之覆晶式封裝結構之製法係先提供一已完成前 段製程且具有多層線路連接結構之整版面基板本體，於該 整版面基板本體之最外層線路具有複數凸塊焊墊，並於該 • 基板本體上形成絕緣保護層，且於該絕緣保護層中形成複 數開孔，以令各該凸塊焊墊對應外露於各該開孔，並於該 開孔中之凸塊焊墊上形成表面處理層，而成為一整版面封 裝基板（panel);接著，將該整版面封裝基板切割成複數 封裝基板單元（unit)或複數封裝基板條（strip)，而各該 封裝基板條具有複數封裝基板單元；最後，再運送至封裝 廠進行後續的置晶、封裝、及/或切單（singulation)等步 • 驟。 惟，若將該整版面封裝基板切割成複數封裝基板單元 後，再進行置晶與封裝步驟，則一次僅有單一封裝基板單 元進行製程處理，因而產能較低且整體成本高；又若將該 整版面封裝基板切割成複數封裝基板條後，再進行置晶、 封裝與切單等製程，則因該封裝基板條必須保留邊框以供 製程進行之夾持使用，因而佔用不少有效面積，而造成材 料成本的浪費。 另一方面，隨著封裝基板的整體厚度愈來愈薄，對於 5 111375 201113959 封裝基板單元或封裝基板條進行置晶或封裝等加工步驟將 更加困難。 然而，若不先將整版面封裝基板切割成複數封裝基板 單元或複數封裝基板條，而直接以整版面封裝基板來進行 置晶、封裝、及切單等步驟，則必須購置較大之製程機台， 因而造成整體設備成本的上升；再者，整版面封裝基板的 大面積對位的精度較低，容易使得最終的封裝結構單元有 較大的製程誤差，進而影響整體良率。 因此，如何避免習知技術中之封裝結構之製法具有較 繁雜之步驟而導致產能低落、及浪費過多基板的有效面積 而導致整體成本上升等問題，實已成為目前亟欲解決的課 題。 【發明内容】 鑑於上述習知技術之種種缺失，本發明之主要目的係 提供一種能提高整體產能與降低整體成本之封裝結構之製 法。 為達上述及其他目的，本發明揭露一種封裝結構之製 法，係包括：提供兩個均具有相對兩表面之承載板單元， 於各該承載單元之一表面上具有金屬層，於該兩承載單元 未具有金屬層之表面之間以第二黏著層結合；於各該金屬 層上依序形成複數電性接觸墊與增層結構，該增層結構係 包括至少一介電層、形成於該介電層上之線路層、及複數 形成於該介電層中並電性連接該線路層與電性接觸墊之導 電盲孔，且該增層結構最外層之線路層復具有複數凸塊焊 6 川375 201113959 墊；於該增層結構最外層上形成絕緣保護層，且該絕緣保 護層中形成複數開孔，以令各該凸塊輝塾對應外露於各节 開孔，於各該凸塊輝塾上電錢形成金屬凸塊，而成為 成對的整版面封裝基板；移除該第二黏著層以將該上 對的整版面封裝基板分離成兩個獨立的整版面封裝其板· 第-次裁切該整版面封裝基板的邊緣與内部進行為 複數封裝基板區塊，又各該封裝基板區塊具有呈（mxnf 陣列排列的封裝基板單元，其中，皆為大於】之二 數’於各该封裝基板單元之該些金屬凸塊上接置具有作用 面之+導體晶片，以成為具有複數封裝結構單元的封裝处 構區塊，於該作用面上具有複數電極塾，而 ㈣。 由焊料凸塊以對應電性連接至各該凸塊 ^極塾稭 護層及該歧半導體晶片上彡& ，…/钇緣保 該些半输材並填入 巴啄诉0隻層之間，以包覆該些焊斜Λ 塊；將該金屬層自該承載單元分離；移除該金屬層.以及 第二次裁切該封裝結構區塊以分離成複數封農結才i單元。 包括於=封裝結構之製法中，該承載單元之製程係可 耠供一具有兩表面之承載板；於該承载板之一 ^形成黏著層；於該㈣層上全面貼設有面積小於絲 層環繞之剝離層;以及於該_層_ β曰^成至屬層。或者，該承載單元之製程係可包括： 具有兩表面之承載板；於該承載板之一表面上形成 積小於該承載板之剝離層；於設有該剝離層之表面上 未形成該剝離層之表面上形成黏著層，以令該㈣層環^ Π1375 7 201113959 該剝離層四周；以及於該剝離層與黏著層上形成金屬層。 於前述之封裝結構之製法中，該第一次裁切之裁切邊 可通過該剝離層。 依上所述之封裝結構之製法’復可包括於各該金屬凸 塊上形成第一表面處理層，而形成該第一表面處理層之材 料可為鎳/金（Ni/Au)、化錄I巴浸金（Electroless Nickel / Electr〇less paiiadium / immersion Gold，ENEPIG)、錫 (Sn)、銀（Ag)、或金（An)。 又於上述之製法中，於該第二次裁切前，復可包括於 各該電性接觸墊上形成焊球。 由上可知’本發明之封裝結構之製法係先將上下成對 的整版面封裝基板裁切成複數上下成對的封裝基板區塊， 而各。亥上下成對的封裝基板區塊之面積適中且具有有複數 上下成對的封裝基板單元；接著，於各該封裝基板單元上 接置半導體晶片並以封裝材加以固定與保護；最後，裁切 成複數封裝結構單元。相較於習知技術，本發明之封裝結 構之製法係整合封裝基板製造及半導體晶片封裝，可—次 對各該封裝基板區塊中的全部封裝基板單元進行半導體晶 片ί裝’以間化步驟並提高產能；此外，本發明之製法過 程中巧妙運用承載板’故可用於超薄基板的封裝製程；再 者’本發明中之封裝基板區塊的面積適中，所以，各該封 裝基板區塊中的各該封裝基板單元除了能擁有較高的製程 精度與良率之外’同時也能節省佈線成本及作業時間、並 提南產能。 111375 201113959 【實施方式】 以下藉的具體實施例說 式，熟悉此技藝之人士可 X月之戶 '她方 瞭解本發明之其他優點及功所揭示之内容輕易地 的剖=:中至：,=之封裝結構之製法 竽第IDu/ A圖的另一態樣， 。亥弟1D圖係苐】D圖的俯視圖。 之承第一1八9及1A，圖所示，提供兩個均具有相對兩表面 該承載單元2之—表面上具有金屬層 载人單元2未具有金屬層22之表面之間以第二 黏著層212結合。 一上述之承載單元2之製程可如第1A圖所示，係提供 具：兩表面之承載板20;於該承載板2〇之一表面上形 成黏著層212;接著，於該黏著層212上全面貼設有面積 小於該承載板20且四周為該黏著層212環繞之剝離層 • 211;之後於該剝離層211與黏著層212上形成金屬層u。 /或者’上述之承載單元2之製程可如第1A，圖所示， 係提供一具有兩表面之承載板2〇 ;於該承載板2〇之一表 面上形成面積小於該承載板2〇之剝離層211 ;接著，於設 有該剝離層211之表面上且未形成該剝離層211之表面上 形成黏著層212，以令該黏著層212環繞該剝離層四 周；以及於該剝離層211與黏著層212上形成金屬層22。 所述之剝離層211可為離型膜，而該金屬層22之材 質可為銅’且該金屬層22可作為電鍍製程中電流傳導路徑 Π1375 9 201113959 之晶種層（seed layer)。以下内容係以第ία圖作說明。201113959 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of manufacturing a package structure, and more particularly to a method for manufacturing a package structure capable of improving overall production and reducing overall cost. [Prior Art] In order to meet the packaging requirements of semiconductor package high integration and miniaturization, and to provide a package substrate for most active and passive components and circuit connections, it has gradually evolved from a single layer board to a single layer board. The multi-layer board expands the available wiring area on the board by lnterjayer connection in a limited space, and can meet the requirements of the integrated circuit of the South Electronics. The conventional multilayer circuit board is composed of a core board and a line build-up structure symmetrically formed on both sides thereof, but the use of the core board will result in an increase in the length of the wire and the thickness of the overall structure, and it is difficult to meet the ever-increasing function and volume of the electronic product. However, there is no small demand for 'developing a circuit board without a core layer structure' to meet the trend of shortening the length of the wire and reducing the thickness of the overall structure, and in response to the trend of high frequency and miniaturization. In the current flip chip semiconductor package technology, the active surface of the semiconductor wafer is mounted on a package substrate, and a plurality of electrode pads are disposed on the active surface of the semiconductor S-chip. The top surface has a plurality of inclusive contact pads, and the semiconductor pads are electrically connected to the package substrate by electrically connecting the electrode pads and the electrical contact pads by solder bumps. In the traditional wire bonding technology, flip chip technology 1 Π 375 4 201113959 is characterized in that the electrical connection between the semiconductor wafer and the package substrate is directly solder bumps instead of the general gold wire, and this The advantage of the flip chip technology is that it can increase the package density to reduce the package component size. At the same time, the flip chip technology does not require the use of a long length of gold wire, thereby reducing the impedance and improving the electrical function. The conventional method for manufacturing a flip-chip package structure is to provide a full-face substrate body having a multi-layer line connection structure, and a plurality of bump pads on the outermost layer of the body of the full-page substrate, and An insulating protective layer is formed on the substrate body, and a plurality of openings are formed in the insulating protective layer, so that each of the bump pads is exposed to each of the openings, and a surface treatment is formed on the bump pads in the opening. The layer is formed into a full-page package substrate; then, the full-face package substrate is cut into a plurality of package substrate units or a plurality of package substrate strips, and each of the package substrate strips has a plurality of package substrate units Finally, it is transported to the packaging factory for subsequent crystallization, encapsulation, and/or singulation steps. However, if the entire package substrate is diced into a plurality of package substrate units, and then the crystallization and packaging steps are performed, only a single package substrate unit is processed at a time, so that the productivity is low and the overall cost is high; After the whole-version package substrate is cut into a plurality of package substrate strips, and then the processes of crystallization, encapsulation, and singulation are performed, the package substrate strip must retain the frame for the process to be clamped, thereby occupying a large effective area. A waste of material costs. On the other hand, as the overall thickness of the package substrate becomes thinner, it is more difficult to perform the processing steps such as lithography or packaging on the 5 111375 201113959 package substrate unit or package substrate strip. However, if the entire package substrate is not first cut into a plurality of package substrate units or a plurality of package substrate strips, and the substrate is directly packaged by a full-face substrate for crystallization, packaging, and singulation, a larger process must be purchased. The overall cost of the device is increased. Moreover, the accuracy of the large-area alignment of the full-page package substrate is low, which tends to cause a large process error in the final package structure unit, thereby affecting the overall yield. Therefore, how to avoid the problem that the manufacturing method of the package structure in the prior art has complicated steps, resulting in low productivity, waste of excessive effective area of the substrate, and overall cost increase has become a problem that is currently being solved. SUMMARY OF THE INVENTION In view of the above-described deficiencies of the prior art, it is a primary object of the present invention to provide a package structure that increases overall throughput and reduces overall cost. In order to achieve the above and other objects, the present invention discloses a method for manufacturing a package structure, comprising: providing two carrier plate units each having opposite surfaces, and having a metal layer on one surface of each of the carrier units, the two bearing units a surface of the metal layer is bonded to the second adhesive layer; a plurality of electrical contact pads and a build-up structure are sequentially formed on each of the metal layers, the build-up structure comprising at least one dielectric layer formed on the dielectric layer a circuit layer on the electrical layer, and a plurality of conductive blind holes formed in the dielectric layer and electrically connected to the circuit layer and the electrical contact pads, and the circuit layer of the outermost layer of the buildup structure has a plurality of bump bumps 6川 375 201113959 mat; forming an insulating protective layer on the outermost layer of the build-up structure, and forming a plurality of openings in the insulating protective layer, so that the bumps of the bumps are correspondingly exposed to the opening of each section, and the bumps are respectively塾 塾 塾 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾-Secondary The edge and the inner surface of the full-width package substrate are a plurality of package substrate blocks, and each of the package substrate blocks has a package substrate unit (mxnf array arrangement, wherein both are greater than) The metal bumps of the unit are connected to the + conductor wafer having the active surface to form a package structure block having a plurality of package structure units, and the plurality of electrodes 塾 on the active surface, and (4). Correspondingly electrically connected to each of the bumps and the protective layer of the bump and the semiconductor wafer, and the half of the material is filled and filled between the layers of the layer to cover The soldering slanting block; separating the metal layer from the carrying unit; removing the metal layer; and cutting the package structure block a second time to separate into a plurality of sealed cells. In the manufacturing method, the processing unit of the carrying unit can provide a supporting plate having two surfaces; forming an adhesive layer on one of the supporting plates; and uniformly disposing a peeling layer having a smaller area than the silk layer on the (four) layer; And in the _ layer _ β 曰 ^ into Or the process of the carrying unit may include: a carrier plate having two surfaces; forming a peeling layer smaller than the carrier plate on a surface of the carrier plate; the surface is not formed on the surface provided with the peeling layer An adhesive layer is formed on the surface of the peeling layer to make the (four) layer ring 四周1375 7 201113959 around the peeling layer; and a metal layer is formed on the peeling layer and the adhesive layer. In the foregoing method for manufacturing the package structure, the first time The cutting edge can be passed through the peeling layer. According to the manufacturing method of the package structure, the first surface treatment layer is formed on each of the metal bumps, and the material forming the first surface treatment layer can be It is nickel/gold (Ni/Au), Electroless Nickel / Electr〇less paiiadium / immersion Gold (ENEPIG), tin (Sn), silver (Ag), or gold (An). In the above method, before the second cutting, the solder ball is formed on each of the electrical contact pads. It can be seen from the above that the manufacturing method of the package structure of the present invention first cuts the upper and lower pairs of the entire surface package substrate into a plurality of package substrate blocks in pairs, and each. The upper and lower pairs of package substrate blocks have a moderate area and have a plurality of upper and lower pairs of package substrate units; then, the semiconductor wafers are attached to the package substrate units and fixed and protected by the package materials; and finally, the cutting is performed. A plurality of package structural units. Compared with the prior art, the manufacturing method of the package structure of the present invention integrates the manufacturing of the package substrate and the semiconductor chip package, and can perform the semiconductor wafer mounting process on all the package substrate units in each of the package substrate blocks. Moreover, the production capacity is improved by using the carrier board in the manufacturing process of the present invention, so that the package process of the package substrate is moderate, and therefore, each package substrate block is In addition to the high process accuracy and yield, each of the package substrate units can also save wiring costs and operating time, and increase production capacity. 111375 201113959 [Embodiment] The following specific embodiments are used, and those skilled in the art can understand the other advantages of the present invention and the contents disclosed by the user. = The method of manufacturing the package structure 另一 The other aspect of the IDu/A diagram, . Haidi 1D map system 苐] top view of the D map. According to the first 1 8 9 and 1A, as shown in the figure, two bearing units 2 are provided with opposite surfaces - a surface having a metal layer on the surface of the manned unit 2 having no metal layer 22 with a second adhesion Layer 212 is combined. The process of the above-mentioned carrying unit 2 can be as shown in FIG. 1A, with a carrier plate 20 having two surfaces; an adhesive layer 212 is formed on one surface of the carrier plate 2; and then, on the adhesive layer 212 A peeling layer 211 having a smaller area than the carrier 20 and surrounded by the adhesive layer 212 is integrally attached; then a metal layer u is formed on the peeling layer 211 and the adhesive layer 212. The process of the above-mentioned carrying unit 2 can be as shown in FIG. 1A, which is to provide a carrier board 2 having two surfaces; the area formed on one surface of the carrier board 2 is smaller than that of the carrier board 2 a peeling layer 211; then, an adhesive layer 212 is formed on the surface of the surface on which the peeling layer 211 is provided and the peeling layer 211 is not formed, so that the adhesive layer 212 surrounds the peeling layer; and the peeling layer 211 and A metal layer 22 is formed on the adhesive layer 212. The peeling layer 211 may be a release film, and the material of the metal layer 22 may be copper' and the metal layer 22 may serve as a seed layer of the current conduction path Π1375 9 201113959 in the electroplating process. The following is illustrated by the ία diagram.
如第1Β圖所示，於各該金屬層22上依序形成複數電 性接觸墊23與增層結構24 ’該增層結構24係包括至 少一介電層24卜形成於該介電層241上之線路層243、 及複數形成於該介電層241中並電性連接該線路層；243 與電性接觸墊23之導電盲孔242 ;其中，形成該介電 層 241 之材料可為 ABF (Ajinomoto Build-up Film)、BCB (Benzocyclo-buthene) > LCP (Liquid Crystal Polymer) > pj (Poly-imide) 、PPE (Poly(phenylene ether)) 、PTFE (Poly(tetra-fluoroethylene))、FR4、FR5、BT (BismaleimideAs shown in FIG. 1 , a plurality of electrical contact pads 23 and a build-up structure 24 ′ are sequentially formed on each of the metal layers 22 . The build-up structure 24 includes at least one dielectric layer 24 formed on the dielectric layer 241 . The upper circuit layer 243 and the plurality of conductive layers 243 are electrically connected to the circuit layer 243 and the conductive contact holes 242 of the electrical contact pads 23; wherein the material forming the dielectric layer 241 can be ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene) > LCP (Liquid Crystal Polymer) > pj (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide
Triazine)、芳香尼龍(Aramide)、或混合環氧樹脂玻璃纖維 (Glass fiber)所構成’且該增層結構24最外層之線路層 243復具有複數凸塊垾墊244 ;接著，於該增層結構24最 外層上形成絕緣保護層25，且該絕緣保護層25中形成複 數開孔250 ’以令各該凸塊焊墊244對應外露於各該開孔 250，於各該凸塊焊墊244上電鍍形成金屬凸塊20，而成 為上下成對的整版面封裝基板2a ;然後，於各該金屬凸塊 26上形成第一表面處理層27，該第一表面處理層27之材 料可為鎳/金（Ni/Au)、化鎳鈀浸金（Electro】ess Nickel/Triazine), aromatic polyamide (Aramide), or mixed epoxy fiberglass (Glass fiber) and the outermost layer of the layered structure 24 is provided with a plurality of bump pads 244; An insulating protective layer 25 is formed on the outermost layer of the structure 24, and a plurality of openings 250' are formed in the insulating protective layer 25 so that the bump pads 244 are correspondingly exposed to the openings 250, and the bump pads 244 are respectively formed on the bump pads 244. The metal bumps 20 are formed by electroplating to form a pair of upper surface package substrates 2a; then, a first surface treatment layer 27 is formed on each of the metal bumps 26, and the material of the first surface treatment layer 27 may be nickel. /Gold (Ni/Au), nickel-palladium immersion gold (Electro) ess Nickel/
Electroless Palladium / Immersion Gold，ENEPIG)、錫 (Sn)、銀（Ag)、或金（Au)。 如第1C圖所示，移除該第二黏著層212,以將該上下 成對的整版面封裝基板2a分離成兩個獨立的整版面封裝 基板2a’。 10 111375 201113959 如第ID及ID’圖所示，該第1D，圖係第id圖的俯視 圖；如圖所示，沿該整版面封裝基板2a，的邊緣與内部進 行第一次裁切，且裁切邊28通過該剝離層211，以成為複 數封裝基板區塊2b，且各該封裝基板區塊2b具有呈 η )陣列排列的封裝基板單元2c ;其中，m與n皆為大於】 之整數，於本實施例中，m與η分別為6與5，但不以此 為限。此外，於該第-次裁切前，復可包括於該絕緣保禮 •層25與金屬凸塊26 (或其上的第一表面處理層27)上： 成第-保護膜（圖式中未表示），以避免該絕緣保護声 ^凸塊26(或其上的第-表面處理層27)於裁切時被 ^或㈣㈣響’並於該第—次裁切後’移除該第一保 如第圖所示’於各該封裳基板單元 作用面29a之半導體晶片29， 接置具有 …封裝結構區塊2,，，於該=面:複數封裝料^ 極塾別㈣該辦291藉具有複數電 連接至各該凸塊烊墊2化接著，於如以對應電性 些半導體晶㈣上形成封裝材31:^^層25及該 該些半導體晶片29與絕緣保護層 :Μ材31並填入 料凸塊30。 以包覆該些焊 如第】F圖所示，將該金屬層& 如第】G圖所示，移除該金屬肩…裁早兀2分離。 接觸塾23’並於各該電性接觸墊J 一卜'"乂露出該些電性 表面處理層（圖式中未 屯成焊球32或第二 %成镇第二表面處理層 J, Γ C 1 - ·· ·* }Π375 201113959 之材料可為錄/金（Ni/Au ) '化鎳飽浸金（Electroless Nickel / Electroless Palladium / Immersion Gold 5 ENEPIG)、錫 (Sn) 、I艮（Ag)、或金（Au)。 如第1H圖所示，進行第二次裁切以將該封裝結構區 塊2b’分離成複數封裝結構單元2c’。此外，於該第二次裁 切前，復可包括於該些電性接觸墊23 (或其上的焊球32 或第二表面處理層）與介電層241上形成第二保護膜（圖 式中未表示），以避免該介電層241與電性接觸墊23 (或 其上的焊球32或第二表面處理層）於裁切時被液體或粉塵 所影響，並於該第二次裁切後，移除該第二保護膜。 综上所述，本發明之封裝結構之製法係先將上下成對 的封裝基板整版裁切成複數上下成對的封裝基板區塊，而 各該上下成對的封裝基板區塊之面積適中且具有有複數上 下成對的封裝基板單元；接著，於各該封裝基板單元上接 置半導體晶片並以封裝材加以固定與保護；最後，裁切成 複數封裝結構單元。相較於習知技術，本發明之封裝結構 之製法係整合封裝基板製造及半導體晶片封裝，可一次對 各該封裝基板區塊中的全部封裝基板單元進行半導體晶片 封裝，以簡化步驟並提高產能；此外，本發明之製法過程 中巧妙運用承載板，故可用於超薄基板的封裝製程；再者， 本發明中之封裝基板區塊的面積適中，所以，各該封裝基 板區塊中的各該封裝基板單元除了能擁有較高的製作精度 與良率之外，同時也能節省佈線成本及作業時間、並提高 產能。 12 1Π375 201113959 上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下，對上述實施例進行修 改因此本發明之權利保護範圍，應如後述之申請專 圍所列。 11 【圖式簡單説明】 第ία至1H圖係本發明封&结構之製法的剖視示意Electroless Palladium / Immersion Gold, ENEPIG), tin (Sn), silver (Ag), or gold (Au). As shown in Fig. 1C, the second adhesive layer 212 is removed to separate the upper and lower paired full-size package substrates 2a into two separate full-size encapsulation substrates 2a'. 10 111375 201113959 As shown in the ID and ID' diagrams, the first 1D is a plan view of the id diagram; as shown in the figure, the edge and the inside of the package substrate 2a are first cut along the entire surface, and The cutting edge 28 passes through the peeling layer 211 to form a plurality of package substrate blocks 2b, and each of the package substrate blocks 2b has an array substrate unit 2c arranged in an array of η); wherein m and n are both integers greater than In the present embodiment, m and η are 6 and 5, respectively, but are not limited thereto. In addition, before the first cutting, a composite may be included on the insulating layer 25 and the metal bump 26 (or the first surface treatment layer 27 thereon): into a first protective film (in the drawing) Not shown) to avoid the insulation protection sound bump 26 (or the first surface treatment layer 27 thereon) being smashed by ^ or (4) (four) at the time of cutting and removing the first after the first cutting As shown in the figure, the semiconductor wafer 29 on each of the sealing substrate unit active surfaces 29a is connected to the package structure block 2, and the surface is covered by the plurality of package materials. 291 has a plurality of electrical connections to each of the bump pads 2, followed by forming a package 31 on the corresponding semiconductor crystals (4) and the semiconductor wafer 29 and the insulating protective layer: The material 31 is filled with the material bumps 30. To cover the solders, as shown in Fig. F, the metal layer & as shown in Fig. G, remove the metal shoulders. Contacting the crucible 23' and exposing the electrical surface treatment layer to each of the electrical contact pads J (the solder ball 32 or the second % of the second surface treatment layer J is not formed in the drawing, Γ C 1 - ·· ·* }Π375 201113959 The material can be recorded as gold/nickel (Ni/Au) 'Electroless Nickel / Electroless Palladium / Immersion Gold 5 ENEPIG, tin (Sn), I艮 ( Ag), or gold (Au). As shown in Fig. 1H, a second cut is performed to separate the package structure block 2b' into a plurality of package structure units 2c'. In addition, before the second cut The second protective film (not shown) is formed on the electrical contact pads 23 (or the solder balls 32 or the second surface treatment layer thereon) and the dielectric layer 241 to avoid the The electrical layer 241 and the electrical contact pad 23 (or the solder ball 32 or the second surface treatment layer thereon) are affected by liquid or dust during cutting, and after the second cutting, the second is removed In view of the above, the method for manufacturing the package structure of the present invention is to first cut the upper and lower pairs of package substrates into a plurality of package substrates. a block, wherein each of the upper and lower pairs of package substrate blocks has a moderate area and has a plurality of package substrate units; and then the semiconductor wafer is attached to each of the package substrate units and fixed and protected by the package material. Finally, cutting into a plurality of package structure units. Compared with the prior art, the package structure of the present invention is integrated with the package substrate manufacturing and the semiconductor chip package, and all the package substrate units in the package substrate block can be used at one time. Semiconductor chip packaging is performed to simplify the steps and increase the productivity; in addition, the carrier board is skillfully used in the manufacturing process of the present invention, so that it can be used for the packaging process of the ultra-thin substrate; further, the area of the package substrate in the present invention is moderate. Therefore, each of the package substrate units in each of the package substrate blocks can have high manufacturing precision and yield, and can also save wiring cost and operation time, and increase productivity. 12 1Π375 201113959 The above embodiment is To exemplify the principles of the invention and its effects, and not to limit the invention. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the following application. 11 [Simple description of the figure] FIG. 1H is a cross-sectional view showing the method of manufacturing the seal & structure of the present invention
^^中’該第1A’圖係冑1A_另一態樣，該第取 圖h第1D圖的俯視圖。 【主要元件符號說明】 2 承載单元 2a 2a’ 2b 2b， 2c 2c’ 20 211 上下成對的整版面封裝基板 整版面封裝基板 封裝基板區塊 封裝結構區塊 封裝基板單元 封裝結構單元 承載板 剝離層 212 第一黏著層 2lT 第二黏著層 22 金屬層 電性接觸墊 增層結構 1)1375 ]3 201113959 241 介電層 242 導電盲孔 243 線路層 244 凸塊焊墊 25 絕緣保護層 250 開孔 26 金屬凸塊 27 第一表面處理層 28 裁切邊 29 半導體晶片 29a 作用面 291 電極墊 30 焊料凸塊 31 封裝材 32 焊球 m 封裝基板區塊之陣列行數 n 封裝基板區塊之陣列列數^^中' The 1A' diagram is a top view of the 1D diagram of Fig. 1D. [Main component symbol description] 2 Carrying unit 2a 2a' 2b 2b, 2c 2c' 20 211 Upper and lower paired full-face package substrate Full-page package substrate Package substrate block package structure Block package substrate unit package structure unit carrier board release layer 212 first adhesive layer 2lT second adhesive layer 22 metal layer electrical contact pad build-up structure 1) 1375] 3 201113959 241 dielectric layer 242 conductive blind hole 243 circuit layer 244 bump solder pad 25 insulating protective layer 250 opening 26 Metal bump 27 First surface treatment layer 28 Cutting edge 29 Semiconductor wafer 29a Interaction surface 291 Electrode pad 30 Solder bump 31 Package material 32 Solder ball m Number of array rows of package substrate block n Number of array columns of package substrate block
)A 川375)A Chuan 375