201032588 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種影像感測系統，特別是一種影像感測裝置 及影像感測方法。 【先前技術】 在資訊發達的現代社會中，影像傳遞已成為人們傳遞訊息的 重要方式之一。隨著科技的進步，影像感測系統已廣泛地應用到 Φ 許多領域上，例如：醫療'太空、軍事、及民生等各種領域。 於影像感測系統中，主要是利用影像感測器來擷取影像。影 像感測系統的基本原理是將影像投射到影像感測器的影像陣列 (imagearray)上’然後透過影像陣列進行影像的擷取，再透過電 子電路的訊號處理來獲得相應於影像的數位影像資料，而後再把 得到的數位影像訊號儲存在儲存媒體中。 目前市面上常見的影像感測器主要可分為電荷耦合元件 _ (charge coupled device ; CCD)和互補式金氧半影像感測器 (complementary metal-oxide-semiconductor image sensor ； CMOS image sensor)兩種。 其中，相較於CCD，CMOS影像感測器具有低電壓與低功率 操作、低製造成本、易於縮小化、高讀出速率、及可實現系統晶 片（system-on-a-chip ; SOC)(即高整合性）等優點。因此，隨 著CMOS製程技術的進步，CM0S影像感測器越來越受到重視， 且更具有其發展的潛力。 一般來說，在影像感測系統中，影像感測器係耦合於影像處 201032588 理單元’以利接收和處理擷取得的影像資料。雖然於影像資料取 得之後’已會進行影像㈣巾雜訊_核理，但若能於擷取影 像的過程巾’減少魏源的存在來避錄_赴 地取得相應於影像嶋資料。 【發明内容】 、以上的問題，本發明提供—種影像感測裝置及影像感測 方法，藉以解決先前技術之於擷取影像的過程中，雜訊源所產生 ❹的雜訊景> 響_取得的影像資料的品質的問題。 本發明所揭露之影佩職置，包括：時序產生器、影像揭 取電路、至少-第—邏輯電路、至少—第二賴電路和情電路。 第:邏輯電路電性連接於影像擷取電路和時序產生器之間。 第-邏輯電路電性連接至影像練電路。並且，情電路電性連 接於時序產生器和第二邏輯電路之間。 於此^序產生器接收-系統時脈，並且依據系統時脈輸出 時脈訊號。第一邏輯電路接收時脈訊號，並且依據時脈訊號控 制影賴取電路的運作。於此，影像感測過程可大致上分為感測 期間和讀取期間。影像擷取電路在感測期間感測一娜信號，並 且，讀取期間讀取擷取信號並產生影像訊號。中斷電路在感測期 門提供時觀敍第二邏輯電路，並且在讀取躺停止提供時脈 訊號至至少一第二邏輯電路。 士本發明所揭露之影像感測方法，包括：藉由第一邏輯電路依 據時脈訊號產生控制訊號；輸4脈訊號至第二邏輯電路；利用 控制訊號控制影像資料的讀出；以及於影像資料的讀出期間，中 201032588 斷輸入至第二邏輯電路的時脈訊號。 综上所述，根據本發明之影像感測裳置及影像感測方法，應 用於影像制祕，可於執行影像:#_取顧，中斷電路 中斷輸入至第二邏輯電路㈣統時脈，藉以減少邏輯電路運作時 產生的電流所造成的電源雜訊。 ’ 以下之實施方式之說明係甩 並且提供本發明之專利申請201032588 VI. Description of the Invention: [Technical Field] The present invention relates to an image sensing system, and more particularly to an image sensing device and an image sensing method. [Prior Art] In the modern society where information is developed, image transmission has become one of the important ways for people to transmit information. With the advancement of technology, image sensing systems have been widely used in many fields, such as medical 'space, military, and people's livelihoods. In the image sensing system, the image sensor is mainly used to capture images. The basic principle of the image sensing system is to project the image onto the image sensor image array (imagearray), and then capture the image through the image array, and then through the signal processing of the electronic circuit to obtain the digital image data corresponding to the image. Then, the obtained digital image signal is stored in the storage medium. At present, the common image sensors on the market can be mainly divided into two types: charge coupled device (CCD) and complementary metal-oxide-semiconductor image sensor (CMOS image sensor). . Among them, compared with CCD, CMOS image sensor has low voltage and low power operation, low manufacturing cost, easy to reduce, high read rate, and system-on-a-chip (SOC) ( That is, high integration). Therefore, with the advancement of CMOS process technology, CMOS image sensors are gaining more and more attention, and have more potential for development. Generally, in an image sensing system, an image sensor is coupled to an image unit at the location of the image to facilitate receiving and processing image data obtained by the image. Although the image (4) towel noise _ is processed after the image data is taken, if the image process can be taken to reduce the existence of Wei Yuan, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SUMMARY OF THE INVENTION The above problems provide an image sensing device and an image sensing method for solving the problem of noise generated by a noise source in the process of capturing images in the prior art. _ The problem of the quality of the acquired image data. The invention includes the following: a timing generator, an image removal circuit, at least a first logic circuit, and at least a second circuit and a circuit. The logic circuit is electrically connected between the image capturing circuit and the timing generator. The first logic circuit is electrically connected to the image training circuit. And, the circuit is electrically connected between the timing generator and the second logic circuit. The sequence generator receives the system clock and outputs a clock signal according to the system clock. The first logic circuit receives the clock signal and controls the operation of the circuit according to the clock signal. Here, the image sensing process can be roughly divided into a sensing period and a reading period. The image capturing circuit senses the signal during sensing, and reads the captured signal during reading and generates an image signal. The interrupt circuit observes the second logic circuit when the sensing period is provided, and provides the pulse signal to the at least one second logic circuit when the reading is stopped. The image sensing method disclosed in the present invention includes: generating a control signal according to a clock signal by a first logic circuit; transmitting a 4-pulse signal to a second logic circuit; controlling reading of the image data by using the control signal; During the reading of the data, the mid-201032588 interrupts the clock signal input to the second logic circuit. In summary, the image sensing skirt and the image sensing method according to the present invention are applied to the image secreting system, and the image can be executed: #_ take care, interrupt circuit interrupt input to the second logic circuit (four) system clock, In order to reduce power noise caused by the current generated by the operation of the logic circuit. The following description of the embodiments is directed to and provides a patent application of the present invention
以上之關於本發明内容之說明及 以示範與解釋本發明之精神與原理， 範圍更進一步之解釋。 【實施方式】The scope of the present invention is further explained by the description of the present invention and the spirit and principle of the invention. [Embodiment]
參照「第1圖」 其顯示根縣翻—纽狀影像感測裝 影像感聰置包括影像練電路⑽、多個 生器150和中斷電路190。 電路時序產 於此，於影像感測裝置中，可將所古知 •:影像資料的讀取_的邏輯電路(即，第一邏二電 影像貧料的讀取不相關的邏輯電路（即，第二邏輊 與 言之，影像_過財纽上分為__和讀取叫。換 第一邏輯電路13〇電性 器150之間。第二邏輯電路Π0電;4接至影像m和時序產生 且，中斷電物電性連接於時序產生器第電=0。並 之間。 承一邏輯電路170 電性^:情電路190的輸出端與第二邏輯電路Μ的輪入端 201032588 分別屬於執行 於此’第一邏輯電路130與第二邏輯電路 170 不同功能的電路。 影像擷取電路m包括影像陣列元件lu和讀出電路出。 在感測期間，影像擷取電路110感測並儲存一揭取信號 讀取期間’歸娜電路11G讀取触錢並_產生影像峨。 多個畫素訊號（即，擷取信號）經由信號線從影像陣列元件 111讀出後’由讀出電路115進行雜訊消除和/或訊號放大等處理 ❹以輪出類比訊號之影像資料（即，影像信號）。 於讀出電路115的輪出端可電性連接類比數位轉換器119,即 類比數位轉換器119電性連接至影細取電路no。於此，可藉由 類比數位轉換器119將讀出電路115讀取的影像資料由類比訊號 轉換成數位訊號，以提供數位訊號之影像資料給後級的影像處理 單元進行各項影像處理。 第-邏輯f路13G和第二邏触路17()可電性連接至一電壓 源180。此電壓源180可分別提供第一邏輯電路13〇和第二邏輯電 路170運作時所需的電壓VI、V2。 於此，時序產生器15〇會接收系统時脈CK§，並依據系統時 脈CKs產生時脈訊號CK1給第一邏輯電路130和第二邏輯電路 170。然後，第一邏輯電路13〇再依據時脈訊號CK1產生控制訊 號，以藉由控制訊號控制影像操取電路11〇的運作。例如，第一 邏輯電路130可利用控制訊號控制影像陣列元件ηι擷取一影 像，以得到多個晝素訊號。並且，第一邏輯電路13〇可利用控制 訊號控制讀出電路115取樣自影像陣列元件m讀取的畫素訊號 6 201032588 以產生影像資料。 而第二邏輯電路170會經由中斷電路190接收時脈訊號CK1 並依據接收到的時脈訊號CK1而運作。換言之，中斷電路190的 輸出端電性連接至第二邏輯電路170的輸入端。於此，中斷電路 190會選擇性輸出時脈訊號CK1給第二邏輯電路170。 其中’於執行影像賁料的§買取期間，旗標訊號flag會被產生， 以致使中斷電路19〇依據旗標訊號flag中斷輸入至第二邏輯電路Referring to "Fig. 1", it is shown that the root county flip-up image sensing device image sensing device includes an image training circuit (10), a plurality of generators 150, and an interrupt circuit 190. The circuit timing is produced here, and in the image sensing device, the logic circuit that reads the image data is known (that is, the logic circuit that reads the first logic and the second image is unrelated) (ie, The second logic and the words, the image _ is divided into __ and read calls. The first logic circuit 13 is switched between the electrical device 150. The second logic circuit is 电0 electric; 4 is connected to the image m and The timing is generated and the interrupting electrical property is electrically connected to the timing generator. The electrical circuit is electrically connected to the timing generator 190. The output of the circuit 190 is connected to the second logic circuit 2010. The image capture circuit m includes an image array element lu and a readout circuit. The image capture circuit 110 senses during sensing. And storing a pick-up signal during the reading period [Genna circuit 11G reads the touch money and generates image 峨. The plurality of pixel signals (ie, the captured signal) are read out from the image array element 111 via the signal line. The circuit 115 performs processing such as noise cancellation and/or signal amplification. The image data of the analog signal (ie, the image signal) is electrically connected to the analog-to-digital converter 119 at the round end of the readout circuit 115, that is, the analog digital converter 119 is electrically connected to the shadow take-out circuit no. The image data read by the readout circuit 115 can be converted into a digital signal by the analog digital converter 119 to provide image data of the digital signal to the image processing unit of the subsequent stage for image processing. The f road 13G and the second logic contact 17 () can be electrically connected to a voltage source 180. The voltage source 180 can provide the voltages VI, V2 required for the operation of the first logic circuit 13 and the second logic circuit 170, respectively. Here, the timing generator 15 receives the system clock CK§ and generates the clock signal CK1 according to the system clock CKs to the first logic circuit 130 and the second logic circuit 170. Then, the first logic circuit 13 The control signal is generated according to the clock signal CK1 to control the operation of the image manipulation circuit 11 by the control signal. For example, the first logic circuit 130 can control the image array component ηι to capture an image by using the control signal. a plurality of pixel signals. The first logic circuit 13 can use the control signal to control the readout circuit 115 to sample the pixel signals 6 201032588 read from the image array component m to generate image data. The second logic circuit 170 The interrupt circuit 190 receives the clock signal CK1 and operates according to the received clock signal CK1. In other words, the output of the interrupt circuit 190 is electrically connected to the input terminal of the second logic circuit 170. Here, the interrupt circuit 190 is selective. The clock signal CK1 is output to the second logic circuit 170. The flag flag flag is generated during the § buy period of executing the image data, so that the interrupt circuit 19 interrupts the input to the second logic circuit according to the flag signal flag.
的時脈訊號CK卜換言之，於執行影像資料讀取的期間，中 斷電路190將不輸出時脈訊號CK1給第二邏輯電路170。如此一 來’即可減少邏輯電路（即，第二邏輯電路170)運作時產生的電 流所造成的電源雜訊。於此’旗標訊號flag可由影像擷取電路ιι〇 產生，即，影像擷取電路110可電性連接至中斷電路19〇 (圖中未 示）。或者是由時序產生器15〇來產生旗標訊號flag。 參照「第2圖」，時脈訊號CK1可區分成執行影像資料讀取 期間和非執行影像資料讀取_。於非執行影像資料讀取期間， 中斷電路190接收到低準位的旗標訊號flag，因而將接收到的時脈 訊號㈤輸出給第二邏輯電路17〇。因此，於非執行影像資料讀 取期間’第二邏輯電路170可接收解同於時脈峨㈤的時脈 訊被CK2。此時’進行運作白_電路較多，相對所產 電流也較大。 而於執行影像資料讀取的期間’中斷電路19〇接收到高狗: 的旗標訊號flag，因而中斷時脈訊號㈤； 影像細取躺，第二邏輯電㈣可接收職準位的= 201032588 號CK2。此時，進行運作的邏 流也較大。換言之，透過中斷電路 因而減少於執行影像龍讀取_，運抑運作 相對減少因賴電路運作喊生的缝電流。…隨量，以 。現=位雖然是以於非執行影料料讀取_，旗標訊號駟 王見低準位，而於執行影像資料讀取_，旗標 ^«,1 ^ , flag 相反，即為於雜柿賴料魏_為高準位，而 資料讀取間為低準位。 丁办像 於-實施射，參照「第3圖」，影像陣列树⑴主要且 有以二維配置排列的多個畫素單元U2所構成矩形影細取區域 A。於此麻輯a社面部何配置水传描電路⑴。水 平掃描電路113沿著影像擷取區域A中畫素單元ιΐ2的列(水平） 方向延伸。於此f彡像棘區域_邊部分可配置有垂直掃描電路 114。垂直掃描電路114沿著影像娜區域中晝素軍元⑴的行(垂 直)方向延伸。藉由水平掃描電路113及垂直掃描電路n4相繼掃 描影像擷祕域巾的畫素單元m，以於_躺執行畫素訊號的 感測以及電子快門操作。 讀出電路115可包括行處理電路和放大器118。行處理電路電 性連接至少一第一邏輯電路χ3〇和影像陣列元件i u。放大器i j8 電性連接至少一第一邏輯電路13〇和行處理電路。 其中，行處理電路可為關聯雙取樣（correlated double 201032588 sampling ; CDS)元件116。此CDS元件116的後級（輪出端）可 配置有多工器117。 CDS元件116配置於影像陣列元件⑴的後級(輸出端卜於 CDS元件116中’以對應於每一行晝素單元112的方式配置有多 個CDS電路。 畫素訊號經由對應之垂直訊號線[從影像_元件⑴中每 一行晝素單元112中讀取並相繼輸入至CDS元件116對應的cds 電路中卩執行畫素訊號的消去雜訊的訊號處理。 /工器117電性連接於CDS元件116和放大器ιΐ8之間。多 工。。117可控制CDS兀件116的訊號輸出’ #其可於—時間點選 擇一行的訊號輸出。 於此，放大器118可為可程式化增益放大器。 貝出電路115的後、級（輸出端）可配置類比數位轉換器lip。 於此，類比數位轉換n 119電性連接於放大器118的輪出端。 類比數位轉換器U9接收放大器118放大後而輪出的影像資 r並且將讀取的影像資料由類比訊號轉換成數位職。換古之， 類比數位轉換器119可將類比影像#料轉換成數位影像資料。 中，類比數位轉換器119可為δς調變器。 於類比數位轉換器119的後級（輪屮破、取 元銳（輸“）可配置f彡像處理單 行數位訊號的處理。換言之，於類比 類比的前段區域係進行類比影像資料的影像處理，而 理。轉換益119❸後段區域則係進行數位影像資料的影像處 201032588 影像處理單元即可包括有帛二邏輯電路17G，並且細第二邏 輯電路170來進行類比影像處理。 於此，影像陣列元件1n、CDS元件Π6、多工器117、放大 器118和類比數位轉換器119接收來自第一邏輯電路13〇的控制 訊號，並且依據接收到的控制訊號而運作。 其中，第一邏輯電路130係依據時脈訊號〇^1而產生控制訊 號。 ❹ 而第二邏輯電路Π0會接收來自中斷電路190的時脈訊號 CK1，並依據接收到的時脈訊號沈}而運作。 時序產生器150於接收系統時脈CKs後，會依據系統時脈CKs 產生時脈訊號CK1給第一邏輯電路13〇和中斷電路190。 並且’於執行影像資料讀取期間’中斷電路19〇依據旗標訊 號flag中斷輸入至第二邏輯電路17〇的時脈訊號CK1，因而第二 邏輯電路170因未接收到時脈訊號CK1 (即，輸入訊號為低準位） 而不運作。如此一來’即於執行影像資料讀取期間，可減少邏輯 ® 電路運作時產生的電流所造成的電源雜訊。 參照「第4圖」，係為根據本發明一實施例之影像感測方法 的流程圖。 於此’藉由第一邏輯電路依據時脈訊號產生控制訊號（步驟 21〇)。輸入時脈訊號至第二邏輯電路（步驟220)。利用控制訊 號控制影像資料的讀取，並且於影像資料的讀取期間，中斷輸入 至第二邏輯電路的時脈訊號（步驟230)。 並且’參照「第5圖」，可將讀取的影像資料由類比訊號轉 i0 201032588 換成數位訊號（步驟240 )，以提供給後級處理單元進行數位影像 資料的訊號處理。即，可將讀取的類比影像資料轉換成數位影像 資料。 此外，參照「第ό圖」，可藉由第二邏輯電路依據時脈訊號 進行讀取的影像資料的訊號處理（步驟250)。 再者，參照「第7圖」，可先利用控制訊號控制影像的擷取， 以得到多個畫素訊號（步驛加），然後再透過取樣此些畫素訊號 而讀取影像資料（步驟234)。 根據本㈣之影像❹彳裝置及影像感财法，躺於影像感 測系統，可於執行影像資料讀取期間，利用中斷電路中斷輸入至 第二邏輯電路的祕時脈，藉以減少邏輯電路運作時產生的電流 所造成的電源雜訊。 雖然本發明以前述之實施例揭露如上，然其並非用以限定本 發月在不脫離本發明之精神和範圍内，戶斤為之更動與潤飾，均 屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考 ® 所附之申請專利範圍。 【圖式簡單說明】 第1圖係為根據本發明一實施例之影像感測裴置的概要示意 圖； =2圖係顯不根據本發明一實施例中，各訊號的時序關係圖； 第3圖係為根據本發明另一實施例之影像感測裝置的概要示 意圖； 第圖係為根據本發明第一實施例之影像感測方法的流程圖； 201032588 第5圖係為根據本發明第二實施例之影像感測方法的流程圖； 第6圖係為根據本發明第三實施例之影像感測方法的流程 圖；以及 第7圖係為於根據本發明一實施例中，讀取影像資料的細部 流程圖。 【主要元件符號說明】 110 .............................影像擷取電路 111 .............................影像陣列元件 112 .............................晝素單元 113 .............................水平掃描電路 114 .............................垂直掃描電路 115 .............................讀出電路 116 .............................關聯雙取樣元件 117 .............................多工器 118.............................放大器 ® 119.............................類比數位轉換器 130.............................第一邏輯電路 150.............................時序產生器 170.............................第二邏輯電路 180.............................電壓源 190.............................中斷電路 VI..............................電壓 V2..............................電壓 12 201032588 CKs...........................系統時脈 CK1...........................時脈訊號 flag.............................旗標訊號 CK2............................時脈訊號 A................................影像擷取區域 L................................垂直訊號線In other words, during the execution of the reading of the image data, the interrupt circuit 190 will not output the clock signal CK1 to the second logic circuit 170. In this way, the power noise caused by the current generated when the logic circuit (i.e., the second logic circuit 170) operates can be reduced. The flag signal flag can be generated by the image capturing circuit ιι, that is, the image capturing circuit 110 can be electrically connected to the interrupt circuit 19 (not shown). Alternatively, the timing generator 15 is used to generate the flag signal flag. Referring to "Fig. 2", the clock signal CK1 can be divided into the execution of the image data reading period and the non-executing image data reading_. During the non-executed image data reading, the interrupt circuit 190 receives the flag signal flag of the low level, and thus outputs the received clock signal (5) to the second logic circuit 17A. Therefore, during the non-execution of the image data reading period, the second logic circuit 170 can receive the time pulse CK2 which is the same as the clock (5). At this time, there are many circuits that operate white, and the current is relatively large. During the execution of the image data reading, the interrupt circuit 19 receives the flag signal flag of the high dog: thus interrupting the clock signal (5); the image is finely taken, and the second logical power (4) can receive the duty level = 201032588 No. CK2. At this time, the logic flow for operation is also large. In other words, by interrupting the circuit, it is reduced to perform the image read _, and the hold operation relatively reduces the seam current that is shouted by the operation of the circuit. ...with quantity, to . Although the current = bit is based on the non-executive shadow material reading _, the flag signal 驷 Wang sees the low level, and in the execution of the image data read _, the flag ^«, 1 ^, flag is the opposite, that is The persimmons are high-level, while the data reading is low. For example, the image array tree (1) mainly has a rectangular image capturing area A formed by a plurality of pixel units U2 arranged in a two-dimensional arrangement. This is a collection of water-discharging circuits (1). The horizontal scanning circuit 113 extends in the column (horizontal) direction of the pixel unit ι2 in the image capturing area A. In this case, the vertical scanning circuit 114 may be disposed. The vertical scanning circuit 114 extends in the row (vertical) direction of the elementary element (1) in the image area. The pixel unit m of the image mask is successively scanned by the horizontal scanning circuit 113 and the vertical scanning circuit n4 to perform sensing of the pixel signal and electronic shutter operation. Readout circuitry 115 can include a row processing circuit and amplifier 118. The row processing circuit is electrically connected to at least a first logic circuit χ3〇 and an image array element i u. The amplifier i j8 is electrically connected to at least a first logic circuit 13 〇 and a row processing circuit. The row processing circuit can be a correlated double sampling (CDS) component 116. The rear stage (rounding end) of this CDS element 116 can be configured with a multiplexer 117. The CDS element 116 is disposed in a subsequent stage of the image array element (1) (the output end is in the CDS element 116). A plurality of CDS circuits are disposed in a manner corresponding to each row of the pixel unit 112. The pixel signal is transmitted via the corresponding vertical signal line [ Read and successively input from each row of pixel units 112 in the image element (1) to the cds circuit corresponding to the CDS element 116, and perform signal processing for canceling noise of the pixel signal. The device 117 is electrically connected to the CDS element. Between 116 and amplifier ι ΐ 8. multiplexed. 117 can control the signal output of CDS element 116 '# It can select one line of signal output at time point. Here, amplifier 118 can be a programmable gain amplifier. The analog, digital (inverter) of the circuit 115 can be configured with an analog digital converter lip. Here, the analog digital conversion n 119 is electrically connected to the output of the amplifier 118. The analog digital converter U9 receives the amplifier 118 and rotates it. The image data is converted from the analog signal into a digital position. In other words, the analog digital converter 119 can convert the analog image into digital image data. The converter 119 can be a delta ς modulator. In the latter stage of the analog-to-digital converter 119 (the rim is broken, the plucking is sharp), the f-image can be configured to process the single-line digital signal. In other words, in the front of the analogy analogy The area system performs image processing of the analog image data, and the image area of the digital image data in the posterior segment of the conversion is 119, and the image processing unit may include the second logic circuit 17G, and the second logic circuit 170 performs the second logic circuit 170. Analog image processing. Here, the image array element 1n, the CDS element Π6, the multiplexer 117, the amplifier 118, and the analog-to-digital converter 119 receive the control signal from the first logic circuit 13 and operate according to the received control signal. The first logic circuit 130 generates a control signal according to the clock signal 。^1, and the second logic circuit Π0 receives the clock signal CK1 from the interrupt circuit 190, and is based on the received clock signal. The timing generator 150 generates the clock signal CK1 according to the system clock CKs to the first logic circuit 13 after receiving the system clock CKs. The circuit 190. And during the reading of the image data read, the interrupt circuit 19 interrupts the clock signal CK1 input to the second logic circuit 17 according to the flag signal flag, and thus the second logic circuit 170 does not receive the clock signal. CK1 (ie, the input signal is at a low level) does not operate. This way, during the reading of the image data, the power noise caused by the current generated by the logic® circuit can be reduced. Refer to Figure 4 The flowchart of the image sensing method according to an embodiment of the present invention is as follows: [The first logic circuit generates a control signal according to the clock signal (step 21A). The clock signal is input to the second logic circuit (step 220). The reading of the image data is controlled by the control signal, and the clock signal input to the second logic circuit is interrupted during the reading of the image data (step 230). And by referring to "figure 5", the read image data can be converted from the analog signal to i0 201032588 into a digital signal (step 240) to provide the subsequent processing unit with signal processing of the digital image data. That is, the read analog image data can be converted into digital image data. In addition, referring to the "figure map", the signal processing of the read image data can be performed by the second logic circuit according to the clock signal (step 250). Furthermore, referring to "Picture 7", the control signal can be used to control the image capture to obtain a plurality of pixel signals (steps), and then the image data is read by sampling the pixel signals (steps). 234). According to the image device and the image sensing method of (4), lying in the image sensing system, the interrupt circuit can be used to interrupt the input to the second logic circuit during the reading of the image data, thereby reducing the logic circuit operation. Power noise caused by the current generated. While the present invention has been disclosed in the foregoing embodiments, it is not intended to limit the scope of the present invention, and the modifications and refinements of the present invention are within the scope of the present invention. For the scope of protection defined by the present invention, please refer to the scope of the patent application attached to ® . BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing an image sensing device according to an embodiment of the present invention; FIG. 2 is a timing diagram showing signals according to an embodiment of the present invention; The figure is a schematic diagram of an image sensing apparatus according to another embodiment of the present invention; the figure is a flowchart of an image sensing method according to the first embodiment of the present invention; 201032588 FIG. 5 is a second according to the present invention. A flowchart of an image sensing method according to an embodiment; FIG. 6 is a flowchart of an image sensing method according to a third embodiment of the present invention; and FIG. 7 is a view for reading an image according to an embodiment of the present invention. Detailed flow chart of the data. [Main component symbol description] 110 .......................Image capture circuit 111 ......... ....................Image Array Element 112 ......................... ...the prime unit 113 ............................. horizontal scanning circuit 114 .......... ...................Vertical Scanning Circuit 115 ........................... .. readout circuit 116 .......................associated double sampling element 117 .......... ...................Multiplexer 118........................... ..Amplifier® 119....................... Analog Analog Digital Converter 130........... ..................first logic circuit 150........................... .. timing generator 170.............................second logic circuit 180.......... ...................Voltage source 190............................ Interrupt Circuit VI..............................Voltage V2............. ................Voltage 12 201032588 CKs..............................System clock CK1...........................clock signal flag.................. ...........flag signal CK2......... ...................clock signal A........................... .....Image capture area L................................ Vertical signal line