201023377 九、發明說明： 【發明所屬之技術領域】 * 本發明係有關於一種可增加受光面積及提高光電轉 - 換效率之太陽能電池板之製作方法及其結構。 【先前技術】 如第1圖所示，習知多晶矽太陽能電池板為傳輪照光 後所產生的電流，大都於一 η型半導體層90之一受光面 9〇a設置有複數條電流傳導銀線L1及複數條锡連接線 & L2，以藉由該些電流傳導銀線L1及該些錫連接線L2將電 流傳輸至一蓄電池’然而’該些電流傳導銀線L1及該些 錫連接線L2形成於該η型半導體層90之該受光面9〇a， 係會造成該η型半導體層90之受光面積大為減少，導致 太陽能電池板之光電轉換效率大幅降低。 【發明内容】 本發明之主要目的係在於提供一種太陽能電池板之 〇 製作方法及其結構，其製作方法係包含提供一 η型半導體 基板，該η型半導體基板係具有一受光面、一相對於該受 光面之背面及複數個凹設於該背面之溝槽；分別於該11型 半導體基板之各該溝槽中形成一 ρ型半導體層；提供一基 板，該基板係具有-表面及複數條形成於該表面之電傳導 線；以及將該基板貼合於該η型半導體基板之該背面，以 使該些電傳導線分別接觸該η型半導體基板之該背面及該 些Ρ型半導體層，本發明係於該η型半導體基板之該背面 形成連續性ρ-η半導體結構，並將該些電傳導線設置於該 5 201023377 背面#於該η型+導體基板之該冑光面沒有電傳導線之 遮蔽’因& ’受光面積可大幅提高，此外，由於該η型半 導體基板之該背面係可以透明之絲板覆蓋，因此，太陽 光亦可穿透該基板而照射到該η型半導體基板之該背面， 達到雙面可照光’因其受光面積大幅增加，故光電轉換效 率將可大幅提高。 【實施方式】 請參閱第2及3八至3(：圖，其係本發明之一較佳實施 例，一種太陽能電池相#4 此电池板之製作方法，其步驟係詳述如下： 首先’請參閱第2圖之步驟⑷及第3Α圖，提供一 η型半 導體基板10，該11型车道1Γι ^ i牛導體基板10係具有一受光面1〇a、 一相對於該受光面1Ga之背面⑽及複數個凹設於該背面 1〇b之溝# 11 ’在本實施例中，各該溝槽η之間的間距 係相等’且各該溝槽u係具有一第一寬度wi;接著請 ❹ 參閱第2圖之㈣_第3B圖’分別於該η型半導體基 板1 0之各該溝槽J i中你J # 價中形成一 p型半導體層20,在本實施 例中，各該 P型半導體層20係具有-第二寬度W2,該第二寬度 W2係與各該溝槽n之該第一寬度们相等，此外，各該 P型半導體層20之高度係不大於各該溝槽n之深度，較 佳地’各該P型半導體層2G之高度係與各該溝槽u之深 度相等；之後，請參閱第2圖之步驟⑷及第3C圖，提供 一基板3 0 ’在本實施例中，·^发> I』甲β亥基板30係為透明基板，且 該基板30係具有-表面施、複數條形成於該表面3〇a之 201023377 Ο ❹ 電傳導線3 1、一第一連接線32及一第二連接線33，各該 電傳導線3 1係含有複數個核殼型導電粒子4〇，在本實施 例中’該些核殼型導電粒子4 0係為銅-踢核殼型導電粒 子’各該銅-錫核殼型導電粒子係具有一銅粒子41及一包 覆該銅粒子41之錫包覆層42，在本實施例中，該些銅· 錫核殼型導電粒子之尺寸係介於0<1微米至12微米之間， 且較佳地，各該銅粒子41之粒徑係介於〇·丨微米至丨〇微 米之間，而各該錫包覆層42之厚度係介於〇 〇1微米至2 微米之間，或者，請參閱第5圖，在另一實施例中，該些 核殼型導電粒子40係可為銅_銀_錫核殼型導電粒子，各該 銅-銀-錫核殼型導電粒子係具有一銅粒子41、一形成於該 銅粒子4丨表面之銀包覆層43以及一形成於該銀包覆層43 上之錫包覆層42，在本實施例中，該些銅·銀·錫核殼型導 電粒子之尺寸係介於G< i微米至12微米之間，其中該銅粒 子41之粒徑係介於°，1微米至1〇微米之間，該銀包覆層 係具有複數個覆蓋該銅粒子41表面之銀島仏，且各 »亥銀島43a之間係具有_顯露該銅粒+ 4工纟面之空間 43b’在本實施例中’該些銀島仏之厚度係介於【奈米 至50奈米之間，且辞此 且该些銀島43a係呈不規則排列，又， 較佳地，該些空間43b係相互連通，此外，該錫包覆層42 係覆蓋該銀包覆層43之該些銀島43a且填充於該些空間 4扑’較佳地’該錫包覆層42之厚度係介於0.01微米至2 微米之間，請再參閲第3C冑，在本實施例中，該些電傳 導線31係' 包含有複數條第-電傳導線3U及複數條第二 201023377 電傳導線312,其中各該第二電傳導線312係位於各該第 一電傳導線3 11之間，該第一連接線32係連接該些第一 電傳導線311，而該第二連接線33係連接該些第二電傳導 ， 線312;最後，請參閱第2圖之步驟（d)及第3D圖，將該 基板30貼合於該n型半導體基板1〇之該背面i〇b，以使 該些電傳導線31分別接觸該n型半導體基板1〇之該背面 i〇b及該些p型半導體層20，請參閱第4圖，在本實施例 〇 中，該些第一電傳導線311係接觸該n型半導體基板ι〇 之該背面i〇b，而該些第二電傳導線312係分別接觸各該 . p型半導體層20，又，較佳地，該些第一電傳導線311係 可接合於該η型半導體基板1〇之該背面1〇b，而該些第二 電傳導線3 12係可分別接合於各該p型半導體層2〇。 本發明係於該n型半導體基板1〇之該背面i〇b形 成連續性p-n半導體結構，並將該些電傳導線3丨設置於該 背面10b’由於該n型半導體基板1〇之該受光面ι〇&沒有 〇 電傳導線之遮蔽，因此，受光面積可大幅提高，此外，由 於該Ϊ1型半導體基板10之該背面1〇b係以透明之該基板 3〇覆蓋，因此，太陽光亦可穿透該基板3〇而照射到該n 型半導體基板10之該背面1 〇b，達到雙面可照光，因其受 光面積大幅增加，故光電轉換效率將可大幅提高。 請再參閱第3D及4圖，其係利用本發明之製作方法 所製得之太陽能電池板結構係包含有一 n型半導體基板 1〇、複數個P型半導體層20以及一基板3〇，該n型半導 體基板10係具有一受光面l0a、一相對於該受光面ι〇&之 8 201023377 背面m及複數個凹設於該背面1〇b之溝# n，在本實施 例中’各該溝槽11之間的間距係相等，且各該溝槽U係 - 纟有―第—寬度W1 ’該些P型半導體層2G係分別形成於 ， 該n型半導體基才反10之各該溝# 11巾，在本實施例中， 各該P型半導體層20係、具有一第=寬度W2，該第二寬度 W2係與各該溝槽丄i之該第―寬度们彳目冑n μ Ρ型半導體層20之高度係不大於各該溝槽丨丨之深度，= ❹佳地，各該ρ型半導體層2G之高度係與各該溝槽u之深 度相等，該基板30係貼合於該n型半導體基板1〇之該背 • 面1〇b，在本實施例中，該基板30係為透明基板，且該基 . 板3〇具有一表面30a、複數條形成於該表面3(^之電傳導 線31、一第一連接線32及一第二連接線33，該些電傳導 線31係分別接觸該n型半導體基板1〇之該背面i〇b及該 些P型半導體層20，在本實施例中，該些電傳導線3 ι係 包含有複數條第一電傳導線3 11及複數條第二電傳導線 Q 312，其中各該第二電傳導線312係位於各該第一電傳導 線3 11之間’此外，該些第一電傳導線3丨丨係接觸該n型 半導體基板10之該背面10b’而該些第二電傳導線312係 分別接觸各該p型半導體層20,又，在本實施例中，該第 一連接線32係連接該些第一電傳導線311，而該第二連接 線32係連接該些第二電傳導線312，請再參閱第3(：及* 圖’各該電傳導線3 1係含有複數個核殼型導電粒子4〇， 在本實施例中，該些核殼？ϋ導電粒子40係為銅_錫核殼型 導電粒子’各該銅-錫核殼型導電粒子40係具有一銅粒子 9 201023377 41及一包覆該鋼粒子41之錫包覆層42，在本實施例中， 該些銅-錫核殻型導電粒子4〇之尺寸係介於〇1微米至以 微米之間，且較佳地，各該銅粒子41之粒徑係介於〇^ 微米至10微米之間，而各該錫包覆層42之厚度係介於 0.01微米至2微米之間，或者，言f再參閱第5 0，在另一 實施例中，該些核殼型導電粒子4〇係可為銅_銀_錫核殼型 導電粒子，各該銅-銀_錫核殼型導電粒子係具有一鋼粒子 Ο 41、一形成於該鋼粒子41表面之銀包覆層43以及一形成 於該銀包覆層43上之錫包覆層42，在本實施例中，該些 銅-銀-錫核殼型導電粒子之尺寸係介於〇【微米至Η微米 之間’其中該銅粒子41之粒徑係介於〇1微米至ι〇微米 之間’該銀包覆層43係具有複數個覆蓋該銅粒子Μ表面 之銀島43a’且各該銀島43a之間係具有—顯露該銅粒子 〇表面之空間43b，在本實施例中，該些銀島仏之厚度 係介於i奈米i 50奈米之間’且該些銀島—係呈不規 則排列，又’車交佳地’該些空間43b係相互連通，此外， 該錫包覆層42係覆蓋該銀包覆層43之該些銀島…且填 充於該些空間4讣，較佳地’該錫包覆層42之厚度係介於 0·01微米至2微米之間。 本發明之保護範圍當視後附之中請專利範圍所界定 者為準’㈣熟知此項技藝者’在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護範 圍。 【圖式簡單說明】 10 201023377 圍· w知夕晶矽太陽At 陽此電池板之結構示意圖。 圖：依據本發明之一番 較佳實施例，—種太陽能 第 1 第 2 電池板之製作方法流程圖 第3A至則：該太陽能電池板之製作方法示意圖。 第 4 圖·沿第3D圖α·α始 線’該太陽能電池板之結 構剖視圖。 第 5 圖：依據本發明之一具辦眘& ν , 殼型導電粒？之結㈣t ® 【主要元件符號說明】 具體實施例，鋼-銀-錫核201023377 IX. Description of the invention: [Technical field to which the invention pertains] * The present invention relates to a method and a structure for fabricating a solar panel capable of increasing light receiving area and improving photoelectric conversion-change efficiency. [Prior Art] As shown in Fig. 1, a conventional polycrystalline silicon solar panel is a current generated by a relay illumination, and a plurality of current conducting silver wires are disposed on a light receiving surface 9〇a of an n-type semiconductor layer 90. L1 and a plurality of tin wires & L2, for transmitting current to the battery by the current conducting silver wire L1 and the tin connecting wires L2, but the current conducting silver wires L1 and the tin connecting wires The formation of L2 on the light-receiving surface 9〇a of the n-type semiconductor layer 90 causes the light-receiving area of the n-type semiconductor layer 90 to be greatly reduced, resulting in a significant decrease in the photoelectric conversion efficiency of the solar cell panel. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for fabricating a solar cell and a structure thereof, the method of fabricating the same, comprising: providing an n-type semiconductor substrate having a light receiving surface and a relative a back surface of the light receiving surface and a plurality of grooves recessed in the back surface; forming a p-type semiconductor layer in each of the trenches of the 11-type semiconductor substrate; providing a substrate having a surface and a plurality of strips An electrically conductive line formed on the surface; and bonding the substrate to the back surface of the n-type semiconductor substrate such that the electrically conductive lines respectively contact the back surface of the n-type semiconductor substrate and the germanium-type semiconductor layers, According to the present invention, a continuous p-n semiconductor structure is formed on the back surface of the n-type semiconductor substrate, and the electrically conductive lines are disposed on the back surface of the 5 201023377. The light-emitting surface of the n-type + conductor substrate has no electrical conduction. The line shadow 'in & 'the light-receiving area can be greatly improved, and since the back surface of the n-type semiconductor substrate can be covered by a transparent silk plate, the sunlight The substrate is irradiated to penetrate the back surface of the η-type semiconductor substrate, can achieve a double-sided illumination 'substantial increase in its light receiving area, so that photoelectric conversion efficiency will be greatly improved. [Embodiment] Please refer to Figs. 2 and 3-8 to 3 (Fig., which is a preferred embodiment of the present invention, a method for fabricating a solar cell phase #4, the steps of which are detailed as follows: Referring to step (4) and FIG. 3 of FIG. 2, an n-type semiconductor substrate 10 having a light-receiving surface 1〇a and a back surface opposite to the light-receiving surface 1Ga is provided. (10) and a plurality of grooves #11b recessed in the back surface 1 'b. In this embodiment, the spacing between the grooves η is equal ' and each of the grooves u has a first width wi; Please refer to FIG. 2(4)_3B' to form a p-type semiconductor layer 20 in the J# price of each of the trenches J of the n-type semiconductor substrate 10, in this embodiment, each The P-type semiconductor layer 20 has a second width W2 equal to the first width of each of the trenches n, and the height of each of the P-type semiconductor layers 20 is not greater than The depth of the trench n is preferably 'the height of each of the P-type semiconductor layers 2G is equal to the depth of each of the trenches u; after that, please refer to the second In the steps (4) and 3C of the figure, a substrate 30 is provided. In the present embodiment, the substrate 19 is a transparent substrate, and the substrate 30 has a surface and a plurality of strips. a 201023377 Ο ❹ electrically conductive line 3 1 , a first connecting line 32 and a second connecting line 33 formed on the surface 3 〇 a, each of the electrically conductive lines 31 1 comprising a plurality of core-shell conductive particles 4 〇, In the present embodiment, the core-shell type conductive particles 40 are copper-kick core-shell type conductive particles, each of which has a copper particle 41 and a coated copper particle 41. The tin-clad layer 42. In this embodiment, the copper-tin-core-shell-type conductive particles have a size between 0 μm and 12 μm, and preferably, each of the copper particles 41 The diameter of the tin coating layer is between 〇〇1 μm and 2 μm, or the thickness of each tin coating layer 42 is between 微米1 μm and 2 μm, or, referring to Fig. 5, in another implementation In the example, the core-shell type conductive particles 40 may be copper-silver-tin core-shell type conductive particles, and each of the copper-silver-tin core-shell type conductive particles has a copper particle 4 1. A silver coating layer 43 formed on the surface of the copper particles 4 and a tin coating layer 42 formed on the silver cladding layer 43. In this embodiment, the copper, silver and tin core shells The size of the type of conductive particles is between G < i micrometers and 12 micrometers, wherein the copper particles 41 have a particle diameter of between 1 micrometer and 1 micrometer, and the silver coating layer has a plurality of layers. The silver islands on the surface of the copper particles 41, and each of the islands 43a have a space 43b' which reveals the copper particles + 4 work surface. In the present embodiment, the thickness of the silver islands is Between [nano and 50 nm], and the silver islands 43a are arranged irregularly, and preferably, the spaces 43b are in communication with each other, and further, the tin coating 42 is covered. The silver islands 43a of the silver coating layer 43 are filled in the spaces 4, preferably the thickness of the tin cladding layer 42 is between 0.01 micrometers and 2 micrometers. Please refer to the 3C. In the present embodiment, the electrically conductive lines 31 comprise a plurality of first-electrically conductive lines 3U and a plurality of second 201023377 electrically conductive lines 312, wherein each of the second transmissions The line 312 is located between each of the first electrically conductive lines 3 11 . The first connection line 32 is connected to the first electrically conductive lines 311 , and the second connection line 33 is connected to the second electrically conductive lines. 312. Finally, referring to steps (d) and 3D of FIG. 2, the substrate 30 is attached to the back surface i〇b of the n-type semiconductor substrate 1 so that the electrically conductive lines 31 are respectively contacted. Referring to FIG. 4, in the embodiment, the first electrically conductive lines 311 are in contact with the n-type semiconductor substrate. The second electrically conductive line 312 is in contact with each of the p-type semiconductor layers 20, and preferably, the first electrically conductive lines 311 are bonded to the n The back surface 1b of the semiconductor substrate 1 is formed, and the second conductive lines 312 are respectively bonded to the respective p-type semiconductor layers 2''. According to the present invention, the back surface i〇b of the n-type semiconductor substrate 1 is formed with a continuous pn semiconductor structure, and the electrically conductive lines 3 are disposed on the back surface 10b′ due to the light reception of the n-type semiconductor substrate 1 Since the surface ι〇& is not shielded by the conductive line, the light-receiving area can be greatly improved, and since the back surface 1〇b of the Ϊ1 type semiconductor substrate 10 is covered with the transparent substrate 3〇, the sunlight is It is also possible to penetrate the substrate 3A and irradiate the back surface 1b of the n-type semiconductor substrate 10 to achieve double-sided illumination, and since the light-receiving area is greatly increased, the photoelectric conversion efficiency can be greatly improved. Please refer to FIGS. 3D and 4 again. The solar panel structure obtained by the manufacturing method of the present invention comprises an n-type semiconductor substrate 1 , a plurality of P-type semiconductor layers 20 and a substrate 3 〇. The semiconductor substrate 10 has a light-receiving surface 10a, a back surface m with respect to the light-receiving surface ι〇& 8 201023377, and a plurality of grooves #n recessed in the back surface 1〇b, in the present embodiment The pitches between the trenches 11 are equal, and each of the trenches U-- has a "first width W1". The P-type semiconductor layers 2G are formed respectively, and the n-type semiconductor bases are opposite to each other. #11巾, in this embodiment, each of the P-type semiconductor layers 20 has a width = W2, and the second width W2 and the first width of each of the trenches 丄i are 胄n μ The height of the germanium-type semiconductor layer 20 is not greater than the depth of each of the trenches, and preferably, the height of each of the p-type semiconductor layers 2G is equal to the depth of each of the trenches u, and the substrate 30 is bonded. In the back surface 1b of the n-type semiconductor substrate 1 , in the embodiment, the substrate 30 is a transparent substrate, and the base The plate 3 has a surface 30a formed on the surface 3 (the electrically conductive line 31, a first connecting line 32 and a second connecting line 33, the electrically conductive lines 31 respectively contacting the n-type In the embodiment, the electrically conductive lines 3 ι include a plurality of first electrically conductive lines 3 11 and a plurality of second electric wires. a conductive line Q 312, wherein each of the second electrically conductive lines 312 is located between each of the first electrically conductive lines 3 11 ' Further, the first electrically conductive lines 3 are in contact with the n-type semiconductor substrate 10 The first conductive line 312 is in contact with each of the p-type semiconductor layers 20, and in the embodiment, the first connecting line 32 is connected to the first electrically conductive lines 311. The second connecting line 32 is connected to the second electrically conductive lines 312. Please refer to the third (: and * diagrams). Each of the electrically conductive lines 3 1 includes a plurality of core-shell type conductive particles 4 〇, in this embodiment. The core-shell conductive particles 40 are copper-tin-core-shell-type conductive particles. Each of the copper-tin core-shell conductive particles 40 has a copper particle. 9 201023377 41 and a tin coating layer 42 covering the steel particles 41. In the embodiment, the copper-tin core-shell type conductive particles 4〇 are between 〇1 μm and μm. And preferably, each of the copper particles 41 has a particle diameter of between 〇μm and 10 μm, and each of the tin cladding layers 42 has a thickness of between 0.01 μm and 2 μm, or Referring to FIG. 50 again, in another embodiment, the core-shell type conductive particles 4 can be copper-silver-tin core-shell type conductive particles, and each of the copper-silver-tin core-shell type conductive particles has a steel particle crucible 41, a silver coating layer 43 formed on the surface of the steel particle 41, and a tin coating layer 42 formed on the silver cladding layer 43, in the embodiment, the copper-silver- The size of the tin-core shell-type conductive particles is between 微米 [micron to Η micron 'where the diameter of the copper particles 41 is between 〇 1 μm and ι 〇 micron'. The silver cladding layer 43 has a plurality The silver islands 43a' covering the surface of the copper particles and each of the silver islands 43a have a space 43b exposing the surface of the copper particles, in the embodiment, the The thickness of the island is between i nanometers and 50 nanometers, and the silver islands are arranged in an irregular arrangement, and the spaces 43b are connected to each other. In addition, the tin coating is in contact with each other. The layer 42 covers the silver islands of the silver cladding layer 43 and is filled in the spaces 4, preferably the thickness of the tin cladding layer 42 is between 0. 01 micrometers and 2 micrometers. The scope of the present invention is defined by the scope of the invention as defined by the appended claims. (4) Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are protected by the present invention. range. [Simple description of the diagram] 10 201023377 The structure of the solar panel of the sun and the sun. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3A is a flow chart showing a method of fabricating a solar cell according to a preferred embodiment of the present invention. Fig. 4 is a cross-sectional view showing the structure of the solar cell panel along the line α·α of Fig. 3D. Figure 5: According to one of the present invention, it is prudent & ν, shell-type conductive particles? Knot (4) t ® [Main component symbol description] Specific embodiment, steel-silver-tin core
l〇b背面 電傳導線 第一連接線 10 η型半導體基板10a受光面 Π 溝槽 20 p型半導體層 30a表面 .31 312第二電傳導線32 3 0 基板 3 11第一電傳導線 33第二連接線 40 核殼型導電粒子 41 銅粒子 43a銀島 42錫包覆層 43銀包覆層 43b空間 90 n型半導體層90a受光面 L1電流傳導銀線L2錫連接線 W1第-寬度 W2第二寬度 (a)提供_n型半導體基板，該η型半導體基板係具有— 又光面、一相對於該受光面之背面及複數個凹設於該 背面之溝槽 201023377 (b) 分別於該n型半導體基板之各該溝槽_形成一 p塑半 導體層 (c) 提供一基板’該基板係具有一表面及複數條形成於該 • 表面之電傳導線 (d) 將該基板貼合於該η型半導體基板之該背面，以使該 些電傳導線分別接觸該η型半導體基板之該背面及該 些ρ型半導體層 ❹ ❹ 12L〇b back electrically conductive line first connecting line 10 n-type semiconductor substrate 10a receiving surface 沟槽 trench 20 p-type semiconductor layer 30a surface. 31 312 second electrically conductive line 32 3 0 substrate 3 11 first electrically conductive line 33 Two connection wires 40 core-shell type conductive particles 41 copper particles 43a silver island 42 tin cladding layer 43 silver cladding layer 43b space 90 n-type semiconductor layer 90a light-receiving surface L1 current conduction silver wire L2 tin connection wire W1 first-width W2 The second width (a) provides an _n-type semiconductor substrate having a smooth surface, a back surface opposite to the light-receiving surface, and a plurality of trenches recessed in the back surface 201023377 (b) respectively Each of the trenches of the n-type semiconductor substrate forms a p-semiconductor layer (c) to provide a substrate having a surface and a plurality of electrically conductive lines formed on the surface (d) to bond the substrate to The back surface of the n-type semiconductor substrate is such that the electrically conductive lines respectively contact the back surface of the n-type semiconductor substrate and the p-type semiconductor layers ❹ 12