201025258 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種脈波調整電路及使用該脈波調整電 路之驅動電路。 【先前技術】 瑕日日顯示裝置具有輻射低 .....—^ 廣泛應用於顯示器、液晶電視、移動電話及筆記本電腦等 ❹領域’並成為顯示器之主流。在液晶顯示裝置中，閘極驅 動電路籍由掃描線耦接至薄膜電晶體之閘極以控制薄膜電 晶體之導通與關閉。然’由於薄膜電晶體之閘極端之寄生 電阻及寄生電容之存在，使得於薄膜電晶體之閘極端關閉 時液晶顯示裝置之顯示晝面出現閃爍之現象。先前技術 中，通常於液晶顯示裝置之驅動電路中增加一脈波調整電 路以減少顯示晝面之閃爍現象。 請參閱圖1，係一種先前技術液晶顯示裝置驅動電路 ❿之方框示意圖。該驅動電路1〇〇包括一電源電路n〇、一 時序控制電路120、一脈波調整電路13〇及一閘極驅動電 ，140。該電源電路；L10連接至該脈波調整電路13〇，該時 序控制電路120分別連接至該脈波調整電路130及該閘極 該間極驅動電路140連接至該脈波調整電 ㈣序控制電路12〇包括一第一輸出端ΐ2ΐ及一 140 第一接收鳊143及一第二輸出妓 端143連接至兮時岸批心 輸出^ 145 ’該第二接收 ㈣序控制電路m，該 201025258 第三輸出端145經由掃描線耦接至薄膜電晶體之閑極。 該脈波調整電路130包括一開關控制電路131、— • 一開關132、一第二開關133及一電阻134。該第—開 .132及該第二開關133均係NpN型場效應電晶體。該二I 控制電路131包括一反向器135。該反向器135之輪入 連接至該時序控制電路12〇之第一輸出端ΐ2ι。該第 關132之閘極連接至該反向器135之輸入端，源極連: 該電源電路110,没極連接至該閘極驅動電路14〇 — 接收端141。s亥第二開關133之閘極連接至該反向器1% 之輸出端，源極經由該電阻134接地，汲 ; 驅動電路140之第一接收端141。 至該閘極 電源電路110將一電源電壓提供給該脈波調 該時序控制電路120之第一輸出端121將一觸發= 提供給該開關控制電路m，控制該第一開關132與 一開關133交替導通。該時序控制電路120之第二輸出端 ❿一鐘訊號提供給該間極驅動電路14°，控制閘極驅 動電路140之驅動頻率。 3發電壓為高電平時，該第—開關132之閘 该回電平之觸發㈣，該第二開關133之間極接收 該反向器135轉換為你雷承^ ^ m Η射，料-為千觸發電M，則該第—開關132 幵—開關133關閉，該電源電路110輸出之電、为 電壓經由該第一開關132 出之電源 電路⑽之證一! 〉及極傳送至該閘極驅動 誃第一端141。當觸發電壓轉換為低電平時， X n 32之閘極接收該低電平之觸發電壓，該第二 201025258 開關133之閘極接收一籍由該反向器135轉換為高電平之 觸，電壓，則該第一開關132關閉，該第二開關133開啟， 先前傳送至閘極驅動電路14〇之電源電壓籍由電阻Η*連 接至地而放電’從而將電源電壓之準位進行削角而轉換為 -削角電壓提供給該閘極驅動㈣14〇，使得該閘極驅動 電路140之第三輸出端145輸出之閘極電壓轉換為一具 削角準位之閘極電壓。 ~ 當該液晶顯示装置之刷新頻率改變時’該時鐘訊號之 頻率及該觸發電壓之頻率相應改變，則該電源電壓之肖 時間改變H由於電阻之阻值未發生改變，而電源 壓籍由電阻放電之時間發生改變，從而導致閘極驅動電壓 經削角後之脈波末端之準位相對於上一刷新頻率閘極驅動 電[經削角後之脈波末端之準位發生改變’從而未達到相 ，之削角效果’使得液晶顯示裝置之顯示晝面存在閃爍現 【發明内容】[Technical Field] The present invention relates to a pulse wave adjusting circuit and a driving circuit using the pulse wave adjusting circuit. [Prior Art] The day-to-day display device has low radiation ..... -^ is widely used in displays, LCD TVs, mobile phones, and notebook computers, and has become the mainstream of displays. In the liquid crystal display device, the gate driving circuit is coupled to the gate of the thin film transistor by a scan line to control the turn-on and turn-off of the thin film transistor. However, due to the parasitic resistance and parasitic capacitance of the gate terminal of the thin film transistor, the display surface of the liquid crystal display device flickers when the gate terminal of the thin film transistor is turned off. In the prior art, a pulse wave adjusting circuit is usually added to the driving circuit of the liquid crystal display device to reduce the flicker phenomenon of the display surface. Please refer to FIG. 1, which is a block diagram of a prior art liquid crystal display device driving circuit. The driving circuit 1A includes a power supply circuit n〇, a timing control circuit 120, a pulse wave adjusting circuit 13A, and a gate driving circuit 140. The power supply circuit; L10 is connected to the pulse wave adjustment circuit 13A, the timing control circuit 120 is respectively connected to the pulse wave adjustment circuit 130 and the gate. The interlayer drive circuit 140 is connected to the pulse wave adjustment electric (four) sequence control circuit. 12〇 includes a first output terminal ΐ2ΐ and a 140 first receiving port 143 and a second output terminal 143 connected to the 兮 岸 bank core output 145 ′′ the second receiving (four) sequence control circuit m, the 201025258 third The output terminal 145 is coupled to the idle electrode of the thin film transistor via a scan line. The pulse wave adjusting circuit 130 includes a switch control circuit 131, a switch 132, a second switch 133, and a resistor 134. The first opening .132 and the second switch 133 are both NpN type field effect transistors. The two I control circuit 131 includes an inverter 135. The wheel of the inverter 135 is connected to the first output terminal 该2 of the timing control circuit 12A. The gate of the third switch 132 is connected to the input end of the inverter 135. The source is connected to the power supply circuit 110, and the gate is connected to the gate drive circuit 14A. The gate of the second switch 133 is connected to the output terminal of the inverter 1%, and the source is grounded via the resistor 134, and the first receiving end 141 of the driving circuit 140. To the gate power supply circuit 110, a power supply voltage is supplied to the pulse wave, and the first output terminal 121 of the timing control circuit 120 supplies a trigger= to the switch control circuit m to control the first switch 132 and a switch 133. Alternate conduction. The second output terminal of the timing control circuit 120 provides a clock signal to the interpole driving circuit 14° to control the driving frequency of the gate driving circuit 140. When the voltage of the third switch is high, the trigger of the first switch 132 is triggered by the level (4), and the pole of the second switch 133 receives the reverser 135 and converts it into your lightning force ^ ^ m ,, material - In the case of a thousand triggering electric M, the first switch 132 幵-switch 133 is turned off, and the power outputted by the power supply circuit 110 is the voltage of the power supply circuit (10) via the first switch 132. 〉 and the pole is transmitted to the gate The pole drive 誃 first end 141. When the trigger voltage is converted to a low level, the gate of X n 32 receives the trigger voltage of the low level, and the gate of the second 201025258 switch 133 receives a touch of the inverter 135 to a high level. When the voltage is applied, the first switch 132 is turned off, the second switch 133 is turned on, and the power supply voltage previously transmitted to the gate driving circuit 14 is discharged by the resistor Η* to the ground, thereby cutting the power supply voltage level. The conversion to the chamfering voltage is supplied to the gate driver (four) 14〇, so that the gate voltage outputted by the third output terminal 145 of the gate driving circuit 140 is converted into a gate voltage of a chamfering level. ~ When the refresh frequency of the liquid crystal display device changes, 'the frequency of the clock signal and the frequency of the trigger voltage change correspondingly, the time change of the power supply voltage H changes because the resistance value of the resistor does not change, and the power source is pressed by the resistor The time of discharge changes, and the level of the end of the pulse wave after the gate drive voltage is chamfered is relative to the last refresh frequency gate drive power [the level of the end of the pulse wave after the chamfer changes] Phase, the chamfering effect' causes the display surface of the liquid crystal display device to flicker. [Summary of the Invention]
有鑑於此’提供—種根據時鐘訊號頻率之改變而調整 放電電路之脈波調整電路實為必要。 提供一種使用上述脈波調整電路之液晶顯示 驅動電路亦為必要 一種脈波調整電路，其 開關及一放電電路。該第一 脈波調整電路之輸出端。該 電壓控制該第一開關與該放 包括一開關控制電路、一第一 開關及該放電電路均連接至該 開關控制電路接收並根據觸發 電電路交替導通。其中，該脈 201025258 電路進一步包括—頻率偵測電路，該頻率偵測電路 根據輸入時鐘訊號之頻率變化控制該放電電路 間。 双！訏 . 一種液晶顯示裝置驅動電路，其包括一時序控制 路、一脈波調整電路及一閘極驅動電路。該時序控^電路 將一時鐘訊號分別提供給該脈波調整電路及該閘極驅動電 路。該閘極驅動電路連接至該脈波調整電路。該脈波調敕 電路包括-開關控制電路、一第一開關及一放電電路°。ς 開關控制電路接收並根據觸發電壓以控制該第—開關與該 放電電路交替導通。其中，該脈波調整電路進—步包括一 頻率偵測電路，該頻率偵測電路用於偵測輸入時鐘訊號之 頻率並將一對應之控制訊號輸出至該放電電路。 與先前技術相比較，該液晶顯示裝置驅動電路係採用 該頻率偵測電路對該時序控制電路輸出之時鐘訊號頻率進 行偵測，並輸出一對應之控制訊號至該放電電路，該放電 ⑩電路對該電源電壓進行調整，使得高頻訊號與低頻=號時 輸出之閘極驅動電壓經削角後之脈波末端之準位相同，從 而降低液晶顯示晝面之閃爍現象。 【實施方式】 »月參閱圖2 ’係本發明液晶顯示裝置驅動電路第一實 施方式之不意圖。該驅動電路200包括一電源電路210、 一時序控制電路220、一脈波調整電路23〇及一閘極驅動 電路240。該電源電路210連接至該脈波調整電路23〇，該 時序控制電路220分別連接至該脈波調整電路23〇及該閘 201025258 極驅動電路240 ’該閘極驅動電路24〇連接至該脈波調整 電路230。該時序控制電路22〇包括一第—輸出端221及 • 一第二輸出端223。該閘極驅動電路24〇包括—第一接收 •端241、一第二接收端243及一第三輸出端245，該第二接 收端243連接至該時序控制電路22〇之第二輸出端⑵， 該第三輸出端245連接至負載。 該脈波調整電路230包括一開關控制電路231、一第 一開關232、一放電電路233及一頻率偵測電路234。該開 關控制電路231包括一反向器2311。該頻率偵測電路⑽ 包括一第一訊號輸入端2241及一第一訊號輸出端2343。 該放電電路包括一第二開關235 &一電阻值可變组件 236。該電阻值可變組件236包括一選擇開關237、一 電阻238及一第二電阻239。該選擇開關237包括一第二 訊號輸入端2371、一第二訊號輸出端2372、一第一 加及-第二接入端咖。該第一開關说及該第二開關 ❹23γ均係NPN型場效應電晶體。該第一電阻238之阻值大 於該第二電阻239之阻值。 該反向器2311之輸入端連接至該時序控制電路22〇 ，第一輸出端221。該第-開關232之閘極連接至該反向 器2311之輸入端，源極連接至該電源電路21〇，汲極 至該閘極驅動電路240之第—接收端241。該第二開關奶In view of this, it is necessary to adjust the pulse wave adjusting circuit of the discharge circuit in accordance with the change of the clock signal frequency. It is also necessary to provide a liquid crystal display driving circuit using the above-described pulse wave adjusting circuit, a pulse wave adjusting circuit, a switch thereof and a discharging circuit. The output of the first pulse wave adjustment circuit. The voltage control of the first switch and the discharge includes a switch control circuit, a first switch and the discharge circuit are both connected to the switch control circuit for receiving and alternately conducting according to the trigger circuit. The circuit of the 201025258 circuit further includes a frequency detecting circuit that controls the discharging circuit according to a frequency change of the input clock signal. double! A liquid crystal display device driving circuit comprising a timing control circuit, a pulse wave adjusting circuit and a gate driving circuit. The timing control circuit supplies a clock signal to the pulse wave adjusting circuit and the gate driving circuit, respectively. The gate drive circuit is coupled to the pulse wave adjustment circuit. The pulse wave tuning circuit includes a -switch control circuit, a first switch, and a discharge circuit.开关 The switch control circuit receives and controls the first switch to alternately conduct with the discharge circuit according to the trigger voltage. The pulse wave adjusting circuit further includes a frequency detecting circuit for detecting the frequency of the input clock signal and outputting a corresponding control signal to the discharging circuit. Compared with the prior art, the liquid crystal display device driving circuit uses the frequency detecting circuit to detect the clock signal frequency outputted by the timing control circuit, and outputs a corresponding control signal to the discharging circuit, and the discharging 10 circuit pair The power supply voltage is adjusted so that the high-frequency signal and the gate drive voltage outputted by the low-frequency signal are the same as the end of the pulse wave after the chamfering angle, thereby reducing the flicker phenomenon of the liquid crystal display surface. [Embodiment] The present invention is not intended to be the first embodiment of the liquid crystal display device driving circuit of the present invention. The driving circuit 200 includes a power supply circuit 210, a timing control circuit 220, a pulse wave adjusting circuit 23A, and a gate driving circuit 240. The power circuit 210 is connected to the pulse wave adjusting circuit 23, and the timing control circuit 220 is connected to the pulse wave adjusting circuit 23 and the gate 201025258 driving circuit 240'. The gate driving circuit 24 is connected to the pulse wave. The circuit 230 is adjusted. The timing control circuit 22 includes a first output terminal 221 and a second output terminal 223. The gate driving circuit 24A includes a first receiving end 241, a second receiving end 243 and a third output end 245. The second receiving end 243 is connected to the second output end of the timing control circuit 22 (2). The third output 245 is connected to the load. The pulse wave adjustment circuit 230 includes a switch control circuit 231, a first switch 232, a discharge circuit 233, and a frequency detection circuit 234. The switch control circuit 231 includes an inverter 2311. The frequency detecting circuit (10) includes a first signal input terminal 2241 and a first signal output terminal 2343. The discharge circuit includes a second switch 235 & a resistance variable component 236. The resistance variable component 236 includes a selection switch 237, a resistor 238, and a second resistor 239. The selection switch 237 includes a second signal input terminal 2371, a second signal output terminal 2372, a first plus-second access terminal. The first switch says that the second switch ❹23γ is an NPN type field effect transistor. The resistance of the first resistor 238 is greater than the resistance of the second resistor 239. The input of the inverter 2311 is connected to the timing control circuit 22A, the first output terminal 221. The gate of the first switch 232 is connected to the input terminal of the inverter 2311, and the source is connected to the power circuit 21, and the drain is connected to the first receiving end 241 of the gate driving circuit 240. The second switch milk
St接至該反向器23U之輸出端，源極連接至該選擇 =2二1號輸出端2372’没極連接至該閘極驅動 電路240之苐一接收端241。該頻率偵測電路之第一 11 201025258 訊號輸入端2341連接至該時序控制電路㈣之 223，第一訊號輸出端2343連 弟—輸出端 丈按主该選擇開關237之笛- 訊唬輸入端2371。該選擇開關237之第一選擇端 ：St is connected to the output terminal of the inverter 23U, and the source is connected to the selection = 2 and the 2nd output terminal 2372' is not connected to the first receiving end 241 of the gate driving circuit 240. The first 11 201025258 signal input end 2341 of the frequency detecting circuit is connected to the timing control circuit (4) 223, and the first signal output end 2343 is connected to the output terminal 2343. The flute-input input terminal 2371 of the main selection switch 237 is pressed. . The first selection of the selection switch 237:
由該第一電阻2 3 8接地，第二選擇 A 239接地。 、工田。亥第一電阻 ❹ 電源電路210將-電源電壓提供給該脈波調整 230。該時序控制電路㈣之第—輸出端221輸出—觸發電 壓至该開關控制電路231，控制該第一開關232與該放 電路233交替導通。該時序控制電路22〇之第二輪出端 將一時鐘訊號分別提供給該頻率偵測電路234及該閉極驅 動電路240,該時鐘訊號控制閘極驅動電路細之驅動頻 率，該頻率偵測電路234根據該時鐘訊號將一對應之控 訊號提供給該放電電路233。 時序控制電路220輸出之觸發電壓為高電平時，該第 一開關232之閘極接收一高電平之觸發電壓，該第二開關 235之閘極接收一籍由該反向器2311轉換為低電平之觸發 電壓，則該第一開關232開啟，該第二開關235關閉，該 電源電路210輸出之電源電壓籍由該第一開關232之源 極、汲極傳送至該閘極驅動電路24〇之第一接收端241。 時序控制電路220輸出之觸發電壓轉換為低電平時， 該第一開關232之閘極接收一低電平之觸發電壓，該第二 開關235之閘極接收一籍由該反向器2311轉換為高電平之 觸發電壓，則該第一開關232關閉，該第二開關235開啟， 先前傳送至該閘極驅動電路240之電源電壓籍由第一電阻 12 201025258 240之^ 接地而放電，使得提供給該閘極驅動雷 24〇之：源電壓之電壓準位被削角，從而該閘極驅動：路 24〇之第三輪出端245將一具有削 動電路 提供給負載。 半位之閘極電壓 施方：：閱圖3 ’係本發明液晶顯示裴置驅動電路第一 驅動訊號頻率圖°該頻率偵測電路234接: ㈣鐘訊號並對其進行偵測。# 接收 ❹ 該頻率偵測電路234輸出g 頻訊號時’ Ί'Ί心 4輸出一第一控制訊號至該選擇問奶 ’吏得該第二開關235之源極經由該第―電阻⑽: 而脾：使得該電阻值可變組件236轉換為第-電阻值，從 而將電源電壓之準位元U0削角轉換A ,., 從 ιπ之削角電壓。 角轉換為一脈波末端準位為 虽時鐘訊號轉換為低頻訊號時，該頻㈣測電路^ 二出-第二控制訊號至該選擇開關237，使得該第二開關 5之源極籍由該第二電阻239接地，即使得該電阻值可 ❹變組件236轉換為第二電阻值，從而將電源電虔之準位別 削角轉換為一脈波末端準位為U2之削角電壓。 根據公式I=U/R = Q/t，因電荷量q不變，為了保證 U=U0-U1=U0-U2，當時鐘訊號為高頻訊號時，即時間【較 小時，則設置電阻R較小；當時鐘訊號為低頻訊號時，即 夺間t較大日才，則5又置電阻r較大。因此，根據高頻訊號 與低頻訊號之間之頻率比值，設置第一電阻及第二電阻之 間之阻值比值，使得U1等於U2。 與先前技術相比較’該液晶顯示農置驅動電路2〇〇係 13 201025258 採用該頻率偵測電路234對該時序控制電路細 出端223輸出之時鐘訊號訊號進行❹i，並輸出二: ，號或者第二控制訊號至該選擇開關加，使二= .關235之源極於不同之刷新頻率下經由該第一電阻: 者第二電阻239接地，产而你π a Λ 8或 条接“ 員訊號與低頻訊號經削 角後之脈波末知準位相同。因此，當時鐘訊號之 :變時’籍由設置該電阻值可變組件之電阻值' ^ ❹^驅動電路輸出之間極驅動錢能夠達到相同之脈波末 1 閃爍現象。 心果’從而降低液晶顯示畫面之 月·"閱圓4係本發明液晶顯示裝置驅動電路二 之方框示意圖。該液晶顯示裝置驅動電路與第I 施方式液晶顯示裝置驅動電路， 貫 可變組件336包括複數電阻（奸、要t在於：該電阻值 扛％虹虹虛、 电阻（未“不）’該選擇開關337包 複數對應之選擇端（未標示），每一電阻一 端與地之間；該頻率伯測雷 ； i^擇 Φ之第二於出减對該時序控制電路32〇 ^ 2, 輪出之時鐘訊號進行偵測，對應不同頻 得號輸出對應之控制訊號至該選擇開關幻 仔该電阻值可變組件336轉換為不同之電阻值。 本發明液晶顯示I詈Φ々 所、十、^ 衮置驅動電路並不限於上述實施方式 .".，電路233中，該電阻值可變組件230亦可 應變阻器，該脈衝響應變阻器接收該頻率_ 路輸出之控制財u而調整為對應之電阻值。 综上所述，本發明確已符合發明專利之要件，爰依法 14 201025258 提出專利申請。惟，以上所述者僅為本發明之較佳實施方 式本發明之範圍並不以上述實施方式為⑯，舉凡熟悉本 .案技藝之人士援依本發明之精神所作之等效修飾或變化， .皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係一種先前技術液晶顯示裝置驅動電路之方框示 意圖。 圖2係本發明液晶顯示裝置驅動電路第一實施方式之 發方框示意圖。 圖3係本發明液晶顯示裝置驅動電路第一實施方式之 閘極驅動頻率示意圖。 圖4係本發明液晶顯示裝置驅動電路第二實施方式之 方框示意圖。 【主要元件符號說明】 液晶顯示裝置 200 > 300 電源電路 210 時序控制電路 220、320 第一輸出端 221 第二輸出端 223 、 323 脈波調整電路 230 開關控制電路 231 反向器 2311 第一開關 232 放電電路 233 第二開關 235 電阻值可變組件 236、336 選擇開關 237 > 337 第二訊號輸入端 2371 第一訊號輸出端 2372 第一接入端 2373 第二接入端 2374 第一電阻 238 第二電阻 239 頻率偵測電路 234 > 334 15 201025258 第一訊號輸入端 2241 第一訊號輸出端 2343 閘極驅動電路 240 第一接收端 241 第二接收端 243 第三輸出端 245 φ Ο 16The first resistor 2 3 8 is grounded, and the second selection A 239 is grounded. , Gong Tian. The first resistance ❹ power supply circuit 210 supplies a supply voltage to the pulse wave adjustment 230. The first output terminal 221 of the timing control circuit (4) outputs a trigger voltage to the switch control circuit 231 to control the first switch 232 and the discharge circuit 233 to be alternately turned on. The second round of the timing control circuit 22 provides a clock signal to the frequency detecting circuit 234 and the closed driving circuit 240. The clock signal controls the driving frequency of the gate driving circuit, and the frequency detecting The circuit 234 provides a corresponding control signal to the discharge circuit 233 according to the clock signal. When the trigger voltage outputted by the timing control circuit 220 is at a high level, the gate of the first switch 232 receives a high level trigger voltage, and the gate of the second switch 235 receives a low level converted by the inverter 2311. The first switch 232 is turned on, the second switch 235 is turned off, and the power voltage outputted by the power circuit 210 is transmitted to the gate driving circuit 24 by the source and the drain of the first switch 232. The first receiving end 241. When the trigger voltage outputted by the timing control circuit 220 is converted to a low level, the gate of the first switch 232 receives a low level trigger voltage, and the gate of the second switch 235 receives a switch converted by the inverter 2311 to When the trigger voltage of the high level is high, the first switch 232 is turned off, the second switch 235 is turned on, and the power supply voltage previously transmitted to the gate driving circuit 240 is discharged by the grounding of the first resistor 12 201025258 240, so that the voltage is provided. The gate is driven to the gate 24: the voltage level of the source voltage is chamfered so that the gate drive: the third wheel end 245 of the path 24 将 provides a shunt circuit to the load. The gate voltage of the half position :方:: Read Fig. 3 ′ is the first driving signal frequency diagram of the liquid crystal display device driving circuit of the present invention. The frequency detecting circuit 234 is connected to: (4) the clock signal and detecting it. #接收❹ When the frequency detecting circuit 234 outputs the g frequency signal, the 'Ί' core 4 outputs a first control signal to the selected breast milk, so that the source of the second switch 235 passes through the first resistance (10): Spleen: The resistance variable component 236 is converted to a first-resistance value, thereby converting the power supply voltage level U0 to a corner, and cutting the angular voltage from ιπ. The angle is converted to a pulse end level. When the clock signal is converted into a low frequency signal, the frequency (four) measuring circuit outputs a second control signal to the selection switch 237, so that the source of the second switch 5 is derived from the The second resistor 239 is grounded, that is, the resistance value variability component 236 is converted into a second resistance value, thereby converting the level of the power supply to a chamfering voltage of U2. According to the formula I=U/R = Q/t, because the charge amount q does not change, in order to ensure U=U0-U1=U0-U2, when the clock signal is a high frequency signal, that is, when the time is small, the resistance is set. R is small; when the clock signal is a low frequency signal, that is, if the clock signal is a large time, then the 5 is further set to have a large resistance r. Therefore, according to the frequency ratio between the high frequency signal and the low frequency signal, the resistance ratio between the first resistor and the second resistor is set such that U1 is equal to U2. Compared with the prior art, the liquid crystal display farm drive circuit 2 system 13 201025258 uses the frequency detection circuit 234 to output the clock signal signal outputted from the terminal 223 of the timing control circuit, and outputs the second:, or The second control signal is added to the selection switch so that the source of the second=off 235 is at a different refresh frequency via the first resistor: the second resistor 239 is grounded, and the π a Λ 8 or the strip is connected. The signal and the low-frequency signal are the same as the pulse wave after the chamfering angle. Therefore, when the clock signal is changed, the resistance value of the variable component of the resistance value is set to ^ ^ ❹ ^ between the drive circuit output and the pole drive The money can reach the same pulse end 1 flicker phenomenon. The heart fruit 'there is the moon of the liquid crystal display picture ·"The circle 4 is a block diagram of the liquid crystal display device drive circuit 2 of the present invention. The liquid crystal display device drive circuit and the The liquid crystal display device driving circuit of the embodiment, the variable component 336 includes a plurality of resistors, such as: the resistance value 扛% rainbow, the resistance (not "no"', the selection switch 337 corresponds to the complex number Selecting terminal (not labeled), between each end of the resistor and the ground; the frequency is measured by the lightning; the second is selected by Φ, and the clock signal is detected by the timing control circuit 32〇^2 Corresponding to the control signal corresponding to the output of the different frequency number to the selection switch, the resistance variable component 336 is converted into a different resistance value. The liquid crystal display of the present invention is not the driving circuit of the device The resistor value variable component 230 is also limited to the strain resistor, and the impulse response varistor receives the control value of the frequency_channel output and adjusts to the corresponding resistance value. The present invention has indeed met the requirements of the invention patent, and the patent application is filed according to the law. The above is only a preferred embodiment of the present invention. The scope of the present invention is not limited to the above embodiment. The equivalent modifications or variations made by those skilled in the art to the spirit of the present invention are intended to be included in the scope of the following claims. [FIG. 1 is a prior art liquid crystal display. Figure 2 is a block diagram showing the first embodiment of the liquid crystal display device driving circuit of the present invention. Figure 3 is a schematic view showing the gate driving frequency of the first embodiment of the liquid crystal display device driving circuit of the present invention. 4 is a block diagram showing a second embodiment of a liquid crystal display device driving circuit of the present invention. [Main element symbol description] Liquid crystal display device 200 > 300 Power supply circuit 210 Timing control circuit 220, 320 First output terminal 221 Second output terminal 223 323 pulse wave adjustment circuit 230 switch control circuit 231 inverter 2311 first switch 232 discharge circuit 233 second switch 235 resistance value variable component 236, 336 selection switch 237 > 337 second signal input terminal 2371 first signal output Terminal 2372 first access terminal 2373 second access terminal 2374 first resistor 238 second resistor 239 frequency detecting circuit 234 > 334 15 201025258 first signal input terminal 2241 first signal output terminal 2343 gate driving circuit 240 a receiving end 241 a second receiving end 243 a third output end 245 φ Ο 16