201013748 、 九、發明說明： 【發明所屬之技術領域】 本發明是關於一種對準標記，尤指一種利用離子佈值製 程所形成的對準標記及利用該對準標記所進行之缺陷檢測 方法。 【先前技術】 Q 半導體積體電路之製造中要經過很多處理步驟，例如微 影、蝕刻及沈積等。在這些步驟中，為了形成所想要之積 體電路元件，會使材料重疊或自現層移除。因此各種處理 程序中各層之適當對準具有其關鍵性。在目前之半導體製 程中大多是利用標示法來測量不同材料層間的對準精確 度，標示法係利用一後層上的一特定位置來與一前層上的 另一特定位置相比較，例如使後層上之一對準圖案重疊於 _ 前層上之另一對準圖案上方，進而利用此二對準圖案來量 測後層與前層間的對準精確度。每一個對準圖案中至少應 包含一個對準標記，因此藉由量測後層上之對準標記與前 層上之對準標記間的距離，即可獲得前層與後層之間的對 準偏移量。目前常見的對準標記包括盒内（box-in-box)光學 游標與條狀(bar-in-bar)光學游標。 然而，隨著積體電路技術的提昇與需求，其要求尺寸不 斷地縮小，而目前已發展出多層結構的晶片。目前在對多 201013748 钂 、 層結構的晶片進行測量與缺陷檢測時通常會採用多種類型 的缺陷檢測系統來進行多次的檢測。舉例來說，可先利用 一光學缺陷檢測系統來對晶圓進行檢測，然後再以一電子 缺陷檢測系統來檢測晶圓，之後再比對兩個系統依據檢測 結果而分別產生的缺陷圖譜(defect maP)。需注意的是’目 前在採用不同類型缺陷檢測系統來進行檢測時，由於座標 軸的不同，所產生的數值時常會有偏移（offset)的問題’造 ❹ 成材料層與材料層之間堆疊精度(overlap sensitivity)不佳。 【發明内容】 因此本發明之主要目的是提供一種對準標記及利用此 對準標記進行缺陷檢測的方法，以改良目前在進行缺陷檢 測時容易產生數值偏移的情況。 ❿ 本發明較佳實施例所揭露的缺陷檢測方法主要包含有 下列步驟。首先利用一第一缺陷檢測系統對一晶圓進行一 第一缺陷檢測步驟，晶圓上具有至少一對準標記，第〜缺 陷檢測步驟另包含對準該對準標記，且對準標記係為第— 缺fe檢測步驟之參考點（reference p〇int)。然後對晶圓進行 一製程，並接著利用一第二缺陷檢測系統對晶圓進行〜第 一缺陷檢測步驟’第二缺陷檢測步驟另包含對準該對準樑 • 记，且對準標記係為第二缺陷檢測步驟之參考點。 201013748 、=發明另—實施例是揭露—種用於缺陷檢測步驟的對 準己’主要包含有—半導體基底、-Ν型井設於半導體 =二一⑽雜區設於N型井中、一介電層設於該半 土&上並覆蓋N型井與P型摻雜區以及複數個導電插 塞設於介電層中並連接至P型摻雜區。其中，N型井較佳 為一 N-型井’而P型摻雜區則較佳為一 P+掺雜區。 Ο 參 【實施方式】 -月參第圖’第i圖為本發明較佳實施例之—對準標 ㈣Μ面示意圖°如第1圖所示，首先提供-半導體基 底42 Ϊ列如石夕曰曰圓。然後進行—離子佈植製程，將ν型 推質值入半導體基底42中，以形成井(N-We_。 接者進仃P離子佈植製程，將p型摻質值人所形成的& 3L井44中以於Ν·型井44中形成—深度較淺的p+摻雜區 46 〇 然後形成一介電層48在半導體基底42上並覆蓋Ν-型井 44與Ρ+摻雜區46。在本實施例中，介電層48可由氧化物、 Γ:=Τ或低介電常數村料等介電材料或其任意 Γ二二後形成一圖案化•層(圖未示)於介電層 纟圖案化光阻層當作遮罩進行—關製程， 示），並同時使各接觸洞貫穿介電層48而暴㈣p+#雜區 201013748 ' 46表面。隨後以丨賤鍍或電鐘的方式分別填入至少一金展材 料於各接觸洞中，以形成複數個接觸插塞（c〇ntact plug)50。在本實施例中，接觸插塞5〇可由鈦、氮化鈦、鎢 (W)、钽、氮化钽、鋁或鋼等金屬導體或其任意組合所構成。 至此即元成本發明較佳貫施例之一對準標記40。另外，依 據本發明之一實施例，接觸插塞5〇以上的金屬内連線部 分，包括接觸插塞50上的第一金屬層（圖未示）、第一接觸 © 洞（圖未示）、第二金屬層（圖未示）與第二接觸洞（圖未示）等 均可用來製作出所需的圖案。舉例來說，第一金屬層可為 對準標記的圖案，而第一接觸洞可為接觸插塞5〇的陣列， 此皆屬本發明所涵蓋的範圍。 需注意的是，本發明的對準標記40係與一般半導體電 晶體的製程相匹配。舉例來說，可在製作電晶體之 ❹ N-型井的時後同時在半導體基底42中形成對準標記4〇的 N-型井44,然後在製作PMOS電晶體之源極/汲極區域的 時候同時在半導體基底42中形成對準標記40的p+挣雜 區。接著於製作MOS電晶體之閘極結構的時候蝕刻並去除 對準標記區域的部分多晶矽層，然後再覆蓋M〇s電晶體之 層間介電層（inter-layer dielectric layer)的同時於N_型井44 與P+摻雜區46上沈積一介電層48。隨後於製作M〇s電 - 晶體區域的導線(contact)時一同形成對準標記區域的接觸 插塞50’且接觸插塞50會直接與P+摻雜區46電性連接， 201013748 ' 而形成一個上下導通的結構。另外，本發明的對準標記4〇 較佳是製作在晶圓的切割道上，但不侷限於這個位置，本 發明又可依據製程需求任意調整對準標記4〇所形成的位 置，例如，形成於晶片中的角落部位，此皆屬本發明所涵 盖的範圍。· 另外，在本實施例中，對準標記4〇的整體形狀會取決 ® 於PN接面的相對位置、舉例來說，本發明在製作N_型井 44及P+摻雜區46時，可控制離子佈植製程的佈植區域， 並同時調整N型與P型摻質所植入的相對位置與摻雜面 積’使PN接面呈現出不同的形狀。請參照第2圖至第$ 圖，第2圖至第5圖為本發明依據不同製程需求所完成對 準標記40之上視圖。如第2圖至第5圖所示，本發明在進 行PN接面的離子佈植製程時可依據相關之電晶體的離子 參 井製程與源極/汲極製程來變更光罩佈局以調整N塑與P裂 摻質的植入位置’使對準標記40呈現出滿足至少兩軸向的 特徵圖案，例如沿X軸與Y軸的兩長條圖案，或直接形戍 具有直角（right angle)的形狀，例如一 τ型對準標記52(如 第2圖所示）、一 L型對準標記54(如第3圖所示）或一十字 形對準標記56(如第4圖所示）。此外，對準標記可同時顯 示出包圍接觸插塞50陣列的型態，如第5圖所示之十字形 — 對準標記56。 201013748 在製作完成對準標記40後，可分別利用一電子缺陷檢 測系統以及一光學檢測系統對對準標記40檢測半導體的 相同製程層次或不同製程層次。其中，電子缺陷檢測系統 可包含一電子束缺陷檢測儀器（e-beam inspection apparatus， ΕΒΙ) ’而光學檢測系統則包含一由KLA-Tencor公司所提供 的光學檢測儀器。 在本實施例中採用電子束來進行缺陷檢測時，對準標記 40的確認是靠檢測機台藉由接觸插塞50與介電層48之間 的明暗對比來定義對準標記40的所在位置。由於本發明的 對準標記40是在半導體基底42中刻意形成一由N-型井44 與P+摻雜區46所構成的PN接面，因此在利用電子束進行 檢測時，所檢測過的區域會因PN接面之間的電壓反差 (voltage contrast)而呈現一發亮狀態（bright state)，使缺陷檢 測儀器在進行檢測時更容易辨識對準標記4〇的所在位置。 此外，本發明更可依據上述形成的對準標記來進行一缺 陷檢測方法。舉例來說，可先提供一晶圓，然後以上述製 程於晶圓的切割道上形成對準標記，接著利用一光學缺陷 檢測系統來對晶圓進行一第一缺陷檢測步驟，例如採用一 由KLA-Tencor公司所製作的光學檢測儀器來對此對準標 «己進行一對準步驟(aljgnment pr〇CeSS)，並依據對準的結果 形成一參考點（Γ6ί^η(^ P〇int)，然後再依據此參考點的座 201013748 j. 標值（coordinates)來產生一第一缺陷圖譜（defect map)。 接著於第一缺陷檢測步驟完成後，再對晶圓進行所需的 半導體製程，且進行的製程可包括由蝕刻製程、微影製程、 化學機械研磨製程、植入製程、清洗製程或材料形成製程 等所組成的群組。然後利用一電子缺陷檢測系統對晶圓進 行一第二缺陷檢測步驟，例如採用一電子束缺陷檢測儀器 & 來對對準標記進行另一對準步驟，並依據對準的結果形成 另一參考點。隨後依據參考點的座標值產生一第二缺陷圖 譜，並比對第一缺陷檢測步驟所產生的第一缺陷圖譜與第 二缺陷檢測步驟所產生的第二缺陷圖譜，找出相對應的缺 陷並予以分析。 換句話說，本發明的第一缺陷檢測步驟及第二缺陷檢測 步驟即是利用至少兩種不同類型的缺陷檢測儀器來對對準 ® 標記進行對準，而且兩個缺陷檢測步驟在進行對準時都會 採用相同的對準標記而具有相同的參考點，因此可大幅降 低相同缺陷在不同材料層之間座標的偏移。根據本發明之 較佳實施例，以此檢測方式進行缺陷檢測後可將材料層之 間的堆疊精度大幅提升至約略1微米。 另需注意的是，上述缺陷檢測方法是先以光學缺陷檢測 系統對晶圓中的對準標記進行對準而形成一參考點，然後 12 201013748 . 再以電子缺陷檢測系統對同一個對準標記進行檢測，但不 偈限於這個順序，本發明又可先以電子缺陷檢測系統來進 行第一次的缺陷檢測步驟，然後再用光學缺陷檢測系統來 進行第二缺陷檢測步驟，此皆屬本發明所涵蓋的範圍。 綜上所述，本發明主要是在一半導體基底中以離子佈 植形成N-型井與P+摻雜區，然後在各摻雜區上形成介電層 © 與貫穿介電層的導電插塞，使導電插塞直接接觸P+摻雜區 而形成一上、下導通的對準標記。由於對準標記的形狀會 取決於PN接面所形成的相對位置，因此本發明在製作N-型井及P+摻雜區時可同時調整N型與P型摻質植入的相對 位置與摻雜面積，使對準標記呈現出不同的形狀。 此外，本發明又可依據上述的對準標記來進行一缺陷 檢測步驟。依據本發明另一實施例，本發明又可先利用一 缺陷檢測系統來對準晶圓中的對準標記並使對準的結果形 成一參考點，然後利用另一缺陷檢測系統來對準同一個對 準標記，並形成另一參考點。由於兩個缺陷檢測步驟均是 以同一個對準標記來形成參考點，因此可大幅降低相同缺 陷在不同材料層之間座標的偏移。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 13 201013748 圍。 【圖式簡單說明】 第1圖為本發明較佳實施例之一對準標記之剖面示意圖。 第2圖為本發明之一 T型對準標記之上視圖。 第3圖為本發明之一 L型對準標記之上視圖。 第4圖為本發明之一十字形對準標記之上視圖。 Q 第5圖為本發明另一實施例之十字形對準標記之上視圖。 【主要元件符號說明】 10 材料層 12 材料層 20 重疊游標圖案 22 對準標記 24 對準標記、， 40 對準標記 42 半導體基底 44 N-型井 46 P+摻雜區 48 介電層 50 接觸插塞 52 T型對準標記 54 L型對準標記 56 十字形對準標記 14BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an alignment mark, and more particularly to an alignment mark formed by an ion cloth value process and a defect detection method using the same. [Prior Art] Q The semiconductor integrated circuit is subjected to many processing steps such as lithography, etching, and deposition. In these steps, in order to form the desired integrated circuit components, the material may be overlapped or removed from the active layer. Therefore, proper alignment of the various layers in various processing procedures is critical. In the current semiconductor manufacturing process, the marking method is mostly used to measure the alignment accuracy between different material layers. The marking method uses a specific position on a rear layer to compare with another specific position on a front layer, for example One of the alignment patterns on the back layer is overlaid on the other alignment pattern on the front layer, and the alignment pattern between the back layer and the front layer is measured by the two alignment patterns. At least one alignment mark should be included in each alignment pattern, so by measuring the distance between the alignment mark on the back layer and the alignment mark on the front layer, the pair between the front layer and the back layer can be obtained. Quasi-offset. Currently common alignment marks include box-in-box optical cursors and bar-in-bar optical cursors. However, with the advancement and demand of integrated circuit technology, the required size has been continuously reduced, and wafers of a multilayer structure have been developed. At present, many types of defect detection systems are often used for multiple measurements in the measurement and defect detection of a multi-layer 201013748 、, layer structure wafer. For example, an optical defect detection system can be used to detect the wafer, and then an electronic defect detection system is used to detect the wafer, and then the defect maps generated by the two systems according to the detection results are respectively compared. maP). It should be noted that 'currently when different types of defect detection systems are used for inspection, the resulting values often have an offset problem due to the difference of the coordinate axes. 'The stacking accuracy between the material layer and the material layer is made. (overlap sensitivity) is not good. SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide an alignment mark and a method of detecting a defect using the alignment mark to improve the case where a numerical offset is easily generated at the time of defect detection. The defect detecting method disclosed in the preferred embodiment of the present invention mainly includes the following steps. First, a first defect detecting step is performed on a wafer by using a first defect detecting system, the wafer has at least one alignment mark, and the first defect detecting step further comprises aligning the alignment mark, and the alignment mark is The first - the reference point of the fe detection step (reference p〇int). Then performing a process on the wafer, and then performing a first defect detection step on the wafer by using a second defect detection system. The second defect detection step further includes aligning the alignment beam and the alignment mark is The reference point of the second defect detection step. 201013748, = invention another - the embodiment is disclosed - the alignment for the defect detection step 'mainly contains - semiconductor substrate, - Ν type well is located in the semiconductor = two one (10) miscellaneous area is set in the N-type well, one An electric layer is disposed on the semi-soil & and covers the N-type well and the P-type doped region, and a plurality of conductive plugs are disposed in the dielectric layer and connected to the P-type doped region. Wherein, the N-type well is preferably an N-type well and the P-type doped region is preferably a P+ doped region.实施 【 实施 实施 实施 月 月 月 月 月 月 月 月 月 月 月 月 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° Round. Then, an ion implantation process is performed, and the ν-type kinetic value is entered into the semiconductor substrate 42 to form a well (N-We_. The entanglement of the P-ion implantation process, and the p-type dopant value is formed by the & A 3L well 44 is formed in the Ν-well 44 to form a shallower p+ doped region 46 〇 and then a dielectric layer 48 is formed over the semiconductor substrate 42 and covers the Ν-well 44 and the Ρ+ doped region 46. In this embodiment, the dielectric layer 48 may be formed of a dielectric material such as an oxide, ytterbium:=Τ or a low dielectric constant, or any other layer thereof to form a patterned layer (not shown). The electric layer 纟 patterned photoresist layer is used as a mask to perform a process, shown, and at the same time, each contact hole is penetrated through the dielectric layer 48 and violently (4) p+# miscellaneous area 201013748 '46 surface. At least one gold material is then filled into each contact hole by means of a ruthenium plating or an electric clock to form a plurality of contact plugs 50. In the present embodiment, the contact plug 5A may be composed of a metal conductor such as titanium, titanium nitride, tungsten (W), tantalum, tantalum nitride, aluminum or steel, or any combination thereof. Up to now, one of the preferred embodiments of the invention has been aligned with the indicia 40. In addition, according to an embodiment of the present invention, the metal interconnect portion of the contact plug 5〇 includes a first metal layer (not shown) on the contact plug 50, and a first contact hole (not shown). The second metal layer (not shown) and the second contact hole (not shown) can be used to create a desired pattern. For example, the first metal layer can be a pattern of alignment marks, and the first contact hole can be an array of contact plugs 5, which are within the scope of the present invention. It should be noted that the alignment mark 40 of the present invention is matched to the process of a general semiconductor transistor. For example, an N-type well 44 with an alignment mark 4〇 can be formed in the semiconductor substrate 42 simultaneously after the fabrication of the N-type well of the transistor, and then the source/drain region of the PMOS transistor can be fabricated. At the same time, the p+ doping region of the alignment mark 40 is formed in the semiconductor substrate 42 at the same time. Then, when the gate structure of the MOS transistor is fabricated, a portion of the polysilicon layer in the alignment mark region is etched and removed, and then the inter-layer dielectric layer of the M〇s transistor is covered while being in the N_ type. A dielectric layer 48 is deposited over well 44 and P+ doped region 46. Then, the contact plug 50' of the alignment mark region is formed together with the contact of the M〇s electro-crystal region, and the contact plug 50 is directly electrically connected to the P+ doping region 46, forming a The structure of the upper and lower conduction. In addition, the alignment mark 4 of the present invention is preferably fabricated on the scribe line of the wafer, but is not limited to this position, and the present invention can arbitrarily adjust the position formed by the alignment mark 4 , according to the process requirements, for example, forming In the corners of the wafer, this is within the scope of the present invention. In addition, in the present embodiment, the overall shape of the alignment mark 4〇 depends on the relative position of the PN junction. For example, when the N_type well 44 and the P+ doping area 46 are formed, the present invention can be used. Control the implantation area of the ion implantation process, and simultaneously adjust the relative position and doping area of the N-type and P-type dopants to make the PN junctions appear different shapes. Please refer to FIG. 2 to FIG. 2, and FIG. 2 to FIG. 5 are top views of the alignment mark 40 according to the different process requirements of the present invention. As shown in FIG. 2 to FIG. 5, the present invention can change the mask layout to adjust N according to the ion-well process and the source/drain process of the related transistor during the ion implantation process of the PN junction. The implantation location of the plastic and P-split dopants causes the alignment marks 40 to exhibit a characteristic pattern that satisfies at least two axial directions, such as two strip patterns along the X-axis and the Y-axis, or a direct shape having a right angle The shape, such as a τ type alignment mark 52 (as shown in Fig. 2), an L type alignment mark 54 (as shown in Fig. 3) or a cross-shaped alignment mark 56 (as shown in Fig. 4) ). In addition, the alignment marks can simultaneously show the pattern surrounding the array of contact plugs 50, such as the cross-shaped alignment mark 56 shown in FIG. 201013748 After the alignment mark 40 is completed, the same process hierarchy or different process levels of the semiconductor can be detected for the alignment mark 40 by an electronic defect detection system and an optical detection system, respectively. Among them, the electronic defect detecting system may include an e-beam inspection apparatus (ΕΒΙ), and the optical detecting system includes an optical detecting instrument provided by KLA-Tencor. When the electron beam is used for defect detection in this embodiment, the alignment mark 40 is confirmed by the detection machine to define the position of the alignment mark 40 by the contrast between the contact plug 50 and the dielectric layer 48. . Since the alignment mark 40 of the present invention deliberately forms a PN junction formed by the N-type well 44 and the P+ doping region 46 in the semiconductor substrate 42, the detected area is detected when the electron beam is used for detection. A bright state is exhibited due to the voltage contrast between the PN junctions, so that the defect detecting instrument can more easily recognize the position of the alignment mark 4 when detecting. Furthermore, the present invention can perform a defect detecting method based on the alignment marks formed as described above. For example, a wafer may be provided first, and then an alignment mark is formed on the scribe line of the wafer by the above process, and then an optical defect detection system is used to perform a first defect detection step on the wafer, for example, using a KLA. - An optical inspection instrument made by Tencor to perform an alignment step (aljgnment pr〇CeSS) and form a reference point (Γ6ί^η(^ P〇int) according to the result of the alignment. Then, according to the reference point of the reference point 201013748 j. coordinate to generate a first defect map (defect map). After the first defect detecting step is completed, the wafer is then subjected to the required semiconductor process, and The process may include a group consisting of an etching process, a lithography process, a CMP process, an implant process, a cleaning process, or a material forming process, and then a second defect is performed on the wafer using an electronic defect inspection system. The detecting step, for example, uses an electron beam defect detecting instrument & to perform another alignment step on the alignment mark, and forms another reference point according to the result of the alignment. Generating a second defect map according to the coordinate value of the reference point, and comparing the first defect map generated by the first defect detecting step with the second defect map generated by the second defect detecting step to find a corresponding defect and In other words, the first defect detecting step and the second defect detecting step of the present invention use at least two different types of defect detecting instruments to align the alignment marks, and the two defect detecting steps are performed. When the alignment is the same, the same alignment mark is used to have the same reference point, so that the offset of the coordinates of the same defect between different material layers can be greatly reduced. According to the preferred embodiment of the present invention, after the defect detection is performed by this detection method The stacking precision between the material layers can be greatly increased to about 1 micrometer. It should also be noted that the above defect detecting method first forms an alignment point by aligning the alignment marks in the wafer with the optical defect detecting system. Then 12 201013748 . The same alignment mark is detected by the electronic defect detection system, but it is not limited to this order. The first defect detection step can be performed first by the electronic defect detection system, and then the second defect detection step is performed by the optical defect detection system, which is within the scope covered by the present invention. The invention mainly comprises forming an N-type well and a P+ doped region by ion implantation in a semiconductor substrate, and then forming a dielectric layer on each doped region and a conductive plug penetrating through the dielectric layer, so that the conductive plug is directly Contacting the P+ doped region to form an upper and lower conductive alignment mark. Since the shape of the alignment mark depends on the relative position formed by the PN junction, the present invention is used in the fabrication of the N-type well and the P+ doped region. The relative positions and doping areas of the N-type and P-type dopant implants can be adjusted simultaneously so that the alignment marks exhibit different shapes. Furthermore, the present invention can perform a defect detecting step in accordance with the alignment mark described above. According to another embodiment of the present invention, the present invention may first utilize a defect detection system to align the alignment marks in the wafer and form the alignment result as a reference point, and then use another defect detection system to align with the same One alignment mark and another reference point is formed. Since both defect detection steps are formed with the same alignment mark to form a reference point, the offset of the same defect between different material layers can be greatly reduced. The above description is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the scope of the present invention should be covered by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing an alignment mark of a preferred embodiment of the present invention. Figure 2 is a top view of a T-shaped alignment mark of the present invention. Figure 3 is a top view of one of the L-shaped alignment marks of the present invention. Figure 4 is a top view of one of the cross-shaped alignment marks of the present invention. Q Fig. 5 is a top view of a cross-shaped alignment mark according to another embodiment of the present invention. [Main component symbol description] 10 material layer 12 material layer 20 overlapping cursor pattern 22 alignment mark 24 alignment mark, 40 alignment mark 42 semiconductor substrate 44 N-type well 46 P+ doped region 48 dielectric layer 50 contact plug Plug 52 T-shaped alignment mark 54 L-shaped alignment mark 56 Cross-shaped alignment mark 14