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TW201003915A - Transistor device - Google Patents

Transistor device Download PDF

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Publication number
TW201003915A
TW201003915A TW097125941A TW97125941A TW201003915A TW 201003915 A TW201003915 A TW 201003915A TW 097125941 A TW097125941 A TW 097125941A TW 97125941 A TW97125941 A TW 97125941A TW 201003915 A TW201003915 A TW 201003915A
Authority
TW
Taiwan
Prior art keywords
agon agon
layer
gate
agon
amorphous phase
Prior art date
Application number
TW097125941A
Other languages
English (en)
Inventor
Tsai-Yu Huang
Shin-Yu Nieh
Hui-Lan Chang
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Priority to TW097125941A priority Critical patent/TW201003915A/zh
Priority to US12/241,096 priority patent/US20100006954A1/en
Publication of TW201003915A publication Critical patent/TW201003915A/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H01L21/02148—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing hafnium, e.g. HfSiOx or HfSiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
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    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

201003915 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體元件技術’特別是有關於—種金氧半 導體場效電晶體元件以及其製作方法。 【先前技術】 〆 隨著CMOS元件尺寸持續微縮，傳統為達到最佳化目 的而採降低閘極介電層（如二氧化矽層）厚度之做法，已面 臨到因電子穿遂效應（tunneling effect)所導致渴電流過大的 物理限制。 ’ 為了有效延展邏輯元件的世代演進，高介電常數材 料’例如金屬氧化物’已成㈣代傳統二氧化石夕:或氮氧 化石夕層作為閘極介電層的熱門選項。高介電常數材料能有 效降低物理極限厚度，並且在相同的等效氧化厚度 (:qUiValentoxidethickness，E〇T)下，降低漏電流，並達成 等效電容，以控制通道開關。 口夂自5亥項技藝者所週知，合悝赏屬氧化物高介電常 =中魏給氧化合物(腿〇)為目前較常被業界用來當作間 ,1電層的同”電常數材料之―’而考量到載子通道遷移- 201003915 (mobility)紐，作為閘極介 目前，要 )_，《絲響轉在非晶 ==氧化細轉麵締㈣，倾使細#超過 :上的轉含量’才能確保魏錢化合物在後 從原本_糾、剛爾練雖m，不會 心被轉化成結晶(crystalline)狀態。 一二1晶相的石夕酸給氧化合物时電常數作〜功仍然不夠 冋。在某些應㈣合t，可能要求祕介電層的介電常數超⑽ 以上’甚至30以上’而以非晶相⑽酸給氧化合物作為間極介 電層顯然無法提供如此高的介電常數。 【發明内容】 本發明之主要目的在提供—種改良之電晶體元件，以解決先 前技藝之不足。 根據一杈佳貫施例，本發明提供一種電晶體元件，包含有一 半導體基底；-源極彳鎌區域以及—祕摻腿域，設於該半導 體基底U極通道區域，於該祕伽區域與舰極換雜區 域之間；以及結構，位於該閘極通道區域的正上方，其中 該閘極結構包含有-非晶相表面層、_結晶態的金屬氧化物問極 介電層，以及一閘極導電層。 201003915 根據另一較佳貫施例，本發明提供— 一丰莫雜a念· 裡电日日肢凡件，包含有 •fv體基底’-源極摻雜區域以及 導於美;^ . ㈣域’設於該半 摻雜 方，其 區’ 域，於該源極摻雜區域與該沒極 間’以及一閘極結構，位於該閘極通道區域的正上， 中該閘極結構包含有一非a彳 々 此3有非日日相表面層、—金屬氧化物間極介電 ^以及-導電層，其中該金屬氧化物_介電層包括 晶相⑽酸給氧化合物層以及—結晶態频給氧化合物層。 為讓本發明之上述目的、特徵、和優點能更明_懂，下文 特舉較佳實施方式，並配合所附圖式，作詳細說明如下。秋而如 下之較佳實施方式與圖式僅供參考與說日賴，並_本 加以限制去。 【實施方式】 Μ參閱第1圖’其為依據本發明第—較佳實施例所繪示的金 氧半導體場效電晶紅件丨的剖面示意圖。如第〗圖所示，金氧 半導體場效電㈣元件丨包含有—半導縣底1Q，例如雜底， 在半導體基底10中形成有1極摻_域12以及―姻參雜區 f Η在源極摻雜區域12與及極摻雜區域M之間為間極通道區 V 16。金軋半導體場效電晶體元件1另包含有-閘極結構20,位 於閘極通道區域16的正上方。 201003915 根據本發明第-較佳實施例1極結構2q包含有—非 ；^7h0US mterfacial layer)22' "層及―間極導電層26。其中，難導電層26包括全屬， 例錢化鈦或氮化组，或者多轉。非晶相表面㈣包括=相 -5tf，m f'KiUt"I(UVRF)A^^^M^ :T=:，非晶相表面層22亦可以包括摻雜氮的 石夕乳層，車父仏者，為利用分耦式電聚氣化(decoupled咖邮 祕t_，DP聰錢行細魏層。形成㈣ 方法可採原子層沈積(ALD)法或者紫外線射頻(UVRF)驗勺 據本發明第一較佳實施例，非晶相表面層22的厚度小於、 (angstrom) 〇 夭 u 根據本發明第-較佳實施例，結晶態的金屬氧化 ^包括尉目為衫_琴nal)或立蝴· 合物，其化學式為Hfl.xSlx〇y，其中χ介於_至㈣之 據本發明第-較佳實施例，結晶態魏給氧化合物的 二 於70%至9G%原子量百分比之間，而料 里、〜丨 量百分比之間，物_ 5埃錢㈣。;根；^ 3〇%原: 佳實施例，結晶態频給氧化合_介電常數可錢交 據本發明，金屬氧化物閘極介電層24亦可以是艮 紹可以稀土元素(聰earth eiem㈣如竭元素所取代。y /、中 8 201003915 牛例來况，可以進行複數次的ALD循環，先在非晶相表祕 上沈積II化給(每次的ALD循環沈積α6 _氮化給）。前粉 積亂化給的每次ALD彳轉包括町四個基本步驟：⑴於反應哭匕 中通入含給的有機金屬前驅物氣體，如TEMA_Hf， : =娜基材表面彻後以惰性氣體，例如氯氣，= ^内多餘的有機金屬前驅物；⑶織於反應器中通人臭氧 臭乳與吸附在基材表面的_金屬前驅物反應；以 性氣體，例如氬氣，進行吹除。 ^ ,後’再進行複數次的ALD循環，在氮化铪上沈積矽原子， 其早久ALD循環同樣包括四個步驟⑴於反應器中通入含石夕的有 機金屬前驅物氧髀，上<3 ^ , A , 札體如3-DMAS或4-DMAS ,先使有機金屬前驅 附在絲細；（2)織以'祕㈣，勤氬氣，吹除反應器 =夕餘的有機金屬前驅物；⑶然後於反應时通人臭氧，使臭氧 -制在基材表_有機金屬前驅物反應；以及⑷再:欠以惰性氣 體，例如氬氣，進行吹除。 、 極介二:24除'了广迷的原子層沈積法之外’本發明金屬氧化物閘 广亦可以_物理氣相沈積 (physical vapor deposition, 、、）法、濺鍍法或者化學氣相沈 積(chemical vapor deposition, CVD) 有機至屬化孥氣相沈積(metal organic CVD，MOCVD)法等其它 方法形成。 、 201003915 曰本^月由於矽酸铪氧化合物的铪含量約介於7〇%至9〇%原子 里百刀比之間而㊉含量約介於抓至遍原子量百分比之間，因 ，通吊'彻後‘的熱製程中，例如活化汲極源極摻質的快速熱製 私_>) ’就足以將非晶相的石夕酸給氧化合物轉化成晶相為正方晶 (g a)或立方曰曰(cubic)的石夕酸給氧化合物。但亦可以額外增加 一道熱製程回火步驟，_靴至麵。〇的高溫，回火時間約 30秒’可確保非晶相的石夕酸給氧化合物均轉化成晶相為正方晶 (tetragonal)或立方晶㈣⑹的魏铪氧化合物。 ^ :月參閱第2圖’其為依據本發明第二較佳實施例所繪示的金 氧半$體場效电晶體元件la的剖面示意圖。如第2圖所示，金氧 半導體場效電晶體元件la包含有—料體基底⑴，例姆基底， 在半‘體基底1Q中形成有―源極換雜區域U以及—祕推雜區 域14，在源極捧雜區域12航極摻雜區域14之間為開極通道區 域。金軋半導體場效電晶體元件la另包含有一閘極結構施， 位於閘極通道區域16的正上方。 根據本發明第二較佳實施例，閘極結構漁包含有—非晶相 发面4 22金屬氧化物閘極介電層124,以及一閑極導電層％。 :中’間極導電層26包括金屬，例如氮化鈦或氮化包，或者多晶 夕非晶相表面層22包括非晶相二氧化石夕層，較佳者 外線射頻(UVRF)氧化法所形成的高品質二氧化石夕層。此外，非晶 相表面層22亦可以包括摻減的魏層，較佳者，為利用分搞式 10 201003915 =氮化(DPN)製成進行氮化的魏層。形成非晶相表面層22的 /可減子層沈積(ALD)法或者紫外線射頻(υγ剛氧化法。 根據本發明第二較佳實施例，金屬氧化物閘極介電層m包 _酸給氧化合物層1細及晶相為正方晶(她ag〇nal) =方^lc)的結曰曰曰態石夕酸給氧化合物層賤，其化學式為 HUlxOy，且X介於〇 〇5至 ,MO之間。其中’非晶相的石夕酸給氧 θ 含量高於5G%軒量百分比，例如介於50%至 60从子夏百分比，而結晶態频給氧化合物_含量約介 至㈣軒量砂以間，齡執倏观至9G%料量百分。 比之間。
以上所述縣本發日狀祕實關，歧树”請專利範 所做之均替化與修挪，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第i ^依，本發明第—較佳實施例所緣示的金氧半導體場效電 日日體凡件的剖面示意圖。 第2 侧：卿__㈣錢轉體場效電 日日體7〇件的剖面示意圖。 【主要元件符號說明】 201003915 1 金氧半導體場效電晶體元件 la 金乳半導體場效電晶體元件 10 半導體基底 12 源極摻雜區域 14 汲極摻雜區域 16 閘極通道區域 20 閘極結構 20a 閘極結構 22 非晶相表面層 24 結晶態的金屬氧化物閘極介電層 26 閘極導電層 124 金屬氧化物閘極介電層 124a非晶相的矽酸铪氧化合物層 124b結晶態矽酸铪氧化合物層
12

Claims (1)

  1. 201003915 十、申請專利範圍： 1. 一種電晶體元件，包含有： 一半導體基底； 一源極推雜區域以及一汲極摻雜區域，設於該半導體基底中； 一閘極通道區域，於該源極摻雜區域與該汲極摻雜區域之間 之該半導體基底中；以及 一閘極結構，位於該閘極通道區域的正上方，其中該閘極結 構依序於。彡半‘體基底上具有__非晶相表面廣、—結晶態的金屬 氧化物閘極介電層，以及一閘極導電層。 2. 如申請專纖圍第〗項所述之電晶體元件，其巾轉晶相表面 層包括非晶相二氧化矽層。 3.如申請專利範圍第！或2項所狀電晶體元件，其巾該非晶 表面層包括摻雜氮的矽氧層。 阳目 4·如申請專利範圍第1 層的厚度小於5埃。 項所述之電晶體元件，其中該非晶相表面 5·如申請專利範_丨項所狀電晶體元件，其巾_曰… 屬氧化物閘極介電層包括曰相盔不古曰“ + '、'〇日日恕的金 合物。 曰曰相為正方曰曰(她agona⑽石夕酸給氣化 13 201003915 屬1項所述之電晶體元件，其找結晶態的金 物_介電層包括純社抑氧化合物。 第5 _輯之編元件，其中該結晶態 羊σ物的铪含量約介於70%至90%原子量百分比之 曰’而石夕含量約介於5%至3〇%原子量百分比之間。 8,如申請專利範圍第1項所述之電晶體元件，其中該έ士曰能的全 屬氧化物_介娜驗於5埃㈣㈣'的4 ,種電晶體元件，包含有： 一半導體基底； 源極摻雜區域以及一汲極摻雜區域，設於該半導體基底中； ^閘極通道區域，於該源極摻雜區域與該汲極摻雜區域之間 之該半導體基底中；以及 —閘極結構，位於該閘極通道區域的正上方，其中該閘極結 構^序於該基底上具有一非晶相表面層、—金屬氧化物閘 極介電層’以及―閘極導電廣’其中該金屬氧化物閘極介電層依 ^於4非晶相表面層上具有一非晶相㈣祕氧化合物層以及一 結晶態矽酸銓氧化合物層。 曰 η·如申請專概圍第9項所述之電晶體元件，其中該結晶態石夕酸 201003915 給氧化合物層的晶相為正方晶(tetragonal)。 11 ·如申請專利範圍第9項所述之電晶體元件，其中該結晶態矽酸 給氧化合物層的晶相為立方晶(cubic)。 12.如申請專利範圍第9項所述之電晶體元件，其中該結晶態矽酸 铪氧化合物的給含量約介於70%至9〇%原子量百分比之間，而矽 : 含量約介於5%至30%原子量百分比之間。 13 ·如申明專利範圍第9項所述之電晶體元件，其中該非晶相的石夕 酸铪氧化合物層的矽含量高於5〇%原子量百分比。 14·如申請專利範圍第9項所述之電晶體元件，其中該非晶相表面 層包括非晶相二氧化硬層。
    層包括摻雜氮的矽氧層。 元件，其中該非晶相表面 電晶體元件，其中該非晶相表面 16·如申請專利範圍第9項所述之 層的厚度小於5埃。 17.如申請專利範圍第9〕 間極介電層厚度約介於5 項所述之電晶體元件， >埃至90埃之間。 其中該金屬氡化物
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