TW201003880A - Semiconductor device comprising a chip internal electrical test structure allowing electrical measurements during the fabrication process - Google Patents

Abstract

A test structure or a circuit element acting temporarily as a test structure may be provided within the die region of sophisticated semiconductor devices, while probe pads may be located in the frame in order to not unduly consume valuable die area. The electrical connection between the test structure and the probe pads may be established by a conductive path including a buried portion, which extends from the die region into the frame below a die seal, thereby maintaining the electrical and mechanical characteristics of the die seal. Hence, enhanced availability of electrical measurement data and superior authenticity of the data may be accomplished, wherein the measurement data may be obtained during the production process.

Description

201003880 VI. Description of the Invention: [Technical Field of the Invention] In general, the present disclosure relates to the field of manufacturing integrated circuits, and more particularly to monitoring electrical measurements of semiconductor devices according to corresponding electrical test structures. data. [Prior Art] Today's global market forces a large number of products to be manufactured to provide high quality products at low prices. It is therefore important to improve yield and process efficiency to minimize production costs. This situation is particularly true in the field of semiconductor manufacturing because it is important to combine cutting-edge technology with mass production techniques in this area. Therefore, the goal of semiconductor manufacturers is to reduce the consumption of raw materials and consumables, while improving the use of process tools, because in modern semiconductor devices, extremely expensive equipment is required and this is a major part of the total production cost. As a result, high tool usage combined with high product yield (i.e., a high ratio of good devices to defective devices) results in increased profits. Integrated circuits are typically fabricated in automated or semi-automated equipment whereby the apparatus is completed by a large number of processes and method steps. The number and type of process steps and method steps that a semiconductor device must pass are based on the particular semiconductor device to be fabricated. A conventional fabrication process for an integrated circuit can include a plurality of optical lithography steps to image a circuit pattern for a particular device layer in a photoresist layer, the photoresist layer then being patterned to form a photoresist mask, the light The mask is used in a further process of forming device features (device 4 946S1 201003880 feature) in a device layer under consideration, such as by etch, implant, deposit, polish, and anneal processes. Thus, one layer after the other, a plurality of process steps are performed in accordance with a particular optical lithography mask that is applied to various layers of a particular device. For example, a complex CPU requires hundreds of process steps, each of which must be completed within a specific process margin to achieve the device specifications considered. Because many of these processes are critical, multiple method steps must be implemented to effectively monitor and control the manufacturing process. A typical method process can include measuring the layer thickness, determining the size of key features (such as the gate length of the transistor), measuring the dopant concentration curve, the number, size, and type of defects, and electrical characteristics (such as transistor drive current, The threshold voltage (that is, the voltage at which the conductive path is formed in the channel region of the field effect transistor), the mutual conductance (that is, the change in the driving current with the gate voltage), and the like. Because of the major process margins, the many metrology processes and actual manufacturing processes are specifically designed for the device under consideration and require specific parameters to be set for the appropriate metrology and process tools. In semiconductor devices, a plurality of different product types are usually manufactured at the same time, such as memory chips of different design and storage capabilities, CPUs of different design and operating speeds, etc., which are used in the production line for manufacturing special application 1C (ASIC). The number of different product types can even reach one hundred and more. Because different product types may require specific manufacturing processes and different masks for optical lithography, various process tools may be required (such as deposition tools, etching tools, implant tools, chemical mechanical polishing (CMP)). Specific settings in tools, metrics, and so on. In conclusion, in the manufacturing environment, a number of different tools 94681 201003880 parameter settings and product types may be encountered at the same time, which also produces a large amount of measurement data, because the measurement data is typically based on product type, manufacturing process details, etc. To classify. Therefore, even for the same type of process tool, a large number of different process recipes may be required, wherein the process recipes must be applied to the process tools when the corresponding product types are to be processed in each tool. However, due to rapid product changes and the highly variable processes involved, the sequence of process recipes that are applied to the process and metrology tools, or to the functionally integrated equipment group, and the formulation itself, may have to be changed frequently. . As a result, tool performance in terms of productivity and throughput significantly affects the total production cost of individual devices, so they are very critical manufacturing parameters. Therefore, great efforts have been made to monitor manufacturing processes in a semiconductor device for yield-affecting processes or process sequences in order to reduce improper handling of defective devices and identify them in manufacturing processes and process tools. . For example, in many stages of the manufacturing process, an inspection step is performed to monitor the status of the device. Moreover, other measurement data can be generated to control various processes, where the measurement data can be used as feed forward and/or feedback data. The measurement data used to control the manufacturing process (such as optical lithography process, etc.) can be obtained by a dedicated structure, and if the corresponding area consumption of these structures can be adapted to the overall design criteria of the circuit layout under consideration, then the dedicated The structure can be located within the grain area. In other cases, the test structure can generally be placed in the area outside the actual grain area, which can also be referred to as a frame. When separating individual grain areas, the frame 6 94681 201003880 can be used to cut the substrate. . During the complicated manufacturing sequence for completing a semiconductor device (for example, a CPU or the like), a large amount of measurement data may be generated by, for example, inspection tools or the like due to a large number of complicated processes, and it may be difficult to evaluate each other's dependencies, A factory target may usually be established for certain processes or sequences, where the target is assumed to provide a process window to obtain the desired electrical behavior of the completed device. . That is to say, it is possible to monitor and control according to the respective inline measurement data: complex individual processes or related sequences, so that the corresponding process results can be maintained within a specific process margin, which can be considered in turn according to the consideration The final electrical performance of the product is determined. As a result, in view of the enhanced overall process control and the various processes appropriately calibrated according to the final electrical performance, the electrical test 1 can be generated according to a dedicated test structure which can be combined at a very later stage of manufacture. A suitable probe pad formed in the metallization system is disposed in the frame region. These electrical test structures may include suitable circuit components such as transistors, conductive lines, capacitors, etc., and such circuit components may be suitably coupled to the probe pads to allow for dedicated measurement strategies for evaluation in the test structure. The electrical performance of the various circuit components can then be correlated to the performance of the circuit components in the continuous die region. These electrical measurements may include the resistance of the conductive structure, the threshold voltage of the transistor, the drive current capability of the transistor, the leakage current, etc., and the large number of processes involved may affect the electrical characteristics. Because these electrical measurements may be obtained at a very later stage of the overall process, there is typically a significant delay in the actual process in which the corresponding test has been formed, thus requiring complex pre-study considerations. There is a significant delay, which can even be in the range of weeks for a typical manufacturing environment. In addition, if the incident energy occurs during the period between the transmission of the critical process and the associated electrical measurement data, then the corresponding electrical 闵屮, 止士六沭立J 里贝τ叶甲It is likely that there will be fewer desirable performance characteristics. The cadaver cloth will now be described with reference to the first to fourth lb diagrams. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The first la_ schematic manner shows that the semiconductor device_upper device UK) includes a grain region]1〇, == a region of the set, wherein the circuit components and the two-generators are formed according to design criteria. In order to establish a functional integrated circuit. Thus, the term "m;; contains any material that can be used to provide a region of a particular region," which is understood to be energy, such as substrate material, semi-guided t-genus 4: lack of knowledge; A large conductor wafer or the like of the semiconductor device 100 is formed, in which individual die regions (4) (4) = the size of the die region and the size of the substrate. The crystal 2 2 = defined at the boundary between two adjacent regions, which includes a frame or a frame region, and the object can represent the manufacturing stage of the very later stage of the 94681 8 201003880 before encapsulating the individual grain regions m The typical area can be selected as the frame area]. Knife cutting area. Therefore, during the body material, the secret dimensions of the respective materials are provided to facilitate the use of the cutting carrier for the carrier material. * The force is not excessive in the conductor device, and the grain seal is provided. And the second is to separate the actual grain area. The μ day grain seal 120 can be combined with the frame 13〇, and the 廿α grain area 110 is electrically and mechanically finished and can provide the crystal 120. It can be formed in a semiconductor package; the "grain seal" is substantially continuous in the metallization system of the grain region 4, in the "wall" of the copper, the wall is provided by 4: The barrier, wherein the defects may, for example, be expressed relative to mechanical defects (especially during separation of respective crystals:: semiconductor device 10 during the cutting of the semiconductor device 100), for example, in the frame region U0 The material is triggered. The sensitive dielectric village measurement data of the system is used to evaluate the electrical performance of the device located in the die = body device 1 (8). For this purpose, the expected @ ί of the circuit in A5 10 obtains one or more Electrical test structure〗 4 The electrical measurement data of 0 can be combined with the respective probe pads 141A, 141, and the frame is located in the frame region 130 and is sized so that the external electrical obliques 141A, 141B can be adapted by the pads 141A, 141B. Appropriate access is required. That is to say, the probes are simultaneously contacted by the respective probe pads for external probes, and the double 曰 σ is determined by the configuration of 4 士. Twist, two-point measurement of the corresponding feature of '14Q, then two probe pads 141A ° 40 and must implement a simple 41 which may be sufficient, however, 94λ〇ι 9 201003880 in other cases, in order to obtain the desired For information, it may be necessary to provide three or more probe pads. It should also be appreciated that a plurality of electrical test structures 140 in conjunction with associated probe pads may be disposed within region 130. It should be further noted that including correlation The area 142 of each test feature of the dimensions of the probe pads 141A, 141B is not to scale, as the area typically required for testing the features 142 is significantly greater than the area consumed by the probe pads 141A, 141B. Smaller. So, by measuring The test structure 140 is positioned in the frame region 130 and may not waste useful wafer area within the die region 110. Figure lb shows in schematic form a portion of the semiconductor device 100 along section lb as shown in FIG. Cross-sectional view. As shown, semiconductor device 100 includes a substrate 101 that can represent any suitable carrier material (e.g., semiconductor material, dielectric material, etc.) over which a semiconductor layer 102, such as a germanium-based layer, is formed. Within or over the semiconductor layer 102, a plurality of circuit elements 151 can be formed within the die region 110, wherein the circuit component 151 can thus represent the desired desired to achieve within the die region 110. A semiconductor component of a functional circuit. Further, test features 142 formed, for example, in the form of circuit elements having the same or similar composition as circuit elements 151 may be disposed in frame 130 in and on semiconductor layer 102. For example, test structure 140 can include one or more transistor components, and the characteristics of the transistor components can be evaluated to determine the electrical performance of circuit component 151 in die region 110. The semiconductor layer 102 can be combined with any of the components formed over the layer 102 (eg, when provided in the form of a transistor element, the gate for the circuit component 151) 0 946S1 201003880 =) can be in the die area 1I0 and in the frame area i3 Set the level (d(10)eleveI) I5G. The device 151' in the device level 15 且 and likewise the test feature 142 can be closed by the contact layer 170: the contact layer (7) can be suitable for the appropriate dielectric material 2: '虱 矽, 二And so on), wherein each of the contact readings 171A, (10) and mc can be formed so as to be electrically connected to the metallization system from the device level 15 ', ', in the metallization layer, The circuit component (5) in the device level 15G and the overall electrical "wire connection" for testing the feature U2 may not be built into the device level 15" because the electrical connections typically required for the circuit architecture are considered. For example, the contact θA member 171A can represent the contact elements of each t in the die region 11(), and the contact element (10) can represent the contact element connecting the die seal to the U0 layer, wherein the contact device p1B can The continuous metal-containing region is provided in the form of a region. Similarly, the contact member nic can establish an electrical connection between the test feature (4) and the metallization system 160 in the frame region 13A. The metallization system 160 can include a plurality of gold The layers 6 〇 a, 160 B, 160 C, depending on the overall complexity of the semiconductor device 1 . The metallization layers 160 C in the die region 110 and the frame region 13 可以 may include metal lines 16 and/ Or the through hole 162, the metal wire (6) and the through hole 162 may be electrically connected to two adjacent metallization layers. On the other hand, the die seal 120 may include a "metal wire" 161 instead of the through hole 62' This provides a substantially continuous metal wall around the area]. Further, as shown in Figure lb, the uppermost metallization layer]6〇c may include

JJ 9468] 201003880 The metallization layer of the metallization layer in the frame area 丨3 Α 141Α, 141Β. Detecting 142. In general, semiconductor devices exemplified in the following processes can be used. First, you can root and map order (as explained above) in the device level 15〇 == manufacturing and measuring the winning material 7L pieces 151 ^ ^ \ ' in the order of clothing can contain complex optical micro 3 steps... deposition Process, implant process, annealing technology, etching system: ~ process and so on. For example, it is possible to use a complex oxidation process to perform a phototransfer (four)' followed by an advanced scorpion sculpt and a patterning process by: = respective key dimensions. In principle: phase two::::: frame area 13 0, in order to form test feature 14 2, the test heart 4 2 ^ # ^ ^ 33⁄4 ^ ^ ^ !! 〇t # ^ ^ ^ ^ =: degree =:= Shrinking, the area in which the features are characterized by a moderately large distance, the region of the domain's closely spaced features, the process may be formed with a plurality of different etch rates. Between the two: η Γ = deposition may also suffer from moderate _. As a result, the heterogeneity of a certain thickness of the (four) layer can be obtained from different device regions. Micro and the resulting surface geometry may be critical to the optical microscopy (eg, for forming gate electrodes, etc.). As a result, surface geometries I may be different even if uniformly planarized: The height level, especially the grain region HO phase 94681 ] 2 201003880 is especially true for the frame region 130, where the overall and local neighborhood of the test feature 142 can be very different than the die region 110. Thus, the final characteristic of the test feature 142 Performance may differ from the electrical performance of circuit component 151, especially for complex semiconductor devices including highly miniature circuit components. For example, the gate length of a transistor component may be in the range of 50 nm and less. Thus, even a very slight difference in the surface geometry between the region 110 and the frame region 130 can result in significant differences in electrical characteristics. As such, the actual evaluation of the characteristics of the circuit component 151 based on the test feature 142 may become It is becoming more and more difficult. After the device level is completed, the contact layer 170 can be formed, followed by appropriate formation for forming the metallization system 160. Manufacturing sequence, for example, using widely accepted damascene techniques based on copper, low-k dielectric materials, etc. It should be understood that in these device levels, for example, due to critical optical lithography steps, combined with etching, The different surface geometries caused by deposition, planarization, etc., result in inconsistencies between the grain region 110 and the frame region 130, as previously described. Therefore, the inclusion will be evaluated according to the corresponding test&quot; structure The respective test structures of the metal features will also provide different performance characteristics compared to the actual metal features in the die region 110. Thus, when electrical measurements can be obtained from the semiconductor device 100 for practical processing in the die regions In the active circuit of 110, the probe pads 141A, 141B can be accessed by respective probes of the external measuring device to establish respective currents flowing through the test feature 142, and then the electrical response can be detected and evaluated. The electrical measurement data may not be suitable due to the difference in critical dimensions, etc., which may be caused by different surface geometries, etc., for example. 13 94681 201003880 Local representation of the actual electrical performance of circuit component 151, which may therefore result in complex processes targeting undesirable targets, such as optical lithography steps, which may therefore increasingly produce poor quality products that may ultimately result Degraded Yield Distribution. The present disclosure relates to various methods and apparatus that can avoid or at least reduce the effects of one or more of the above problems. SUMMARY OF THE INVENTION A brief summary of the present invention is presented below to provide certain aspects of the present invention. The summary is not an extensive overview of the invention, and is not intended to identify key or critical elements of the scope of the invention, or to describe the invention. Present some concepts as an introduction to a more detailed description of the discussion later. In general, the present disclosure relates to semiconductor devices and methods in which the associated test structure can be configured for the die area of the semiconductor device with increased correlation with the electrical performance of the circuit components associated with the active circuit. Electrical measurement data. Alternatively, the respective probes can be positioned within the frame region and the test structure and probe pads can be attached according to a suitably designed conductive path to avoid significant consumption of grain area. In some illustrative aspects disclosed herein, the conductive path can be at least partially disposed beneath the metallization system of the semiconductor device, thereby enabling "crossing" to be formed in the metallization system of the semiconductor device. The grain seal does not unduly affect the mechanical properties of the semiconductor device. As a result, a high degree of flexibility in selecting the appropriate location for testing the structure can be provided so that a very similar condition can be established during the manufacture of the test feature, thereby resulting in 14 946S1 201003880 A high correlation between the test characteristics and the electrical performance of the actual circuit components. In other cases, at least a portion of the test features represent actual circuit components that can be used at least temporarily as test features during the process. The test feature is accessed via a conductive path and a probe pad that can be established at any suitable manufacturing stage, such as at the device level and/or in any metallization layer still to be formed. As a result, any process in the process The desired stage can be effectively obtained with a high degree of Electrical measurement data of the actual electrical performance of the active circuit. In some of the illustrative aspects disclosed herein, the buried portion of the conductive path can be established within any suitable device level below the metallization system, for example, active Above the semiconductor layer, the substrate, the semiconductor layer or the contact level, without substantially adversely affecting the integrity of the grain seal within the metallization system. One exemplary semiconductor device disclosed herein includes comprising a substrate formed over the substrate a metallization region of the semiconductor region and the semiconductor region. The semiconductor device includes a plurality of circuit elements formed in the semiconductor region and over the semiconductor region. Further, the 'grain sealing region is formed in gold, ί&quot; In the genus system, and provided with a conductive path connected to a plurality of circuit elements, the conductive path includes a portion of the buried portion formed under the die seal region. An exemplary method disclosed herein includes a semiconductor region Forming a plurality of circuit elements on the neutralization, wherein the plurality of circuit elements are formed in the semiconductor Within the die area of the body device. The method further includes forming a buried conductive path connected to at least one of the plurality of circuit elements. Finally, the method includes the plurality of circuit elements and the embedding 15 94681 201003880 A metallized system grain sealing region is formed on the conductive path, and the object is composed of a domain, and wherein: =2! From the crystal region and the frame region A further exemplary method of forming a portion of the upper iliac crest region formed in the embedding section includes at least one iliac device region separating the granule region from the frame region. a path connecting the at least one circuit to one or more probe pads in the conductive domain. Finally, forming one or more probe pads and measuring devices in the frame region and receiving power from the second package Sexual measurement data.兀 羧 羧 羧 [Embodiment] 乂τ (4) Various exemplary embodiments of the present invention. For the sake of clarity, the “all features of the implementation are not described in this document.” = == In the development of such a practical embodiment, it must be made; the real = decision to achieve the developer’s specific goals, “The industry-related restrictions that make H-related or commercial development effects can be complex and time consuming, but this is routine for those who have the usual knowledge in the technical field of L: Jielu. Referring to the drawings to illustrate the cup. ZJ. This 1 day. Various structures, systems and devices are not painted in the drawings for the purpose of illustration only, so as not to be obscured by those skilled in the art. However, the present invention is simplistic. However, the drawings illustrate and explain the examples of the present invention. The meanings and meanings of the present invention should be understood and explained in the meanings recognized by those skilled in the art. 946S1 16 201003880 - Before and after the text Consistently used terms and vocabulary do not imply a specific definition, and a specific definition refers to a definition that is different from the common idioms that are familiar to the skilled person. If a term or vocabulary has a specific definition, that is, The specification will provide its definitions directly and explicitly when it comes to the benefit of those skilled in the art. In general, the present disclosure provides semiconductor devices and methods for forming and operating semiconductor devices in which the semiconductor devices are The correlation between the electrical measurement of the feed and the electrical performance of the circuit components of the active circuit in the die region can be enhanced. For this purpose, for example, by means of circuit components that can be temporarily used as test features - and/or The electrical measurement data can be obtained from the die region at any suitable manufacturing stage by a dedicated test structure, wherein the electrical access can be accomplished via a conductive path comprising the buried portion so as not to unduly affect the crystal The mechanical integrity of the grain seal. As a result, a minimum grain area can be provided for providing test features, or for establishing an appropriate interconnection scheme for temporarily using actual circuit components as test features, while appropriate The size of the probe pad is set in the frame area %. As a result, it is used to connect the electricity used as the test feature. Depending on the interconnection scheme of the component and the probe pad, the internal measurement of the die can be taken at a relatively early stage of manufacture compared to conventional strategies, since each probe pad can be formed once in the frame region. Thus, with a probe pad available, the buried portion of the conductive path can provide the possibility to access the device hierarchy within the die region, even before the actual metallization layer is actually formed. Allows the generation of electrical measurements. On the other hand, during the manufacturing sequence used to provide the grain seals in the metallization system, 17 94681 201003880 can be used to maintain a high degree of compatibility while maintaining a high degree of compatibility. The desired mechanical integrity of the metallization system is also provided, for example, regarding the generation of cracks during processing of the sensitive metallization system and cutting of the carrier material. In some exemplary embodiments, only the conductive path corresponding to the embedding is present. Each portion of the die seal can be electrically insulated from the device level to maintain electrical insulation between the probe pad and the die seal region, thus To maintain the seal die connected electrically with the semiconductor layer or the substrate of the active. As a result, substantially the same electrical and mechanical properties for the grain seal region can be achieved, while still providing superior electrical measurement data, which can also be generated in any suitable manner, relative to conventional strategies. Manufacturing stage. Figure 2a shows a top view of a semiconductor device 200 in a schematic manner, the semiconductor device 200 including a die region 210, a die seal region 220 laterally surrounding the die region 210, and a frame region 230. Moreover, the grain region 210 can include a functional circuit 211 that can provide the desired electrical function in accordance with the overall circuit design. For example, the functional circuit 211 may include a digital circuit, an analog circuit, etc., which may incorporate a low power circuit, a high power circuit when considering a complex system on a wafer. For example, a CPU including a memory region, an ASIC including a complicated digital and analog circuit, and the like may be disposed in the die region 210. Moreover, circuit portion 240 can be disposed within die area 210 and, in certain exemplary embodiments, can represent a dedicated test structure configuration to provide at least one electrical characteristic (eg, threshold voltage, drive current, switching speed). Electrical measurement data of other forms of transistor characteristics). In this case, circuit portion 240, which is in the form of a test structure, can represent at least one circuit element that is isolated from functional circuit 211 and can be operated without affecting circuit 211. In other exemplary embodiments, circuit portion 240 can include at least one or more circuit elements that can represent a portion of functional circuit 211, such as by being provided between circuit portion 240 and one or more portions of functional circuit 211. Appropriate interconnection system to set up. In this case, in addition to the interconnect structure 212, an interconnect structure capable of dedicating the at least one or more circuit components as a test feature to obtain an internal electrical measurement of the die may be provided. For this purpose, one or more conductive paths 245, 246 may be provided to connect the circuit portion 240, whether or not the circuit portion 240 may represent a dedicated test structure or may be temporarily used as part of the circuit 211 of the test structure. Depending on the overall circuit configuration, at least the conductive paths 245, 246 can be partially established within the device level, the contact level, and the metallization system. Moreover, conductive paths 245, 246 can each include a "buried" portion or section 245A, 246A, respectively. Portions 245A, 246A can be considered as buried sections, that is, portions 245A, 246A can extend from die area 210 to the frame area below die seal 220 (i.e., below the metallization system of device 200). 230, which will be explained in more detail later. As a result, the circuit portion 240 at least temporarily representing the test structure can be connected to the plurality of probe pads 241A, 241B by the conductive paths 245, 246, wherein the size of the probe pads 241A, 241B is appropriately given to enable A test device, such as any suitable test device known in the art, is accessed externally. As a result, due to the configuration of the semiconductor device 200, the electrical measurement data can be obtained by, for example, the internal die of the circuit portion 240, without excessively consuming the available wafer area because of the consumption area. The pin cushions 241A, 241B can be positioned in the frame region 230. Moreover, the mechanical integrity of the die seal region 220 (which may be formed by the connected metal lines in the metallization system of the device 200) may be maintained while still allowing via the probe pads 241A, 241B and the conductive path 245. , 246 to achieve electrical access to the circuit portion 240. Thus, during the manufacturing phase of the semiconductor device 200, once the probe pads 241A, 241B are formed, the electrical measurement data can be collected from the circuit portion 240 immediately. For example, if the conductive paths 245, 246 are substantially built into one or more of the lower metallization layers, the probe pads 241A, 241B can be formed at an early stage of fabrication, and thus the circuit portion 240 can be electrically accessed. In order to obtain the desired internal measurement data of the grain. In some exemplary embodiments, the conductive paths 245, 246 may even be built into the device hierarchy and may combine the contact levels of the device 200 without substantially requiring any overlay metallization layer, such that upon completion of the basic transistor structure Or an effective electrical measurement can be paid even before the basic transistor structure is completed. Since the circuit portion 240 can be formed according to a neighboring region similar to that encountered when forming the actual circuit component of the functional circuit 211, or if the circuit portion 240 can represent a portion of the circuit 211, the corresponding electrical measurement data can have a height Authenticity in order to evaluate the electrical performance of functional circuit 211, which may also result in superior control strategies, such as those relating to appropriately determining target values for critical processes, as previously described. Figure 2b shows in schematic form a cross-sectional view of semiconductor device 200 along section lib in accordance with an illustrative embodiment. As shown, the semiconductor device 200 20 94681 201003880 can include the same criteria as described above for the substrate 201. j should be formed on the main body, * and above, such as functional electric kilo, body z 11 and Thunder circuit components. For the sake of convenience, it is omitted. Ρ 分 a t 2b in the picture 202. Regarding the substrate 201 and the semiconductor layer 2, j can form a semiconductor layer 1 Ο 夕 夕 日 从 从 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 隹 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 层 层 层 层 层 层 层 层 层 层 层 层 层- &quot; 240 required component 242, the circuit component 242 can take _. The beer does not have a plurality of circuit components, and at least the circuit portion 24 of the circuit components 242 is used as a test feature to extract from the die region 2: at least temporarily, the semiconductor layer 202 can be formed and formed therein. Sexual measurement data. The device level of the conductor device, such as the front = yuan:: to; semi-metallization system 260, the metallization of the metal can be set up, 2 Na, dirty, such as by a plurality of gold as by the functional circuit 211 The wiring is required for the big case. It should be understood that in the illustrated manufacturing stage, the metallization system 26 may still be completed when highly complex semiconductor devices are considered. Thus, when metallization system 260 is completed, it can include more metallization layers than those shown in the &lt;= diagram. In other cases, as previously discussed, if the corresponding conductive paths 245, 246 can be established with a reduced number of metallization layers, the metallization system 260 can include a smaller number of metallization layers, such that The corresponding electrical offset data is obtained in the early stages of the entire manufacturing sequence. In the illustrated embodiment, the conductive path 246' can be established by using the metallization layer 260A of the metal line 261. The metal line 261 can be connected to the other metal lines 261 in the metallization layer 260B through the through holes 262. Moreover, conductive path 246 can be coupled to one or more circuit elements 242 via contact level 270, which can include appropriate dielectric 21 94681 201003880 materials and respective contact elements 271A within die area 210 and Contact element 271C within frame region 230. It will be appreciated that within at least a portion corresponding to the buried conductive path 246A, the die seal region 220 may not be coupled to the device level 250 by the contact level 270, while other regions of the buried portions 245A, 246A are not disposed. Corresponding contact elements or regions may be provided, as previously described with reference to device 100, with reference to contact portion 171B (Fig. lb). As a result, the buried conductive path 246A is connected to the circuit portion 240, i.e., one or more circuit elements 242, within the die region 210 by contact elements 271 and metal lines 261 and through vias 262, and by positioning The contact member 271C and the metal line 261 and the through hole 262 in the frame region 230 are connected to the probe pad 241B. As such, the electrical connection of the circuit portion 240 to the probe pad 241B can be established by the conductive path 246, wherein the buried portion 246A provides the mechanical integrity of the die seal region 220 while also being at least The dielectric material of the contact level 270 is disposed over the buried portion 245 without the contact elements being connected to the die seal region 220 while remaining electrically isolated from the die seal region 220. The semiconductor device 200 as shown in Fig. 2b can be formed in accordance with the following processes. Circuit elements for functional circuit 211 and circuit component 242 of circuit portion 240 can be formed in accordance with a desired fabrication technique, wherein circuit portion 240 can be positioned at any suitable location within die region 210 for obtaining The similar process conditions and hence the electrical performance of the circuit components 24 in other critical regions within the grain region 210 can establish highly similar process conditions. For example, if certain key processes (eg, optical lithography, planarization techniques, etc.) are known to be highly sensitive to patterning density, the circuit element 242 can be placed to provide similarity to the circuit element 242. The device area at the local neighborhood is such that a comparable process result will be obtained for the critical device area and for circuit component 242. During the manufacturing sequence used to form circuit component 242, buried portion 246A can also be formed, for example, by any suitable fabrication technique (e.g., implantation of a dopant species to provide a low resistance path, etc.). The various processes that can be used to form the buried portion 246A in accordance with the sequence used to form the active regions of the transistor will be described in greater detail later. Thus, if desired, a high degree of compatibility with conventional process techniques can be maintained without excessively creating additional process complexity. Thereafter, a patterning process can be used, for example, by depositing a suitable dielectric material to define contact holes for contact elements 271A, 271B and respective contact elements or lateral sides of conductive paths 246A for embedding. Portions of the die seal region 220 form a contact level 270. Accordingly, a suitable optical lithography mask can be provided to avoid electrical contact between the die seal region 220 and the buried portion 246A. Thereafter, the metal can be filled into the contact opening in accordance with widely accepted process techniques. The metallization system 260 can then be formed in accordance with widely accepted process techniques, or required to complete the conductive path 246 and provide at least a portion of the probe pads 241A, 241B, however, contrary to conventional strategies, appropriate The design is to provide a metal wire 261 and a through hole 262 for connection to the buried portion 246A and to the probe pads 241A, 241B. Thus, after the conductive path 246 is completed, the electrical measurement data can be obtained by connecting the probe pads 241A, 241B with an external electrical measuring device 23 94681 201003880. Thereafter, other metallization layers can be provided if desired. It will be appreciated that the respective test features can also be disposed within the metallization system 260 within the die region 210. When it is desired to test the metal features, the test features can also be suitably comprised of embedded portions (e.g., portions 245A, 246A). Conductive path connections. Moreover, when the electrical measurement data can be obtained from circuit portion 240 at a later stage of fabrication, a respective probe pad can be provided to cover previously formed pads 241A, 241B, thereby enabling the formation of metallization system 260 during formation. Any advanced manufacturing stage can be accessed externally. Figure 2c shows in schematic form a cross-sectional view of a semiconductor device 200 in accordance with yet another illustrative embodiment, wherein the buried portions 245A, 246A may be disposed on the semiconductor layer 202, for example, in the form of a gate electrode material. As shown, the buried portion 246A may be formed on or over the semiconductor layer 202, or may be formed on or above the isolation region disposed in the semiconductor layer 202, depending on the overall process strategy. For this purpose, in some exemplary embodiments, the buried portion 246A may be formed along the gate electrode structure of the transistor in a common fabrication sequence. For example, after the gate dielectric material and the gate electrode material are formed on the semiconductor layer 202 above the isolation region (eg, trench isolation, etc.) in the active region of the transistor, the optical micro according to the appropriate design may be The shadow mask performs a subsequent patterning process to pattern the buried portion 246A. In general, the gate electrode structure can be set to a suitably low resistance 94681 201003880, for example, by adding a moderately high dopant concentration and/or providing a metal-containing material (eg, in the form of a metal cation). The rate allows the buried portion 246A to also include a moderately low resistivity for use as an interconnect structure between the circuit portion 240 and the probe pads 241A, 241B. In other cases, complex gate electrode materials in the form of metal-containing materials may be used and may be used in a process strategy using high-k dielectric gate materials, and the corresponding process sequence may be applied to the buried portion 246A. As such, conductive path 246A can be established without additional processing steps so that a high degree of compatibility with conventional process strategies can be maintained. Figure 2d shows, in schematic form, a semiconductor device 200 in accordance with other exemplary embodiments in which buried portions 246A, 245A may be disposed at contact level 270. In the fabrication stage illustrated in Figure 2d, the first metallization layer 260A can be formed over the contact level 270 and can include respective metal lines 262 to connect the buried portion 246A, the buried portion 246A being capable of The contact "element" in contact level 270 is provided in the form of a contact. Similarly, in the die seal region 220, a respective metal line 262 may be provided, however, the metal line 262 may be terminated by an additional etch stop layer 263 (eg, in the form of tantalum nitride or the like) and the buried portion 246A. Electrically isolating, the etch stop layer 263 can be additionally disposed over at least the buried portion 246A to maintain the electrical integrity of the conductive path 246 that is still to be established via the subsequent metallization layer 260B, as also referred to above. The descriptions are shown in Figures 2b to 2c. As a result, the contact level 270 can be formed in accordance with widely accepted process techniques, however, different contact masks can be used to form respective contact holes in the dielectric material of the contact level 270 corresponding to the buried portions 246A. Thereafter, the contact element 271A in the die region 210 may be formed with the buried portion 246A and possibly also with other contact portions that are connected to the die seal 94681 201003880 region (ie, the buried portion 246A). The metal wires 262) of the outer region are formed together. Thereafter, layer 263 can be deposited, for example in the form of hafnium oxide, tantalum nitride, or the like, depending on the type of material to be deposited on metallization layer 260A. Next, the etch stop material can be patterned to obtain portion 263, as shown in Figure 2d, after which the usual deposition sequence for providing a suitable dielectric material for metallization layer 260A can be implemented. Thereafter, other processes can be continued in accordance with widely accepted strategies, however, during the patterning of the dielectric material of metallization layer 260A, additional etch stop layer 263 can reliably avoid contact with buried portion 246A. As a result, in this case, a highly conductive connection can also be established while maintaining a high degree of process compatibility while requiring only additional deposition and patterning steps. Referring to Figures 2e through 2g, additional illustrative embodiments will now be described in which a highly conductive buried portion can be formed during the standard fabrication sequence for forming the drain and source regions of a transistor of a particular conductivity type. Figure 2e shows a partial top view of the semiconductor device 200 in a schematic manner, with one of the circuit elements 242 in the form of a transistor element being shown for convenience, and a portion of the portion 246 embedded in the die region 210 being illustrated. . In the illustrated manufacturing stage, the active region 242D for the transistor 242 can be defined in accordance with the isolation structure 203, which can be provided in the form of shallow trench isolation. Further, a gate electrode 242G as indicated by a broken line will be formed over a portion of the active region 242D and the isolation structure 203. Similarly, in the illustrated manufacturing stage, the buried portion 246B can include an active region 26 94681 201003880 246D surrounded by the side of the isolation structure 203. It will be appreciated that the active region will be understood to be a semiconductor region in which an appropriate dopant concentration will be established, possibly in combination with a metal-containing material, to provide the desired conductivity. Fig. 2f shows, in a schematic manner, a semiconductor device 200 according to the section Ilf of Fig. 2e. In the illustrated embodiment, device 200 can represent an SOI configuration in which a buried insulating layer 204 can be disposed between semiconductor layer 202 including isolation structure 203 and substrate 201. It should be understood, however, that the principles disclosed herein may also be applied to a bulk configuration, i.e., a configuration in which at least some of the device regions of device 200 may omit the buried insulating layer 204. Thus, as shown, the gate electrode structure 242G can be formed over the active region 242D, which is surrounded by the side of the isolation structure 203. Further, implant region 242A can be formed in active region 242D to provide a desired dopant concentration for the source and drain extensions of transistor 242. Similarly, in the buried portion 246B, the implanted region 242A can be formed over the active region 246D. The device 200 of X as shown in Figure 2f can be formed according to widely accepted process techniques, including forming a gate dielectric material, followed by depositing a suitable gate electrode material, such as polysilicon, etc., and then patterning the The gate electrode material is equal to the gate electrode 242G. Thereafter, an appropriate implantation sequence can be implemented while using the gate electrode structure 242G as an implant mask to obtain the doped region 242A in the active region 242D. Similarly, doped region 242A can be formed in active region 246D of buried portion 246B. Thereafter, the spacer structure 242S can be formed on the sidewalls of the gate electrode structure 242G in accordance with widely accepted process techniques. It should be appreciated that 27 94681 201003880 other types of transistors can be masked in accordance with widely accepted CMOS techniques during the implantation process used to form region 242A. The 2g diagram is shown in schematic form at another advanced stage of fabrication of the semiconductor device 200. As shown, deep drain and source regions 242B can be formed in transistor 242, and similar dopant concentrations 242B can also be provided in buried portion 246B. Furthermore, the metal telluride region 242C can be formed on the drain and source regions 246B and in the gate electrode of the transistor 242, and the corresponding metal halide region 242C can also be disposed on the buried conductive path 246B. . As a result, the buried portion 246B can be provided as a low resistance path due to the high dopant concentration 242B and the metal telluride region 242C, and the buried portion 246B can be formed along with a respective transistor structure (such as the transistor 242). Therefore, it does not substantially cause additional process complexity. Furthermore, in the SOI configuration shown in FIG. 2g, the isolation structure 203 can provide lateral insulation of the buried conductive path 246B, while the buried insulating layer 204 can also be provided for vertical insulation, so that In addition to any contact elements 271A, 271C of the metallization system, in combination with the dielectric material from contact layer 270 (not shown in Figure 2g), substantially complete electrical insulation of buried portion 246B can be obtained, as previously described. Illustrator. Referring to Figures 2h through 2i, additional illustrative embodiments will now be described in which the buried portion 246A, 246B may be additionally or alternatively formed in the device level 250 and/or the contact level 270 within the substrate 201. Figure 2h shows the device 200 in an earlier stage of manufacture in a schematic manner. As shown, the semiconductor layer 202 can be formed in a buried insulating layer 28 94681 201003880

- 204, thereby defining the SOI fabric. As is well known, in many complicated integrated circuits including SOI fabrics, at least some device regions may be added to the substrate 201, for example in the form of a substrate diode, etc., such diodes The body can often be used as a thermal sensing device or the like. For this purpose, an opening may be formed through the semiconductor layer 202 and the buried insulating layer 204 to expose a portion of the substrate 201. As a result, an appropriate opening may be formed at a region corresponding to the die seal region 220 during the respective process sequence or during a separate process sequence to be provided in the buried portion in the substrate 201. For this purpose, a suitable etch mask can be provided to expose the desired portion of the semiconductor layer 202 in conjunction with the corresponding fabrication sequence used to form the substrate diodes, or in a separate sequence, while masking other device regions. Thereafter, an etch sequence can be performed in accordance with the widely accepted etch recipe to etch through the semiconductor layer 202 and the buried insulating layer 204. Figure 2i is shown in schematic form on device 200 after completion of the above described process sequence. Furthermore, when portion 246B can be formed in accordance with the transistor fabrication sequence, the buried portion 246B can be formed on the substrate, for example, according to any suitable technique, such as providing a high doping concentration, and possibly in combination with a metal telluride region. 20], as described above with reference to the 2f to 2g drawings, only in the substrate material 201. For example, during the corresponding process sequence, the respective substrate diode structures can be formed, thereby also providing a high degree of process compatibility with conventional strategies. Thereafter, other processes may be continued in a manner similar to that described above, i.e., contact level 270 and metallization system 260 may be formed as previously described to complete the via circuitry 29 94681 201003880 including buried portion 246B. 246. As a result, the present disclosure provides a semiconductor device and a method of forming and operating the same, wherein the internal measurement data of the die can be obtained, for example, via a dedicated test structure or via a circuit component that can be temporarily used as a test feature, which can be Suitably designed to be interconnected in the form of one or more electrically conductive paths, each of which may include a portion to provide a buried connection from the die region to the frame region without affecting the die seal Mechanical integrity of the area. That is, the buried portion can extend from the die region to the frame region below the die seal region, thereby maintaining the mechanical stability of the semiconductor device while still providing the internal circuit components and locations for connecting the die. A low resistance path of the probe pad within the frame region. The die seal can still maintain electrical contact with any portion of the substrate or the outer side of the buried conductive path, thereby providing substantially the same electrical performance as the grain seal of conventional devices. As a result, the circuit characteristics used to obtain the electrical measurement data can form a continuation with respect to the degree of critical device features in the die region, thereby enhancing the evaluation of the electrical performance of the active circuit in the die region. Furthermore, since at least the conductive bridge between the die region and the frame region can be established in an early manufacturing stage, the present disclosure provides the possibility of obtaining electrical measurement data at an early manufacturing stage, that is, as a test. Once the conductive path between the characteristic circuit component and the probe pad is established, it can be obtained immediately. As a result, extremely important electrical measurement data can be obtained during the manufacturing process (i.e., prior to completion of the metallization system), and Itrj does not have the electrical and mechanical functions of mussels and grain escapes, seals. 30 94 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 For example, the process steps can be different from the bed----------------------------------------------- Furthermore, outside of the architecture or narrator shown here. Therefore, it is to be noted that the specific embodiments and variations of the present invention are as described in the spirit and the scope of the present invention. Accordingly, the claimed invention is intended to be within the scope of the appended claims. &lt; A. The monthly special [schematic description] The reference to the above description, together with the accompanying drawings, can be used to understand the same components in the inner valley of the present disclosure, and the same component symbol identifies the same component, and wherein: the guide U/lb diagram is respectively indicated The method shows that according to the half of the conventional strategy ==!: section: the semiconductor device includes an electrical test structure positioned in the frame of the material guide plate to obtain an electrical measurement resource to illustrate The method shows a semiconductor mounting pattern according to an exemplary embodiment. The semiconductor device includes a plurality of electric spoons/at least one of the circuit elements in the die area that can be used as test features, and the test is performed via the conductive path of the added portion. The feature is connected to a probe pad located in the frame of the frame; the map is shown in a schematic manner in accordance with Figure 2a of the illustrative embodiment + = sectional view of the device 'where the buried conductive path is formed in the semiconductor layer of the device Below the die seal area; t 94681 31 201003880 Figure 2c shows in schematic form a cross-sectional view of a semiconductor device according to a second embodiment of another exemplary embodiment, wherein the buried portion is 2D is a schematic view showing a cross-sectional view of a semiconductor device according to a second embodiment of the exemplary embodiment, in which a buried portion can be established at a contact level; and FIG. 2e is shown in a schematic manner A top view of a transistor active region and a buried portion of a conductive path for connecting to a probe pad outside the die region in accordance with an exemplary embodiment; FIGS. 2f through 2g are diagrammatically shown in accordance with a second embodiment of the illustrated embodiment a cross-sectional view of the device during various stages of fabrication wherein the portions of the fabrication are provided as a low resistance path in accordance with the order in which the drain and source regions of the transistor are formed; and the 2h to 2i In accordance with yet another illustrative embodiment, a cross-sectional view of a semiconductor device during various stages of fabrication in which a portion of a buried portion of a substrate material of an SOI fabric is disposed is shown. While the subject matter disclosed herein is susceptible to various modifications and alternatives, It should be understood, however, that the description of the specific embodiments of the invention are not intended to All modifications, equivalents, and changes. [Major component symbol description] 100 semiconductor device 32 94681 201003880 101 102 110 120 130 140 141A, 141B 142 150 151 160 160A, 160B, 160C 161 162 170 171A, 171B, 171C 200 201 202 203 204 210 21 1 212 220 Substrate semiconductor Layer grain area grain seal frame area (frame) Electrical test structure probe pad test feature (area) Device level circuit component metallization layer (metallization system metallization layer metal wire through hole contact layer contact element (contact part) Semiconductor device substrate semiconductor layer isolation structure buried insulating layer grain region functional circuit interconnection structure die sealing region 201003880 230 frame region 240 circuit portion 241A, 241B probe pad 242 circuit component (transistor) 242A implant region ( Doped region) 242B deep drain and source region (dopant concentration) 242C metal germanide region 242D active region 242G gate electrode 242S spacer structure 245 &gt; 246 conductive path 245A, 246A segment (embedded portion) (conductive path) 246B buried part 246D active area 250 Level metallization system 260 set 260A, 260B, 260C metallization layer 261 through-hole 263 a metal line 262 engraved name stop layer 270 contacting the contact level 271 element 271A, 271B, 271C contact element 94681

Claims (1)

201003880 2. Patent application scope: A semiconductor device comprising: a grain region, a semiconductor region; comprising a metallization system formed over the substrate and formed in the semiconductor region and over the plurality of circuit element semiconductor regions; ri (10) region Formed in the metallization system; and a scoop connected to the plurality of circuit elements, the conductive circuit: (d) embedded in the portion of the day-to-day area, as defined in the patent application, the first circuit element definition Independent test structure, information. The semiconductor device of the present invention, wherein the plurality of functional circuits formed in the crystal (four) domain towel form the test structure to form an electrical measurement. i. The semiconductor device of the item: the plurality of circuit elements are formed in the die region: part of the second circuit.甲之功月匕4. 5. 6. If the scope of application for patents is 】-u thousand limbs device, the frame area surrounding the daily granule seal area is included, 1 4, with T ' The frame area includes a top stitch pad, and the at least one probe + $ ^ ^ pin pad is electrically connected to the buried portion of the conductive path. The device of the semiconductor device of the first aspect of the patent, wherein the buried 4 is formed at least partially in the semiconductor region. The semiconductor device of claim 1, wherein the portion of the buried portion 9468] 35 201003880 is at least partially formed in the substrate. 7. The semiconductor device of claim 1, wherein the buried portion is formed at least partially over a level of two degrees from a surface = boundary of the semiconductor region. 8. The semiconductor device of claim 7, wherein the buried portion comprises a gate electrode material. The semiconductor device of claim 7, wherein the buried portion is at least partially formed at a contact level of the semiconductor device, such as the semiconductor device of claim i, wherein the "area system" The semiconductor device of the first aspect of the present invention, wherein the die is at least one of a contact level electrical conductor region of the semiconductor device and the substrate. To the sub-guide area of the patent, the semi-guided area is electrically insulated from the conductive path. The method of ignoring the granules includes: a semiconductor in the grain region of the upper semi-lead-red device Forming a plurality of circuit components in and over the region; the plurality of Wei paths are connected to the plurality of circuit components to form a metallization, and the second conductive path is shaped by a crystal "the system includes a grain seal The region, the grain phase region and the frame region, the grain is densely 94681 36 201003880 14. The second::::: is formed on the buried conductive circuit. • s T 〇 寻 寻 苐 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 ‘ ‘ ‘ ‘ ‘ 该 该 该 该 该 该 该 该 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在The method of claim 13, wherein the metallization is formed to form at least one probe pad in the frame region, the π being electrically connected to the buried conductive path. f 16. The method of claim 15, wherein the metallization is formed [t the metallization system included in the grain region _ forming and the buried =: ΓΓ an interconnect structure is connected to the test The structure includes a (four) frame plus a path from which the metallization system is formed, and a second interconnect structure is formed in the metallization system in the region, and the second interconnect structure is connected to the buried a conductive path and the at least one probe pad. 17.2. Please refer to the method of §13, wherein the buried conductive ί path is formed in the process of forming the drain and source of the transistor of the type. ^ 1 As in the case of the patent (4) 13-like method, the towel, the self-contained conductive line is formed in the sequence of the electrode structure used to form the transistor device: [9] The method of claim 3, wherein the embedding guide is formed in a process for forming circuit components formed in the substrate. 20. The method of claim 14, wherein the method includes connecting at least - 94681 37 201003880 probe pads to an external measurement probe, and obtaining electrical measurement data from the test structure. 21_ a method comprising: ▲, disposing at least one circuit component in a die region of the half V body device, and separating the die region and the frame region by a die seal region; and providing a conductive path to connect the at least one circuit The component and the one or more probes formed in the shelf region; and the new measurement data are obtained from the V-circuit components by connecting the one or more probe pads and the measuring device. 2. If the scope of the patent application is included in the guiding circuit and the guiding circuit, the portion of the guiding circuit is disposed in the slap, and the embedded portion is known to be in the sealing area of the semiconductor device. In the lower part of the system, the grain is densely traversed. 3. If the metal of the square device of the item is completed, the semiconductor material is completed. The method of item 21, wherein 'the at least one electric ==::: the electrical component of the circuit element is electrically insulated to form a test ί circuit in: = a function formed by the other circuit component. For example, claim 21 The data of the item includes the at least lightning, the middle, the electrical measurement, and the circuit components are set as the functional circuit and the boring tool, and the functional circuit includes (4) using the at least one component as the measuring component. And temporarily 94681 38