201003866 九、發明說明： 【發明所屬之技術領域】 本發月係有關於—種封裝基板結構，尤指—種可埋設 半導體元件之封裝基板結構。 【先前技術】 目刖業界為滿足半導體封裝件高積集度 (Integration)及微型化（Miniaturizati〇n)的封妒需 f，且為求提昇單—半導體封裝件之性能（ability)與容 里（capac 1 ty)以符合電子產品小型化、大容量與高速化之 趨勢’係發展出半導體晶片之堆疊技術。 5月多閱弟1A圖，一般具有堆疊技術之半導體封裝件 係將一第—半導體晶片以覆晶（FlipChip)方式電性連 接於一基板10上，且於該基板1〇相對接合第一半導體晶 f y之側°又置供外接其他電子裝置之焊料球12，並於 該第-半導體晶片n上黏接至少一第二半導體晶片η: 且該第二半導體晶片13以打線(Wire bonding)方式藉由 =線14電性連接至該基板1()，並於該基板1()上形^包 覆該第-及第二半導體晶片u，13i封裝材15。 然，因第一及第二半導體晶片11>13均電性連接同一 土板1 0 ’右其中一半導體晶片故障，將導致半導體封誓 件整體失效，且僅能從基板1Q上測試全部晶片的良/ 而無法單獨檢測單—半導體晶片的良率，致使該半導㈣ 裝件需整件報廢，而浪費成本。201003866 IX. Description of the Invention: [Technical Field of the Invention] This publication relates to a package substrate structure, and more particularly to a package substrate structure in which a semiconductor element can be buried. [Prior Art] The industry has met the need to meet the high integration and miniaturization of semiconductor packages, and to improve the performance and capacity of single-semiconductor packages. (capac 1 ty) has developed a stacking technology for semiconductor wafers in line with the trend of miniaturization, large capacity, and high speed of electronic products. In the case of a multi-layer semiconductor package in May, a semiconductor package having a stacking technique is electrically connected to a substrate 10 by a flip-chip method, and the first semiconductor is oppositely bonded to the substrate. The side of the crystal fy is further provided with a solder ball 12 for externally connecting other electronic devices, and at least a second semiconductor wafer η is bonded to the first semiconductor wafer n: and the second semiconductor wafer 13 is connected by wire bonding. The first and second semiconductor wafers u, 13i are packaged on the substrate 1 () by electrically connecting the line 14 to the substrate 1 (). However, since the first and second semiconductor wafers 11 > 13 are electrically connected to the same soil plate 10 'right one of the semiconductor wafer failures, the semiconductor sealing member will be completely failed, and only the entire wafer can be tested from the substrate 1Q. Good / can not separately detect the yield of the single-semiconductor wafer, so that the semi-conductive (four) assembly needs to be scrapped in whole parts, which is a waste of cost.
遂發展POP 睛麥閱第1B圖’為解決上述之問題 110852 5 201003866 (Package on Package)技術，以提供另一種半導體封裝 件，係包括至少二封裝件i 6，各該封装件1 6之間藉由導 電件17相互電性堆疊；其中，該封裝件16具有一基板 160、設於該基板16〇上並以打線方式電性連接至該基板 160之半導體晶片161、以及設於部份之基板16〇上且覆 盍該半導體晶片161之封裝材162，且該導電件丨7設於 該基板160上；另外，於最下層之基板16〇之相對堆疊之 一側設有供外接其他電子裝置之焊料球163。 惟，各該封裝件16的高度係為該基板丨6〇及覆蓋該 半導體晶片161之封裝材162的高度總和，且因該半導體 晶片161設於基板16〇上，迫使封裝材162的高度需配合 =導體晶片161的高度，而使整體半導體封裝件高度^ 高’俾使PGP技術之半導體封裝件不易製成輕薄短小^裝 置，因而使電子產品的應用受限；另外，因半導體晶片 =1被封裝材ι62所覆蓋，導致半導體晶片ΐ6ι於作:過 辁中不易散熱’而產生高熱，致使半導體晶片Μ埶， 進而使半導體晶片1 61發生損毁。 問題’實為 因此’如何解決上述習知半導體封裝件的 目荊亟欲解決的課題。 【發明内容】 4α於上述習知技術之種種缺失，本發 — 提供—種降低封裝高度之封裝基板結構。 目的在於提供一 本發明之另一 基板結構。 種具散熱功能之封襞 II0852 6 201003866 •構，ί達^述及其它目的’本發明揭露—種封裳基板結 μ ·基板’係具有相對之第—及第二表面，Μ 弟表面上具有複數打線墊，於該第二表面上且 球塾，且具有貫穿該第一及第二表面之開口;；=: 第二表面上’並封住開口，且該金屬板之厚 ;植球塾，該金屬板面積略大於該開口；以及防 ::::該基板之第一及第二表面上，並具有對應開 防>層開η，且該防焊層具有複數開孔，以對應 各該打線墊、植球墊及金屬板。 Μ 上述之封裝基板結構中，該基板係為 =多層封裝基板;該金屬板係為銅，：3 防:層之間復具有介電層，以使金屬板部份埋入 料球r日 設置複數接觸該金屬板或植球塾之焊 之封録板結構復可包括電性接料、半導 (、¥線或封裝材。該電性接觸墊係可設於: 俾供電性連接至-半導體二 片係可容設於開口中並結合於金 ^相對之作用面及非作用面，該作用面上具有複數電極 接今tit作用面結合於金屬板上；該導線可用以電性連 並填充於開口中，！包覆第-表面 此外，上述之封裝基板結 打線塾。 Π0852 7 201003866 所組群組之其中一者。 曰 ，~ ^衣基板結構藉由開口之設計，以供半導體 严产於而可降低整體之封裝高度’·另外，該金屬板之 二二、；_球墊之厚度，以供該半導體晶片穩固設於 :反士，且利用金屬材質導熱性佳之特性，俾使半導體 曰曰片可猎由金屬板散熱’以達到具散熱功能之。 【實施方式】 , \下藉由特疋的具體實施例說明本發明之實施方 熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 詈本二？ Γ2A及2β圖，係為本發明之封裝基板結構接 +導體曰曰片封裝後之剖面示意圖；係包括：基板20、 金屬板21、防焊層22、半導體曰# ^ . 〇 裳材26。 牛導-曰曰片23、導線25以及封 i 所述之基板20係為已完成線路佈局之兩層或多声封 褒基板，該基板内部或表面之線路層係藉由導電盲孔 電錄導通孔電性連接（圖未示），該基板2Q具有相對之第 -表面20a及第二表面20b，於該基板2〇之第一及第二 表面20a，20b上具有介電層2〇1，且於該第一表面 介電層201上設有複數打線墊2〇2，又於該第二表面 之介電層201上設有複數植球墊m，且具有貫穿該介· 層201及基板20之開口 200。 ％ 其中，該打線^02上以電錢或化學沉_成^ 4理層2G2a’ &升連接結構之電性效果，而該表面處 110852 8 201003866 理層2 0 2 a係為錄、把、金、錫所組群組之一者，如鎳/ 金（Ni/Au ’係先形成鎳’之後再形成金）、化鎳浸金 (Electroless Ni & Immersion Gold，ENIG)、化鎳鈀浸 金（Electroless Nickel/Electroless pailadium/Immersi〇n Gold’ ENEPIG)、化學鍍錫（immersi〇n Tin，IT)、及直接 浸金（Direct Immersion Gold, DIG)之其中一者。 所述之金屬板21係為銅（cu)且設於該基板2〇之第 二表面20b上的介電層201上（如第2A圖所示），或部 份嵌入介電層201中（如第2B圖所示），以封住該開口 200之一鈿，且该金屬板21之厚度s大於植球墊2〇3之 厚度h，該金屬板21之面積略大於開口 2〇〇之面積，以 供承載半導體晶片23之用。 入所述之防焊層22設於該第一及第二表面20a，20b之 電層2 01上，該防焊層2 2並具有對應開口 2 〇 〇之防焊 層開口 220，且該防焊層22具有複數開孔221，以對應露 t出各該打線墊202、金屬板21及植球墊2〇3。 圖中之半導體晶片23具有相對之作用面23a及非作 “面23b，於該作用面23a上具有複數電極墊，且該 半導體晶片2 3以該非作用面2 3 b藉由黏著層2 4固定於該 200中之金屬板21上，而該電極塾231藉由該導線 5以電性連接至該基板2〇之打線墊2〇2。 因金屬板21之厚度s大於植球墊2〇3之厚度h，使 =半導體晶片23得以穩固設置於金屬板以上，且藉由金 板21導熱性佳的特性，俾使該半導體晶片藉由金屬 110852 9 201003866 板21以達散熱之作用。 圖中之封裝材26係設於該基板20之第一表面2〇a 的介電層201上，並填充於開口 2〇〇中，以包覆該半導體 晶片23、導線25及打線墊202。 另外，俾於該基板20之第二表面20b的防焊層22 之開孔221中，使外露之金屬板21及植球墊203上接置 焊料球2r ’其中，位於金屬板21上的焊料球，係 仏政熱用，而位於該植球墊2〇3上之焊料球係供外 r其他電子裝置。 '、 本發明藉由半導體晶片23置於開口 200中之設計， 而可降低整體之封裝高度，相較m技術，本發明封裝 f板結構之封裝材26不需配合半導體晶片23的高度，使 得整體封裝基板結構的高度明顯降低；此外，因半導體曰 片23谷置於開口 2〇〇中，且藉由金屬板2 片…而使半導體晶片23可藉由金屬板21進行散^。日日 请參閱第3圖# a 士政。 用之剖面示意圖明之封裝基板結構之堆疊應 β 圖所不’依第2圖所示之結構向上堆 宜’於忒基板20之第一表面2〇“ 性接觸墊204,且嗜带祕社Λ 工"又有电 ^ ^ ^ η φ ^ ^甩丨生接觸墊204上接置有導電件28， 以支心且電性連接至少—半導體封裝件3〇。 該半導體封裝件^ 裝基板_上並以導線3〇3、= 一封裝基板300、設於封 導體晶片性連接至封裝基板300之半 a u，ηι 。又於。卩份封裝基板300上且包覆該半 ¥组日日片301之封裝材3〇2。 干 110852 10 201003866 ，於其他實施例中，亦可將半導體封装件3〇以 裝件取代’而使整體高度更低;然，有關 人ί衣件30之種類繁多’惟乃業界所周知，並不 、上述且其非本案技術特徵，故不再贅述。 /由上述堆疊結構，相較於習知技術，因最底部之 半導體封裝基板結構的整體g声 ' 之封裝結構得以製絲薄降低，俾使整體堆疊 用增廣。品，-使電子產品的應 、、不上所述’本發明之封裝基板結構藉由基板設置開 體 =置人’使主要結構高度僅為基板的高 二：Γ::導體晶片厚度，以有效達到降低高度之 =之元為銅且較厚的金屬板作為承載半導體 熱功能之目的。 逆巧具月文 上述實施例係用以例示性說明本發明之原理及 ==用於限制本發明。任何熟習此項技藝之人士料 :不違广本:务明之精神及範嘴下，對上述實施例進行修 圍戶/歹/。發明之㈣保護範圍，應如後述之中請專利範 【圖式簡單説明】 f 1A及1B圖係為f知半導體封裳件之剖面示意圖； 第2A及2B圖係為本發明4# ^ 副裝後之剖面示意二1之及料基板結構接置半導體 第3圖係為本發明之封裝基板結構之堆疊應用之剖 π 110852 201003866 。 【主要元件符號說明】 10、160 基板 11 第一半導體晶片 12 、 163 、 27 、 27’焊料球 13 第二半導體晶片 14 ' 25 ' 303 導線 15、162、26、 302封裝材 16 封裝件 161、23、301 半導體晶片 17、28 導電件 20 基板 20a 第一表面 20b 第二表面 200 開口 201 介電層 202 打線墊 202a 表面處理層 203 植球墊 204 電性接觸墊 21 金屬板 22 防焊層 220 防焊層開口 221 開孔 12 110852 201003866 z^a 作用面 23b 非作用面 231 電極墊 24 黏著層 30 半導體封裝件 • 300 封裝基板 h ' s 厚度 13 110852遂Development of POP Eyes 1B Figure 'To solve the above problem 110852 5 201003866 (Package on Package) technology to provide another semiconductor package, including at least two packages i 6, each between the packages 16 The package member 16 has a substrate 160, a semiconductor substrate 161 disposed on the substrate 16 and electrically connected to the substrate 160, and a portion disposed thereon. The substrate 16 is mounted on the substrate 162 of the semiconductor wafer 161, and the conductive member 7 is disposed on the substrate 160. In addition, one side of the opposite stack of the lowermost substrate 16 is provided for externally connecting other electronic components. Solder ball 163 of the device. The height of each of the packages 16 is the sum of the heights of the substrate 丨6〇 and the package 162 covering the semiconductor wafer 161, and the semiconductor wafer 161 is disposed on the substrate 16 ,, forcing the height of the package 162 With the height of the conductor wafer 161, the height of the overall semiconductor package is high, so that the semiconductor package of the PGP technology is not easily made into a thin and light device, thereby limiting the application of the electronic product; Covered by the package material ι62, the semiconductor wafer is caused to be high in heat, which causes the semiconductor wafer to collapse and damage the semiconductor wafer 161. The problem is actually how to solve the problem of the above-mentioned conventional semiconductor package. SUMMARY OF THE INVENTION 4α is missing from the above-mentioned prior art, and the present invention provides a package substrate structure that reduces the package height. It is an object to provide another substrate structure of the present invention. A heat-dissipating sealing device II0852 6 201003866 • The structure of the invention is disclosed in the present invention. The invention has disclosed that the substrate substrate has a relative first and second surface, and the surface has a plurality of wire mats on the second surface and having a ball and having an opening penetrating the first and second surfaces;;=: on the second surface and sealing the opening, and the thickness of the metal plate; The metal plate area is slightly larger than the opening; and the::::: the first and second surfaces of the substrate have a corresponding opening prevention layer η, and the solder resist layer has a plurality of openings to correspond Each of the wire mats, ball pads and metal plates. Μ In the above package substrate structure, the substrate is a multi-layer package substrate; the metal plate is made of copper, and: 3: a dielectric layer is provided between the layers to make the metal plate partially embedded in the material ball. The sealing board structure of the plurality of contacts of the metal plate or the ball-fed ball may further comprise an electrical material, a semi-conductor (, a wire or a package material. The electrical contact pad may be provided on: 俾 power supply connection to - The semiconductor two-piece system can be accommodated in the opening and coupled to the opposite surface and the non-active surface of the gold, and the active surface has a plurality of electrodes connected to the working surface of the tit to be bonded to the metal plate; the wire can be electrically connected Filled in the opening, the surface of the package is covered, and the above-mentioned package substrate is wound. Π0852 7 201003866 One of the group groups. 曰,~ ^ The structure of the substrate is designed to be tight for the semiconductor. Produced to reduce the overall package height '· In addition, the thickness of the metal plate 22, _ ball pad, for the semiconductor wafer is firmly set to: anti-shi, and the use of metal material thermal conductivity characteristics, make Semiconductor cymbals can be hunted by metal plates [Embodiment] The following is a description of the embodiments of the present invention by those skilled in the art, and other advantages of the present invention can be easily understood by those skilled in the art from this disclosure.詈 2 Γ 2A and 2β diagrams are schematic cross-sectional views of the package substrate structure + conductor 曰曰 package of the present invention; including: substrate 20, metal plate 21, solder mask 22, semiconductor 曰 # ^ 〇 材 material 26. The cow lead-battery 23, the wire 25 and the substrate 20 described in the package are two or more sound-sealing substrates having completed the circuit layout, and the circuit layer inside or on the surface of the substrate is borrowed. The conductive vias are electrically connected to the vias (not shown). The substrate 2Q has opposite first and second surfaces 20a and 20b, and has first and second surfaces 20a and 20b on the substrate 2 a dielectric layer 2〇1, and a plurality of wire pads 2〇2 are disposed on the first surface dielectric layer 201, and a plurality of ball pads m are disposed on the dielectric layer 201 of the second surface, and have a penetrating The dielectric layer 201 and the opening of the substrate 20 are 200%. ^02 on the electricity or chemical sink _ into ^ 4 layer 2G2a' & liter connection structure of the electrical effect, and the surface at 110852 8 201003866 layer 2 0 2 a is recorded, put, gold, tin One of the group groups, such as nickel/gold (Ni/Au ' is formed by forming nickel first, then gold is formed), nickel immersion gold (Electroless Ni & Immersion Gold, ENIG), nickel-palladium immersion gold (Electroless Nickel) /Electroless pailadium/Immersi〇n Gold' ENEPIG), immersi〇n Tin (IT), and Direct Immersion Gold (DIG). The metal plate 21 is made of copper (cu) and is disposed on the dielectric layer 201 on the second surface 20b of the substrate 2 (as shown in FIG. 2A) or partially embedded in the dielectric layer 201 ( As shown in FIG. 2B, to seal one of the openings 200, and the thickness s of the metal plate 21 is greater than the thickness h of the ball pad 2〇3, the area of the metal plate 21 is slightly larger than the opening 2 The area is for carrying the semiconductor wafer 23. The solder resist layer 22 is disposed on the electrical layer 210 of the first and second surfaces 20a, 20b, and the solder resist layer 22 has a solder resist opening 220 corresponding to the opening 2, and the anti-solder layer The solder layer 22 has a plurality of openings 221 to correspondingly expose the wire pads 202, the metal plates 21 and the ball pads 2〇3. The semiconductor wafer 23 in the figure has an opposite active surface 23a and a non-"surface 23b" having a plurality of electrode pads on the active surface 23a, and the semiconductor wafer 23 is fixed by the adhesive layer 24 by the non-active surface 23b. The metal plate 21 of the 200 is electrically connected to the wire pad 2〇2 of the substrate 2 by the wire 5. The thickness s of the metal plate 21 is larger than the ball pad 2〇3 The thickness h is such that the semiconductor wafer 23 is stably disposed above the metal plate, and the thermal conductivity of the gold plate 21 is such that the semiconductor wafer is cooled by the metal 110852 9 201003866. The package 26 is disposed on the dielectric layer 201 of the first surface 2〇a of the substrate 20 and filled in the opening 2 to cover the semiconductor wafer 23, the wires 25, and the bonding pads 202. In the opening 221 of the solder resist layer 22 of the second surface 20b of the substrate 20, the exposed metal plate 21 and the ball pad 203 are attached to the solder balls 2r', wherein the solder balls on the metal plate 21 are It is used for heat, and the solder ball on the ball pad 2〇3 is used for external electronics. The present invention can reduce the overall package height by the design of the semiconductor wafer 23 placed in the opening 200. Compared with the m technology, the package material 26 of the packaged f-plate structure of the present invention does not need to match the height of the semiconductor wafer 23. The height of the overall package substrate structure is significantly reduced; in addition, since the semiconductor wafer 23 is placed in the opening 2, and the semiconductor wafer 23 can be dispersed by the metal plate 21 by the metal plate 2. Please refer to Figure 3 for a day. # a Shizheng. The outline of the package substrate structure should be shown in the schematic diagram. The structure shown in Figure 2 should be stacked up on the first surface of the substrate 20. "Sexual contact pad 204, and the user has a secret", and there is a ^ ^ ^ η φ ^ ^ contact pad 204 is connected with a conductive member 28, to be connected and electrically connected at least - semiconductor package 3 pieces. The semiconductor package is mounted on the substrate _, and is provided with a wire 3〇3, a package substrate 300, and a half-connected au, ηι of the package conductor 300. Again. The package substrate 300 is wrapped on the package substrate 300 and covered with the package material 3〇2 of the half-day group 301. In the other embodiments, the semiconductor package 3 can be replaced by a package to make the overall height lower; however, the variety of the person 30 is only known in the industry, and No, the above is not a technical feature of the present case, so it will not be described again. / From the above-mentioned stacked structure, the package structure of the overall g-sound of the bottommost semiconductor package substrate structure can be made thinner than that of the conventional technique, so that the overall stack can be augmented. Product, - the electronic product should not, the above-mentioned 'package substrate structure of the present invention by the substrate set open = set the person's main structure height is only the substrate's height two: Γ:: conductor wafer thickness, to effectively The metal that achieves the reduced height is copper and the thicker metal plate serves as the semiconductor thermal function. The above embodiments are intended to illustrate the principles of the invention and == are used to limit the invention. Anyone who is familiar with this skill is expected to: Do not violate the extensive text: the spirit of the spirit and the scope of the law, the above-mentioned examples are revised. (4) The scope of protection shall be as follows. Please refer to the patent specification [Simple Description of the Drawings] f 1A and 1B are the schematic diagrams of the semiconductor seals; the 2A and 2B diagrams are 4# ^ The cross-sectional view of the package is shown in Fig. 1 and the substrate structure is connected to the semiconductor. Fig. 3 is a cross-sectional view of the package substrate structure of the present invention, π 110852 201003866. [Main component symbol description] 10, 160 substrate 11 first semiconductor wafer 12, 163, 27, 27' solder ball 13 second semiconductor wafer 14 ' 25 ' 303 wire 15, 162, 26, 302 package 16 package 161, 23, 301 semiconductor wafer 17, 28 conductive member 20 substrate 20a first surface 20b second surface 200 opening 201 dielectric layer 202 wire pad 202a surface treatment layer 203 ball pad 204 electrical contact pad 21 metal plate 22 solder mask 220 Solder mask opening 221 Opening 12 110852 201003866 z^a Acting surface 23b Inactive surface 231 Electrode pad 24 Adhesive layer 30 Semiconductor package • 300 package substrate h ' s Thickness 13 110852