TW201001420A - Nonvolatile semiconductor memory and semiconductor device - Google Patents

Abstract

A semiconductor device includes a memory unit and a sense unit. The memory unit includes first and second nonvolatile semiconductor memories that cooperate to store a piece of information. The second nonvolatile semiconductor memory stores a logic state complementary to the first nonvolatile semiconductor memory. The sense unit reads the piece of information stored by the first and second nonvolatile semiconductor memories through a pair of first and second signal lines. Each of the first and second nonvolatile semiconductor memories includes at least a floating gate formed over a semiconductor substrate, a drain, and a source. For writing, a voltage is applied between the source and drain to inject charge into the floating gate, so that the charge is then accumulated in the floating gate. For erasing the charge accumulated in the floating gate, a voltage is applied between the semiconductor substrate and the drain or source, to generate band-to-band current which produce hot carriers in the semiconductor substrate. The hot carriers erase the electric charge accumulated in the floating gate.

Description

201001420 VI. Description of the Invention: [Technical Field] The present invention relates to a non-volatile semiconductor memory which can be rewritten in a unit structure of a germanium polysilicon layer which can be fabricated by a standard CMOS (complementary metal- 〇xlde semiconduct®) process. Components and semiconductor devices. [Prior Art] EEPROM (Electrically Erasable Programmable Read

Only Memory) is a non-volatile semiconductor memory that has been used for many purposes since the information is not lost after the power is turned off. For example, as a representative use of EEPROM, there is an IC card. Moreover, since it is convenient to rewrite at any time for visual use, the mask read-only memory (Mask R〇M) in the computer is replaced with EEpR〇M or flash memory. Further, in recent years, a system L SI or a buried type of so-called logical mixed memory in which a nonvolatile semiconductor memory is loaded into one of the logic 1C is required. Further, the analog circuit is incorporated as an adjustment switch for adjusting the analog circuit of high precision, and a small-scale nonvolatile semiconductor memory of several tens of thousands to several K bits is also required. However, non-volatile semiconductor memory is generally constructed using two layers of polycrystalline germanium or three layers of polycrystalline germanium. The process is more complicated than the standard cm〇s logic process and there are many steps. It is necessary to embed the non-volatile semiconductor memory with the standard logic. In the case of one wafer, there are problems in that the number of processes is large, the yield is also lowered, and the price (cost) of the product is increased. As a means for solving this problem, an EEPROM using one layer of polysilicon 4 201001420 has been disclosed (Patent Document 1). If this layer polycrystalline stone is used, the process can be reduced as compared with the conventional 2-layer polycrystalline process. [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei 10-289959. SUMMARY OF THE INVENTION However, in the above technique, since the second layer of polycrystalline stone used as the control gate is omitted, it is required to be buried in the floating layer by the diffusion layer. The control room is more complicated than the standard CM〇s process used in logic. Further, when the diffusion layer buried in a high concentration is oxidized, it becomes an inferior oxide film, which is unfavorable; It is a problem. In addition, it is complicated to require high power & search, write, and erase. The present invention is composed of the above problems, and the purpose thereof is to provide a two-layer standard CM0S process manufacturing layer of more than one layer. A non-volatile semiconductor memory device having a unit structure of a spar and a semiconductor device using the same. In order to solve the above problems, the semiconductor device of the present invention has a memory (four) error by a first non-volatile semiconductor The memory element and the storage are opposite to the first semiconductor memory device: the semiconductor memory device is stored, and the information is stored; and the second and second signal lines are stored in the first and second signal lines. Information of the second and second semiconductor memory devices; wherein each of the second and second non-volatile semiconductor memory devices includes at least a floating gate, a drain, and a source formed on the half substrate; As a write state, an electromigration is applied between the and the electrodes to inject a charge into the floating gate and accumulate; as a erased state, when the charge accumulated in the floating is erased, the conductor substrate is in the half 201001420 Applying a voltage to the drain or the source, enabling a hot carrier between the band and the band to be generated in the semiconductor substrate, and the hot carrier is used to erase the charge accumulated in the floating gate. Further, the present invention The second non-volatile semiconductor memory device has a drain connected to the second signal line, a source connected to the first control signal terminal, and a second non-volatile semiconductor memory device connected to the drain. The first signal line and the source are connected to the second The signal control terminal; the second control signal terminal and the second control signal terminal connected to the source of each of the second and second non-volatile semiconductor memory devices are independent of each other, during writing and erasing When using different potentials, they become the reference potentials when reading. ~ The special principle of the present invention is that the first non-volatile semiconductor memory device has a drain connected to the second signal line and the source is connected to The second control signal terminal; the second non-volatile semiconductor memory device has a drain connected to the first signal line, a source connected to the second control signal terminal; and a common connection 7 first control signal terminal Further, the present invention is characterized in that it further includes a second transistor and a drain connection of the ith non-volatile semiconductor memory device. The source and the source of the ith transistor are connected to the first control signal terminal; the drain of the second non-volatile semiconductor memory device is connected to the source of the 帛2 transistor and connected to the first source! a signal terminal; the first transistor is connected to the activation signal input terminal, the drain is connected to the second signal line, and the source is connected to the 帛1 non-volatile semiconductor memory device line; 201001420 The gate of the second transistor is connected to the activation signal input terminal, the drain is connected to the first signal line, and the source is connected to the drain of the second non-volatile semiconductor memory 7L; the common connection is The gi control signal terminal is a predetermined potential at the time of erasing and writing, and becomes a reference potential during reading; the first and second transistors are made by inputting an activation signal to the activation signal input terminal. In the on state 帛1 or the second non-volatile semiconductor 5 memory 7L is in an erased state, and when the charge accumulated on the floating gate is erased, electricity is applied between the semiconductor substrate and the gate or source. Μ, enabling the hot carrier between the band to generate a charge in the semiconductor substrate by the thermal carrier to erase the charge accumulated in the floating gate. Further, the present invention is characterized in that the first and second resistors are further provided, and the drain of the first non-volatile semiconductor memory device is connected to the second signal line, and the source is connected to the source through the 帛i resistor. i control signal terminal; the second non-volatile semiconductor memory element < the drain is connected to the first signal line, and the source is connected to the ith control signal terminal and the control signal terminal S through the second resistor It is a predetermined potential at the time of erasing and writing, and becomes a reference potential at the time of reading. Further, the present invention is characterized in that: the second non-volatile semiconductor memory device (the fourth non-volatile semiconductor memory device) is connected to the second signal line, and the source is connected to the first transistor crystal line. The second non-burst semiconductor memory cell strain $, B 1 丨 遐兀 遐兀 遐兀 遐兀 连接 连接 连接 连接 、 、 、 ϋ # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # And the gate of the electric body, the gate of the circuit is connected to the input terminal of the activated signal, and the source is connected to the control signal terminal; the gate of the second transistor is connected to The input terminal and source 201001420 of the activation (4) are connected to the first control signal terminal; the third and second transistors are activated by the input of the activation signal; the second control signal terminal, two wipes: And when writing, it is a predetermined potential, and becomes a reference potential at the time of reading. Further, the present invention is characterized in that the sensing unit includes a flip-flop circuit in which a power supply line is connected through a power supply transistor and holds a signal; and the flip-flop circuit controls the conduction state of the power supply transistor, A voltage is applied to the power source to maintain an output signal of the second and second non-volatile memory devices. Further, the present invention is characterized in that the sensor unit includes a flip-flop circuit, is connected to a power source through a power supply transistor, is connected to a reference potential through a grounding transistor, and is transparent to (four)-to-the second and second to the first line. Connected to the memory unit; and a signal amplifying unit that amplifies an output signal from the flip-flop circuit. Also: This is a semiconductor device with a combined memory and sensing unit.

The § 己 体 单元 ' 立 立 立 立 力 力 力 力 立 立 立 立 立 特征 立 特征 特征 特征 特征 特征 特征 特征 特征 特征 特征 特征 特征 特征 特征 特征 特征 特征 特征 特征 特征 特征 特征 IA 特征 IA 特征 IA IA IA IA The memory unit ′ includes a first part of the sub-gate, the dipole and the source formed on the semiconductor substrate. The H1 and the second non-volatile half (four) memory element are connected to the power supply by a transistor for transmitting power. The positive body element, ## / m and the second non-volatile semiconductor memory and heart:::::: when the charge of the floating gate is generated in the semiconductor substrate conductor substrate, the thermal carrier between the band energy bands is The half-loader, the flip-flop device and the hot-hot carrier erase the electricity accumulated in the floating gate. The power supply is provided with: a sensing portion, which is controlled by the activation signal to control the conduction state and the disconnection state of the body. Applying power to the positive 201001420 inverter circuit; a source line for connecting the sources of the second and second non-volatile semiconductor memory elements to each of the turns; and a line for the sensing portion Selecting a signal and transmitting the activated signal to each line; and a bit line for sensing the signal The information is transmitted to each column; the sense amplifier is provided with a reading means, and the signal outputted by the sensing portion is connected to each column of the bit line γ to read the bit line and the line specified by the non-volatile semiconductor Information stored in the state of charge accumulated by the floating gate of the memory component. Further, the semiconductor device of the present invention includes a memory unit in which a memory unit and a sensing unit are combined, and includes at least a matrix array in which the memory cells are arranged in a row and column direction and a sense amplifier; each of the memories The body sheet includes: a memory portion including: at least a first and a second non-volatile semiconductor memory device & and each of the first and second portions formed on the semiconductor substrate j 2 non-volatile semiconductor memory elements are connected in series, and are controlled in an on state or an off state to select or not select the first and second transistors of the second and second non-volatile semiconductor recording elements; The positive and negative devices connected to the power supply through the power supply transistor are used to hold the signal; the non-volatile semiconductor is recorded as the "component, which is the first state" 俨 2 'the crystal is turned on' in the first and second non-volatile semiconductors. The source and the pole of the memory element, and the inter-turn yoke are applied with a voltage to inject a charge into the float and accumulate, and the eraser accumulates in the first! The non-volatile semiconductor and the seventh of the floating gate of the β7& memory device are non-volatile semiconductors and the seventh, the second and second non-volatile semiconductors, and the enable band-energy band Sub-vc: the electrode is not applied between the pole or the source. The hot carrier is generated in the semiconductor substrate, and the charge accumulated in the floating is erased by 4 carriers; the flip-flop circuit has... 201001420 The sensing unit applies power to the flip-flop circuit by controlling the conduction state and the off state of the power supply transistor by power supply control; and the source line for the first and second non-volatile semiconductors The source of the memory component is connected to each row; the row line is configured to transmit a control signal for controlling the gates of the second and second transistors, the activation signal, and a selection signal of the sensing portion to each row And a bit line for transmitting information of the sensing part to each column; the sensing amplifier is provided with a reading means for connecting the signal outputted by the sensing part to the bit line of each column, according to the input to The signal of the line selectively blocks the non-volatile semiconductor And the sensing element portion of the bit line and read row line designated in the state of charge accumulated in the floating gate non-volatile semiconductor memory device of the information stored. Further, the present invention is characterized in that the memory portion includes an ith non-volatile semiconductor memory device and a non-volatile semiconductor memory having a logic state opposite to that of the 帛i non-volatile semiconductor memory device. The body component; the m-number holding unit includes: a sensing circuit having an activated signal input terminal, a signal for reading the memory portion by the input activation signal, and information for reading the sensing circuit and outputting the force item The flip-flop circuit is configured to: when the information of the memory unit is read, the pre-charging unit charges the signal holding unit and the amplification detecting unit, and amplifies and outputs the signal outputted by the signal holding unit. And the second non-volatile semiconductor memory device is a transistor structure, and "the floating, the immersed, and the source are formed on the semiconductor substrate. The respective sources are connected to the 帛! control signal terminal; as the write state' Applying a voltage between the source and the gate to inject a charge into the floating gate and accumulating it, and as an erased state, when the erase is accumulated on the floating 10 201001420, on the semiconductor substrate A voltage is applied between the drain or the source to enable a hot carrier between the band and the band to be generated in the semiconductor substrate, and the charge accumulated in the floating gate is erased by the hot carrier. Further, the present invention is characterized A memory unit comprising: a first non-volatile semiconductor memory device; and a second non-volatile semiconductor memory device having a logic state opposite to the 帛1 non-volatile semiconductor memory device; and a signal holding unit And connecting the memory unit through a pair of i-th and second signal lines, and maintaining and outputting information read from the memory unit by the flip-flops of the active circuit; the 帛i and the second non-volatile a semiconductor=memory element is a transistor structure, and is formed by a drain and a source formed on a semiconductor substrate, each source is connected to the first control signal material; and as a write state, between the source and the anode Applying electricity M to inject charge into the floating gate and accumulating; and in the erased state, applying a voltage between the semiconductor substrate and the gate or source when the charge accumulated on the floating gate is erased a hot carrier between the band and the band In the conductor substrate, the charge accumulated in the floating gate is erased by the hot carrier, and the seventh pole of the first non-volatile semiconductor chip Ms is connected to the first signal line, and the source is connected to the first a control signal terminal, the second non-volatile semiconductor memory device and the pole are connected to the (4) 2 signal line, and the source is connected to the control signal terminal, and the control signal terminal s is commonly connected, during erasing and At the time of writing, the predetermined potential 'becomes a reference potential at the time of reading, and the signal holding unit includes a sputum circuit' having a power supply transistor connected to the power supply side of the i-reactor circuit. Further, the present invention is characterized in that And a memory unit including a first non-volatile semiconductor memory device of the first 11 201001420 and a second non-volatile semiconductor memory device having a logic state opposite to the first non-volatile semiconductor memory device, and the first a second transistor in which the non-volatile semiconductor memory device is connected in series, and a second transistor in series with the second non-volatile semiconductor memory device; and a signal holding portion to have a flip-flop having an activation circuit The first and second non-volatile semiconductor memory devices are composed of a transistor, and are composed of a floating gate, a drain, and a source formed on the semiconductor substrate, and each source is connected to the third control. a signal terminal; as a write state, a voltage is applied between the source and the drain to inject a charge into the floating gate and accumulate, and as an erased state, the charge accumulated in the floating gate is erased, and the semiconductor is discharged Applying a voltage between the substrate and the drain or the source, enabling a hot carrier between the band and the band to be generated in the semiconductor substrate, and the charge accumulated in the floating gate is erased by the hot carrier; the memory portion is The drain of the second non-volatile semiconductor memory device is connected to the high-speed sensing amplification state through the second signal line, the source is connected to the drain of the first transistor, and the drain of the second non-volatile semiconductor memory device Connected to the high-speed sense amplifier through the second signal line, the source is connected to the drain of the second transistor, the gate of the second transistor is connected to the input terminal of the activated signal, and the source is connected to the second control Signal terminal 'this second The gate of the transistor is connected to the input terminal of the activation signal, and the source is connected to the ith control signal terminal. The ith control signal terminal is a predetermined potential during erasing and writing, and serves as a reference during reading. Potential, the signal holding unit is provided with an activation circuit, and the power supply transistor of the power supply side of the flip-flop circuit; the signal protection == the control signal given to the activation circuit will be stored in the non-volatile half 12 201001420 The information to be read is read and the information of the conductor memory component is amplified and detected for output. According to the present invention, in the semiconductor device of the present invention, and by borrowing and borrowing, the device is also provided with eight devices. § 己 部, eight non-volatile semiconductor memory devices, and # i # |卞汉 has the second non-volatile half of the 愔驹海第一1 non-swipping m + conductor memory component conductor 愔驹 ^ ^

Du Niu; the first and second non-volatile semiconductor symmetry element 2 includes at least a floating gate, a drain: and a source ' formed on a semiconductor substrate as a write state, and the source-drain Apply a voltage between the two to float and accumulate; and in the erased state, apply a voltage between the semiconductor substrate and the gate or source when the charge of the product is erased. a hot carrier between the strips is generated in the semiconductor substrate, and the charge accumulated in the floating gate is erased by the hot carrier; and the sensing portion is read and stored through a pair of first signal lines and second signal lines Information on the second and second non-volatile semiconductor memory components. Therefore, since the gate signal input is not provided, the polysilicon process of the second layer is not required. Therefore, in order to omit the process of embedding the gate layer = control gate in the lower portion of the floating gate, the conduction state is at the source _ bungee. Applying a voltage to inject a charge into the floating chamber and accumulating it; and in an off state, applying a voltage between the semiconductor substrate and the drain or source when erasing the charge accumulated in the floating gate, enabling band-energy A hot carrier between the strips generates a charge in the semiconductor substrate by erasing the charge accumulated in the floating gate, and the non-volatile semiconductor memory device can be realized by a standard logic CMOS process and the device is used. In a semiconductor device, a logic mixed memory can be realized easily and at low cost. 13 201001420 [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. [Operation Principle] FIG. 1A is a plan view showing one transistor constituting a nonvolatile semiconductor memory device used in an embodiment of the present invention, and FIG. 1B is a cross-sectional view of FIG. 1B showing the equivalent of g 1A at w lc . Circuit diagram. The non-volatile semiconductor memory device of Fig. 1C is composed of a floating gate FG, a drain D, and a source s formed on the semiconductor substrate SUB (potential Vsub) using a cell structure of a layer polysilicon. The floating gate FG is a charge holding region, and no electrode is provided, and a floating gate FG composed of polysilicon is formed on the gate insulating layer formed on the substrate SUB. Further, the drain D and the source S are respectively provided with electrodes on the metal contact piece through the diffusion regions ‘ formed on the substrate SUB. Figure 2 shows the equivalent circuit of the coupling system of the non-volatile semiconductor memory device shown in Figure 1 a to Figure 1c. It is assumed that the floating gate FG has a charge q, and since the overall charge amount of the system is Q, it becomes (Vsub - VFG) * C(FB) + (VD - VFG) * C(FD)

+ (VS ~ VFG) * C(KS) + (Vch - VFG) * C(FC) = Q where 'VFG, VD, VS, Vch are the potential of the floating gate FG and the potential of the drain d' source s The potential, the potential of the channel CH. Further, C (FB) is the capacitance between the floating gate FG and the substrate SUB, C (FD) is the capacitance between the floating gate FG and the drain D, and C (FS) is the capacitance between the floating gate FG and the source S, C (FC) is a floating gate 14 201001420

The capacitance between FG and channel CH. Here, if the sum of the capacitances is defined as CT (sum), Bay, J

C(FB) + C(FD) + C(F,S) + C(FC) = CT becomes

VFG = Vsub * C(FB)/CT+ VD* C{FD)/CT + VS* C(FS)/CT + Vch * C(FC)/CT-QI CT

Among them, Q/CT is the potential at which the charge is injected into the floating gate. Here, let Vsub = 0V (reference potential, the same below), Bay|J

VFG = {VD*C(FD) + VS *C(FS) + Vch *C(FC)}/CT-Q/CT Here, the ratio of each capacitor will be slightly different depending on the process, but it is rough. For C(FD): C(FS) : C(FC) = 0.1:0.1:0.8 degree.

Here, when the amount of charge in the floating gate FG is Q/CT = - ΔVFG, set CT=1, Bellow J

(VFG = 0AxVD + 0.\xVS + Q.^xVch + ^FG Here, the erasing of the nonvolatile semiconductor memory device of Fig. 1A to Fig. 1C is explained. The transistor constituting the nonvolatile semiconductor memory device The threshold of the channel CH is set to 0.5 V. The erase is set to VD = 8 V, VS = open. Since the source is extremely open, the depletion layer diffuses to the channel CH portion of the transistor due to the floating gate FG and the substrate SUB. The capacitance becomes very small, so after ignoring, the floating gate potential VFG (Erase) is set to ΔVFG=0, then 15 201001420 VFG{Erase) = 0.1 x FZ) = 0.1 x 8(K) = 0.8( K) · (Expression 2) After applying a voltage to the drain D, as shown in Fig. 4A, first, the electric field concentration of the depletion layer is generated near the drain D, and the so-called high-energy Band to Band (B to B) flows. The current produces pairs of holes and electrons. The hole with high energy (hot carrier) is loaded into a part of the floating gate FG. After the voltage is further increased, when the oxide film is relatively thick, the junction collapses before the flow current of the FN (Fauler · Nordheim). Current flows to the substrate SUB. Let this breakdown voltage be VBD. In addition, for the details of the band-to-band (B to B) current, refer to "Documentation: "Flash Memory Technology Manual", edited by: Sakaoka Fujio, Publisher: Science Forum, Inc., 1 993 August 1st, 5th, 1st edition, 1st brush release. Chapter 5, Section 2, Analysis of the inter-band tunneling phenomenon of non-volatile memory cells, P206~215". Further, in Fig. 4A, the horizontal axis represents the drain potential VD, and the vertical axis represents the drain current ID, and the floating gate potential VFG is used as a parameter to schematically indicate the change in the drain current ID when the drain potential VD is changed. Here, since B to B and the collapse are generated at a certain electric field, they are dependent on the potential of the floating gate FG. As shown in Fig. 4A, the VBD also becomes low when the VFG is low, and the VBD also becomes high when the VFG is high. Explain the erase of the charge accumulated in the floating gate. At the potential difference between the gate and the drain, the critical potential for generating B to B is 5V. At VD = 8V, the floating gate potential VFG is implanted and erased before it becomes 3V. In other words, the erased hot carrier is injected. Since the initial VFG is 0.8V, 16 201001420 is 3V after erasing, so the amount of change ΔVFG(E) during erasing becomes +2.2V. On the other hand, the write system is VD = 5V and VS = 0V. At this time, the state before writing is usually the erased state, and there is a hole in the floating gate FG. Since the transistor is in an on state, the channel operates in a saturated region. Therefore, assuming that the channel area is about half, the floating gate potential VFG (Program) at the time of writing becomes VFG (¥r ogram) = 0.1 x FZ) + 0.8 χ ΡΊ) x 0.5 (Expression 3) according to (Formula 1). 0.1 x 5(V)+ 0.8 x 5(F)x 0.5 = 2.5(F) "- Generates hot electrons for writing. Here, since the threshold of the transistor is 0.5 V, the potential VFG of the floating gate FG becomes 0.5 V, and the current does not flow any more, and the writing is terminated. At this time, since the gate voltage is changed from 2.5 V to 0.5 V, the amount of change ΔVFG (P) at the time of writing becomes -2.0 V. Referring to Fig. 3, the transistor characteristics of this erase and write state will be described. In this figure, the horizontal axis is the floating gate potential VFG, and the vertical axis is the current ID of the drain D. In the three states of erasing, neutral, and writing, the gate current when the floating gate potential VFG is changed is schematically indicated. A chart of changes in ID. Next, a description of the reading is performed. The reading system is set to VD=1V and VS=0V. At this time, the floating gate FG has a charge of ΔVFG, and the floating gate potential VFG (Read) at the time of reading becomes

VFG(RQad) = 0.IxVD + O.Sx Vch x 0.5 + AVFG When “0” is read, Vch=0V, the floating gate potential VFG (“0”) when “0” is read. , becomes 17 201001420 FFG("0") = 0.1 x 1(F) + AFFG (Formula 4-1) On the other hand, when reading "1", since the channel is turned on, Vch==lv, read " 1 ''time floating gate potential VFG (" Γ ), becomes

FFG('T')= 0.1 X 1(^)+0.8 X l(F)x 0.5 + AVFG When reading, 'electronics _ △ 2.0V have been injected in the floating gate FG during writing, therefore, according to 4_丨), read the floating gate potential VFG ("〇") when "“", become ah 7 ("0'') = 0_ thing) -2 摩) = -1 bee) (Formula 4-2 On the other hand, when "1" is read, since there is a hole Δ2.2V in the floating gate FG at the time of erasing, the floating gate potential VFG at the time of "丨," is read according to (Formula 4_2) ( "1"), the action of becoming KFG ("1") = 0.1 (F) + 0.8 X 1 (F) x 0.5 + 2.2 (F) = 2.7 (F) is organized in Fig. 4B. In addition to the non-volatile semiconductor memory device, the operation of the drain and the source can be set to be opposite to each other. [Embodiment 1]

(Part 2), 202 (2nd - 20th (first non-volatile semiconductor memory cell non-volatile semiconductor memory device) memory unit 18 201001420 200. SRAM part 1 is used for sensing and locking The memory unit 200 is a memory unit that can be written and erased. The SRAM unit 1 includes a PM〇s transistor ι〇1, and is input to the SRAM unit 1活性Activating and sensing/determining the activation signal (SET) of the data of the memory unit; PM〇s transistors constituting the latch unit 1〇2, 1〇3, NMOS electric Japanese body 1〇4, 1〇5; and transfer gate nm〇S transistor 1〇6,

107, for reading the data of the memory unit to the outside. Further, the memory unit 200 includes nonvolatile semiconductor memory elements 2〇1 and 202, and stores data indicating the opposite logic. The connection between the SRAM unit 1 and the memory unit 2A will be described. In the SRAM portion, the body 103 is connected to the transistor 105, and the phaser is connected to form a flip-flop circuit. The transistor 102 is connected to the transistor 1〇4 and the transistor to serve as an inverter, respectively. Again, these 2 counters

That is, the gate of the transistor 102 is connected to the gate of the transistor 104, and the source is connected to the drain of the transistor 104. The source of the transistor 104 is connected to a reference potential. Moreover, the gate electrode of the transistor 103 is connected to the pole electrode 105 of the electro-cardiac core 5, the source of the source transistor 105 is connected to the source of the transistor H 102, and the gate is connected to the gate. The idler and the source of the transistor 102 are connected to the base, and the inverter is combined. The crystal (8) is connected to the power supply...

々J, that is, the gate of the electric crystal f P-characterized signal SET is connected to the live electrode, the pole is connected to the power source, and the source is connected to the drain of the transistor 102, 103 of 201001420. Further, the transistor 106 and the transistor 1 are connected to the word line data line DL and the data line inversion signal line DLB. The gate of the transistor 106 is connected to the word line WL, the drain is connected to the data line DL, and the source is connected to the source of the transistor 1 〇2. The gate of the transistor 107 is connected to the word line WL, the drain is connected to the data line inversion signal line DLB, and the source is connected to the source of the transistor 丨〇3. The non-volatile semiconductor memory elements 2 and 2 of the memory unit 200 are connected to the SRAM unit 1 through the signal lines Bit and BitB. The source of the non-volatile semiconductor memory device 2G1 is connected to the control signal terminal s, and the drain electrode is connected to the gate terminal of the transistor 102 of the 8& The non-volatile semiconductor § 己 兀 2 2G2 < source is connected to the control signal terminal SB, the drain transmission signal, the line Bh is connected to the gate terminal of the transistor 1 0 3 of the sram portion (10). The operation of the memory unit 2〇〇 will be described with reference to Fig. 5B. The write operation, the erase operation, and the read operation are sequentially shown in FIG. 5B. During the write operation, the input terminal data line DL of the word line WL and the activated signal set respectively enters the potential of 2V. 'The data line inverts the signal line b and inputs the potential of ον. 'Data line DL, data line inversion The potential of the signal line is transmitted to the signal line and the line line Bit through the transfer transistor 1G6 & 1G7, and the potential of the signal line BitB is 〇v. - After the potential of B 8 V is applied to the control terminal s and the control signal terminal a, the non-volatile semiconductor memory device 2 〇i 20 201001420 becomes the write state 'non-volatile semiconductor memory device 202 becomes smeared In addition to the dissimilarity, electrons are injected into the floating gate of the non-volatile semiconductor memory device 2, and the floating gate of the non-volatile semiconductor memory device 202 is injected into the gate. On the other hand, in the erasing operation, conversely, a potential of 0 V is applied to the data line DL. After the potential of the data line inversion signal line is given 2 V, the potential of the signal line Bit becomes 透过 through the transfer transistors 106 and 107. v, the potential of the signal line BitB becomes iv. At this time, after the potentials of S = 8V and SB = 5V are applied to the control signal terminal S and the control signal terminal SB, the nonvolatile semiconductor memory device 2〇1 becomes the erased state, and the nonvolatile semiconductor memory device 202 becomes Write status. The reading operation of the data set in the memory unit 2〇〇 will be described with reference to Fig. 6 . Fig. 6 is a timing chart showing the reading operation of the memory unit 2A. 6 shows, in chronological order, the voltage changes of the respective signal lines of the input terminal of the activated signal set, the word το line WL, the signal line Bit, the BitB, the data line DL, and the data line inversion signal line D L B . The case where the memory unit 200 performs writing, that is, the case of reading "〇,, data. First, the voltage of the data line DL and the data line inversion signal line DLB is precharged to 2V (precharge). The terminal voltage of the input terminal of the control signal terminal S and the control signal terminal SB is set to S = SB = 〇V. Since the time t1, the terminal voltage of the input terminal of the activation signal SET is gradually changed from 2V to 〇v. The potential of the activation signal set 21 201001420 gradually changes from 0V to 0V. Thereby, the SRAM unit 100 is activated, and the signal lines Bit and BitB are charged. The voltages of the signal lines Bit and BitB gradually become south. When the "〇" data is written, the non-volatile semiconductor 5 memory element 210 is turned off, and the non-volatile semiconductor memory element 202 is turned on. Thus, the potential of the signal line Bit drops to "L ( On the low side, the potential of the signal line BitB is charged, the signal line Bit is set to "0", and the B signal line BitB is set to "丨" (time t12). When the voltage of the word line WL is set to 2 V at time t13, the transfer transistors 106 and 07 are turned on, the voltage of the data line DL becomes, and the voltage of the data line inversion signal line DLB becomes 2V, and the reading ends. Take action. When the memory unit 200 has been erased, that is, when the "丨" data is read, the signal indicating each state becomes the opposite action, and the voltage of the signal line Bit is 2V. The voltage of the signal line BitB is 〇v, the data line The voltage is 2v, and the voltage of the data line inversion signal line DLB becomes 〇v, and the reading operation is ended. The terminal voltage of the input terminal of the activation signal SET starts from "η" to "L" to the voltage of the data line D1 and the data line inversion signal line dlb, that is, the period from time t1 to U3 is the sensing period.疋 The advantage of this configuration is that the composition can be made simple. Further, the portion to which the high voltage is applied is a part of the signal terminal S and the control signal terminal SB connected to the nonvolatile semiconductor device 2, 1, 2, and SRAM # 100 (sensing portion). Since a high voltage is not applied, the thin portion 22 201001420 can be used for the sense/detail portion, for example, the μ/m process of the logic standard process is used in the SRAM portion 100 (sensing portion), and the non-volatile semiconductor memory device is also used. 2〇丨, I/O transistor process using logic standard process (using voltage 3~5V, real & 8V~9V)[This way, it can provide simple and tiny non-volatile memory ^ [Implementation 2] Fig. 7A, Fig. 7B, and Fig. 7C show a second embodiment which is modified from the first embodiment. Figure 7A is a block diagram of Embodiment 2. f

In the part which is changed in the second embodiment, the same reference numerals will be given to the unmodified portions, and the description will be omitted with reference to the first embodiment. The SRAM unit 100 (sensing unit) shown in the first embodiment is the same, but in the memory unit 200' non-volatile semiconductor memory device 2 (i-non-volatile semiconductor memory device) and 202 (second non- The source of the volatile semiconductor memory device is separated from the control signal terminal SB, but in the memory portion 200a of the present embodiment, the sources of the non-volatile semiconductor memory devices 201 and 202 are respectively connected to When the common control signal terminal S ° is set to be in common, the control signal terminal voltage VS for simultaneously establishing the write operation and the erase operation needs to be optimized. Figs. 7B and 7C show an example of changing the applied voltage of the control signal terminal voltage vs. Fig. 7B shows a case where the voltage of the control signal terminal is 7V. The cancer is recognized again (Formula 2), (Formula 3), (Formula 4-1), and (Formula 4-2). Here, since the pole is interchanged with the source, VS replaces VD. 23 201001420 becomes the initial state of the floating gate FG at the time of erasing, according to (Formula 2) = 〇_ 1 X 7 (" = 0· 7 (4) The final state of the floating gate FG is +1 due to becoming 7V-5V=2V · 3Υ. Therefore, the amount of change becomes the initial state of the floating gate FG when it is changed, according to (Formula 3) VFG(?rogram) = 0.1 x 7(F) + 0.8 x 7(F) x 0.5 = 3.5 ^^ The final state is erased at FG=2V, so the amount is +1.5V when FG=2v is set. According to (Formula 4-1}, according to (Equation 4-2), therefore, the floating gate FG is read. The initial state becomes FFG("0")=0.1 x 1(F) -1.5(F)=-1.4(F) and the initial state of the floating gate FG of 'reading '1' becomes = 〇·1X) + 〇·8 x 宁)χ 5 +1 3(F) = 1 ·8(κ) Therefore, as the threshold value of the non-volatile semiconductor memory elements 2〇1, 2〇2 is 0.5V, It can be enough to move. Fig. 7C shows the case where the control signal terminal voltage vs is set. The initial state of the floating gate FG at the time of erasing, according to (Formula 2), becomes VFG (Erase) = 0.1 x 6 (F) = 〇.6(F) 24 201001420 The final state of the floating gate FG is 6V_5V=1 v Therefore, the amount of change becomes +0.4V. Further, the initial state of the floating gate FG at the time of writing becomes VFG (?r ogram) = (1) x 6 (F) + 〇.8 x 6 (F) x 0.5 = 3.0 (V) according to (Expression 3). The final state is erased at FG = 1 V. Therefore, when FG = 1 v, the amount of change becomes -2.0V. Therefore, take the initial state of the floating gate FG of 0, and according to (Formula 4_i), become KFG("0")=0.1(F)x 1(F)- 2.0(7)= -1.9(F) 'The initial state of the float FG of reading 1 is FFG('T') = 〇. 1X l(F) + 〇.8 X l(F)x 0.5 + 0.4(F according to (Formula 4-2) ) = 0.9 (K) Therefore, since the threshold ' of the non-volatile semiconductor memory elements 20 1 and 202 ' is 0.5 V, the margin of the "丨" reading operation becomes severe (the allowable range of reading) Narrowed). However, in this case, if the threshold values of the non-volatile semiconductor memory devices 20 1 and 202 are set to be around 0 V, they can be read. When the source is extremely common, there is an optimum voltage near VS=6V to 7V. [Embodiment 3] Another embodiment is further shown in Fig. 8. In the present embodiment, the memory cells of the second embodiment are arranged in a plurality of matrix shapes to constitute a memory array unit. That is, the memory cells mi i to Mmn each include an SRAM unit 1 (sensing unit) and a memory unit 2a, and the internal details are described in the second embodiment. The same portions are denoted by the same reference numerals, and the description is omitted. The memory cell array is provided with (mxn) memory cells M1丨 to Mmn and n sense amplifiers 800-1 to 8〇〇-n. Further, the word lines WL1 are shared, and the memory cells M 丨} to Min' are arranged such that the word lines WLm are common ‘memory units Mml to Mmn. Further, the data lines DL1 and DLB1 of the Mil~Mml are connected in common, and the data lines DLn and DLBn of the Mln~Mmn are commonly connected. Further, the source is commonly connected in the direction of the word line, and each becomes the source line s丨~

Sm. The terminals of the activation signal SET for activating the SRAM portion 100 are also connected by gate lines SET 1 to SETM in the word line direction. The data lines DL1, DLB1 to DLn, and DLBn are connected to the sense amplifiers 800-1 to 800-n, respectively. The word lines WL 1 to WLm (row lines) are used to supply selection signals selected for each of the SRAM sections 100 of each row to the signal lines of each of the SRAM sections 1A. The gate lines SET 1 to SETM (row lines) are used to supply the activation signal SET that activates the SRAM unit 1 to the signal lines of each of the SRaM units 1 .

The data lines DL1, DLB 1 to DLn, and DLBn are used to transmit information read from the SRAM 26 201001420 part 100 or written information to the signal lines of each column. The source lines S 1 to Sm (line) are used to supply write/erase. The control signals for reading the information of the memory unit 200a are supplied to the signal lines of each line. In this array configuration, for example, the memory cells M1丨 to Mln selected by the word line WL1, the gate line SET1, and the source line si can be simultaneously written/erased or read, so that a so-called full page can be performed. Overwrite, full page read, high speed rewrite, high speed read. [Embodiment 4] Embodiment 4 of the embodiment of the embodiment is shown in Fig. 9. In the portion changed in the fourth embodiment, the same portions are denoted by the same reference numerals, and the description will be omitted. Although the SRAM unit 1 (sensing unit) shown in the first embodiment is the same, in the memory unit 200, the nonvolatile semiconductor memory device 2 (first non-volatile semiconductor memory device) and 202 (the first) The source of the non-volatile semiconductor memory device is separated from the control signal terminal SB and the control signal terminal SB, and the non-volatile semiconductor memory devices 201 and 2 are directly connected to the sram unit 100. The memory part 2〇〇b of the form is different. For the connection of the sources of the non-volatile semiconductor memory devices 201 and 202 to the common control signal terminal S, reference is made to the description of the memory unit 2 0 0 a shown in the second embodiment. The memory unit 200b is provided with a NM〇s transistor 203 for data transfer between the SRAM unit 100 and the non-volatile semiconductor memory devices 201 and 202, and 204. The drain of the non-volatile semiconductor memory device 20 1 is connected to The source and source of the transistor 27 201001420 203 are connected to the control signal terminal $. Non-volatile semiconductor memory The drain of the body 7L member 202 is connected to the source of the battery 204, and the source is connected to the control signal terminal s. The gate of the transistor 203 is connected to the input terminal of the transfer signal Df, and the drain is connected to the SRAM portion 1B through the signal line BltB. The gate of the transistor 204 is connected to the input terminal of the transfer signal coffee and the pole transmission line Bit is connected to the SRAM unit 1 〇〇. The transfer signal selected during writing, erasing, and transferring the data of the non-volatile semiconductor memory devices 2〇1 and 202 to the SRAM is input to the transistors 2〇3 and 2〇4 as "H". The gate. In this configuration, although the size of the memory unit is slightly increased, after the memory material is transferred to the SRAM unit, the non-volatile semiconductor memory elements 201 and 202 are inputted from the SRAM unit 1 because the transfer signal TRF is input "1". (/Separate, the voltage is not supplied to the drain, no unnecessary voltage is applied, and there is an advantage of improving reliability. [Embodiment 5] Another embodiment 5 is further shown in Fig. 10. In the embodiment, the memory unit ΜΑ 11 to MAmn is substituted for the memory unit M of the memory cell array shown in the third embodiment.丨~Mmn. The memory cell array' has (mxn) memory cells mai 1 to MAmn and n sense amplifiers 800-1 to 800-n. Memory cells Mil~Mmn, and memory cells MA11~MAmn 28 201001420 is different in the form of the memory unit. The memory unit Μ 1 1 to Mmn includes the SRAM unit 100 (sensing unit) and the memory unit 200a, but the memory units MA11 to MAmn are provided with the SRAM unit 100 (sensing And the memory unit 200b. That is, the memory unit included in the memory unit ΜΑ 11 to MAmn is the same as the memory unit shown in the fourth embodiment. The portion that is changed in the fifth embodiment is not changed. The same reference numerals will be given to the third and fourth embodiments, and the description will be omitted. The data stored in the memory cells MA11 to MAmn can be read in batches. For example, the transfer signals TRF 1 to TRFm for data transmission are set to "L". Therefore, the memory cells connected to the row lines of the "L" input to the transfer signals TRF1 to TRFm can be selected. Therefore, if the memory cells are separated from the SRAM portion 100, the memory can be In the same manner as the SRAM unit 100. When the entire memory unit simultaneously performs data transfer, the current flowing into the SRAM unit 100 is excessively concentrated, and a large current flows. In this case, if the activation signal SET is activated to the signal SET The input timing of the input terminals is sequentially shifted, and the activation timing of each of the memory cells MA11 to MAmn is shifted, and the peak current can be suppressed. [Embodiment 6] FIG. 11 is changed from the second embodiment. In the embodiment which is changed in the sixth embodiment, the same reference numerals will be given to the unmodified portions, and the description will be omitted with reference to the second embodiment. 29 201001420 A high-sensitivity sense amplifier 300 (sensing unit) is provided instead of the implementation. The SRAM unit 100 is shown in the second embodiment, and the memory unit 200a is the same, and is connected to the high-sensitivity sense amplifier 30A via the signal lines Bit and BitB. The high-sensitivity sense amplifier 300 provided in place of the SRAM unit 100 is shown. The high-sensitivity sense amplifier 300 includes pre-charge PMOS transistors 301 and 302, sensing NMOS transistors 303 and 304, a sense amplifier activating NMOS transistor 305, and data for sensing ( Read) Transfer transistors to data lines 3〇6 and 3〇7. The gate of the transistor 301 is connected to the input terminal of the precharge signal Pre. The drain is connected to the power source, and the source is connected to the signal line Bit. The gate of the transistor 302 is connected to the input terminal of the precharge signal Pre, the pole is connected to the power source, and the source is connected to the signal line BitB. The gate of the transistor 303 is connected to the drain of the signal line BitB and the transistor 304, and the source is connected to the drain of the transistor 3〇5. The gate of the transistor 304 is connected to the drain of the signal line Bit and the transistor 3〇3, and the source is connected to the drain of the transistor 3〇5. The gate of the 3B body of the 3B body is connected to the wheel-in terminal of the sense amplifier activation signal (hereinafter referred to as "sensing signal SEN"), and the source is connected to the reference potential. The gate of the transistor 306 is connected to the word line WL, the drain is connected to the data line DL, and the source is connected to the drain of the transistor 3〇3. The gate of the transistor 307 is connected to the word line WL, the drain is connected to the data line inversion signal line DLB, and the source is connected to the drain of the transistor 3〇4. The operation will be described with reference to Fig. 1 . 30 201001420 This figure is a timing chart showing the operation of the configuration shown in FIG. First, at time m, when the "charge signal PRE becomes "L" at the wheel input terminal of the precharge signal PRE, the transistor 3〇ι & 3〇2 is activated, and the signal lines Bit and BitB are gradually charged. "Ή. At this time, the input terminal of the character line milk for transmitting the sensing terminal SEN and the sensing data to the data line DL and the data line inversion signal line _ is input "L". The selection signal that is inserted into the sense signal and the word line WL becomes "l".

In addition, the signal lines DL and the data line reversal signal lines are gradually charged to become "H" in conjunction with the signal lines charged by the transistors 301 and 302. The charging of the data line DL and the data line inversion signal line DLB is pre-charged in the same order as the pre-charge signal pRE by another data line pre-charging circuit. Regarding the data line precharge circuit, the precharge circuit 600 and the like shown in the next embodiment can be applied. The detailed description will be described later. At time t22', "n" is input to the input terminal of the precharge signal PRE, and the precharge signal PRE becomes "Η". The charging of the transistors 301 and 302 is stopped, and the pre-charging is completed. Here, the signal input from "l" gradually becomes "Η" at the input terminal of the sensing signal SEN, and since the sensing signal s EN is gradually changed from "L" to "Η", the sensing of the high-sensitivity sense amplifier 300 is performed. The amplifier is activated. At this time, the data written in the memory unit 200 is "", the data, since the non-volatile semiconductor memory device 20 1 is in the off state, 202 is in the on state, and the common source S is the reference potential (0 V). The current flows through the non-volatile semiconductor memory device 202 at the common source s, and the small voltage difference between the signal line Bit 31 201001420 and the BitB cannot be detected, which may cause a malfunction. To avoid malfunction, the rising waveform of the sensing signal SEN is as shown in the figure. As shown, it needs to rise slowly. Ideally, the voltage of the input terminal of the sensing signal SEN is preferably set near the threshold of the transistor 305 to cause the transistor 305 to operate at a low current. However, the operating current of the transistor 305 In relation to the sensing speed, the sensing speed is slowed down when the transistor 3 〇5 is operated with a low current and the current is limited. At time t23, the input terminal of the sensing signal SEN is input ΓΗ", and the sensing signal SEN becomes " H". During this time, the potential of the signal lines Bit and mtB is determined. At time t24, after "Η" is input to the word line WL in the state where the potentials of the signal lines Bit and BitB are determined, the word line WL becomes "η". Since the word line WL becomes "Η", the transistors 306 and 307 are activated and charged by the signal lines Bit and BitB 'by this' data line DL and the data line inversion sfl line DLB potential is determined to 'end reading action. [Embodiment 7] Fig. 13 shows Embodiment 7 in a form modified from Embodiment 6. In the portion changed in the seventh embodiment, the same portions are denoted by the same reference numerals. The description of the sixth embodiment will be omitted. A high-sensitivity sense amplifier 400 (signal holding unit) in place of the high-sensitivity sense amplifier 3 shown in the sixth embodiment, and a precharge circuit 6 (precharge unit) and an amplifier unit 700 (amplification detecting unit) . Further, the memory unit 2A is the same, and is connected to the high-sensitivity sense amplifier 400 through the signal lines Bit and BitB. The high-speed sense amplifier 400 includes sensing NMOS transistors 40 1 and 402, sense amplifier activating NMOS transistors 403 and 404, and 32 201001420 to transmit (read) the sensed data to the data line DL and The data line inverts the transfer transistors 405, 406 of the signal line DLB. The gate of the transistor 40 1 is connected to the drain of the signal line BitB and the transistor 402, and the source is connected to the drains of the transistors 403 and 404. The gate of the transistor 402 is connected to the drain of the signal line Bit and the transistor 401, and the source is connected to the drains of the transistors 403 and 404. The gate of the transistor 403 is connected to the input terminal of the sensing signal SEN, and the source is connected to the reference potential. The gate of the transistor 404 is connected to the input terminal of the sensing signal SENd, and the source is connected to the reference potential. The gate of the transistor 405 is connected to the word line WL, the drain is connected to the data line DL, and the source is connected to the drain of the transistor 40 1 . The gate of the transistor 406 is connected to the word line WL, the drain is connected to the data line inversion signal line DLB, and the source is connected to the drain of the transistor 402. The precharge circuit 600 includes transistors 601, 602, and 603. The gate of the transistor 60 1 is connected to the input terminal of the precharge control signal PRE, the drain is connected to the power source, and the source is connected to the data line DL. The gate of the transistor 602 is connected to the input terminal of the precharge control signal PRE, the drain is connected to the power source, and the source is connected to the data line inversion signal line DLB. The gate of the transistor 603 is connected to the input terminal of the precharge control signal PRE, the drain is connected to the data line DL, and the source is connected to the data line inversion signal line DLB. An embodiment of a high-sensitivity sense amplifier 33 201001420 400 that replaces the high-sensitivity sense amplifier 300 is provided. The difference between the high-sensitivity sense amplifier 400 and the sixth embodiment shown in Fig. 11 is that the precharged transistors 301 and 302 included in the high-speed sense amplifier 300 are deleted, and the activated transistors are again separated into 403 and 404. Further, the precharge circuit 600 is provided only on the data line DL and the data line reverse signal line DLB side. Further, after the precharge circuit 600' inputs "L" to the input terminal of the input precharge control signal pre, the precharge control signal Pre becomes "L". Thereby, the data line DL and the data line reverse signal line DLB can be charged through the transistors 601, 602 '. The transistor 603' is activated simultaneously with the transistors 601 and 602, and functions to balance the charge potentials of the data line DL and the data line inversion signal line D]LB. Further, the amplifier unit 700 > is an amplifier for further reading the data transmitted through the data line DL and the data line inversion signal line DLB at high speed, and a circuit for latching the data to be read. The active transistor of the speed sensing amplifier 400 is composed of a transistor 403 that performs an initial sensing operation (sensing 丨) and a transistor 404 that performs the sensing operation (sensing 2). Next, the operation will be described with reference to Fig. 14. This figure is a timing chart showing the operation of the configuration shown in FIG. First, pre-charging starts at time t31, and inputs "input" at the input terminal of the pre-charge signal, the sensing signals SEN, and SENd, "pre-charge signal coffee, sensing signal § SENd" When it becomes "L", the word line WL becomes. 34 201001420 406 becomes conductive, pre-charge circuit 600

Thereby, the transistors 405 and 4 are also operated in a charged state. The precharge circuit 600 pre-sets Bit and BitB is also charged.

SEN becomes "Η" The precharge circuit 600 ends the precharge. Further, the potential is slightly lower than the level of the Η", because the potential of the word line WL is "η" in the word line WL, and the input 406 is turned off. Further, the potential of the "Η" level is sensed. When the level is slightly lower, the transistors 405 and 40 input the signal SEN at the input terminal of the sensing signal SEN to become "η". At this time, the transistor 403 is made to operate at a constant current, or the transistor having a small capacity of the transistor is used to reduce the drain current. Thereby, the sensitivity of the sensing operation is increased, and the small potential difference between the signal lines Bit and BitB is expanded. Input "η" at the input terminal of the sensing signal SEN, and the sensing signal SEN becomes "Η". After the potential difference between the signal line Bit and BitB is increased to some extent, at time t33, "H" is input to the input terminal of the sensing signal SENd, and after the sensing signal SENd becomes "H", the potentials of the signal lines Bit and BitB are rapidly determined. Here, "η" is input to the input terminal of the word line WL, and the potential of the word line WL becomes "H", and the transistors 405 and 406 are completely turned on. The potential of the 'data line DL' and the data line inversion signal line DLB is determined. The determined potential is input to the amplifier unit 7A, and the amplifier unit 700 high speed 35 201001420 determines that the data is latched and the reading is completed. [Embodiment 8] Embodiment 8 of the embodiment modified in the seventh embodiment is shown in Fig. 15. In the part changed in the eighth embodiment, the same portions are denoted by the same reference numerals. The description of the seventh embodiment will be omitted. The high-speed sense amplifier 400 and the precharge circuits 600 and 700 shown in the seventh embodiment are the same, but the memory unit 2〇〇c is different from the memory unit 200a. The source of the non-volatile semiconductor memory devices 2〇丨 and 2〇2 in the memory unit 200a' is directly connected to the common control signal terminal s, but is connected to the common control signal terminal 8 through the resistor in the memory unit 200c'. . The memory unit 200c further includes resistors 2〇5 (first resistor) and 2〇6 (second resistor)'. The source passivation resistors 205 and 206 of the nonvolatile semiconductor memory devices 2A and 2〇2 are connected to the control unit. Signal terminal s. Since the resistors 205 and 206 are provided, even if the control signal terminal S is a common terminal, a sufficient operation margin (reading tolerance range) can be secured. As described in the second embodiment, after the control signal terminal s is a common terminal, the write erase voltage needs to be set to about 6V to 7V. Therefore, there is a case where the amount of injection of electrons or holes is small, and the read margin is reduced, and it is necessary to pay attention to the optimization of the voltage. In the present embodiment, for example, the nonvolatile semiconductor memory device 2〇1 is written (electron injection), and the nonvolatile semiconductor memory device 2〇2 is erased (hole injection), and the control signal terminal is considered. S applies 8V. For writing non-volatile semiconductor memory elements 2〇1, due to the flow 36 201001420

The current of the moving hot electrons is about La, so the source of the non-volatile semiconductor body element 201 is applied 6V. On the other hand, since the non-volatile semiconductor memory element 202 that is erased does not flow current, it is non-volatile. The source of the semiconductor memory device is applied with 8V. f

"Therefore, the voltage at the time of writing is as shown in Fig. 7C^6V. When reading 0-inch, the sluice gate becomes -1.9V, and the voltage at the erasing is as shown in the case of 8V in Fig. 4B. When reading "i", float fg to +2U to take "〇", read, and 1 "all to ensure sufficient margin. [Embodiment 9] Embodiment 9 which is a modification of Embodiment 2 is shown in Fig. 16. In the part changed in the ninth embodiment, the same reference numerals are attached to the unaltered portions. The description will be omitted with reference to the second embodiment. A high-sensitivity sense amplifier 500 (signal holding portion) in place of the SRAM portion 1 (sensing portion) shown in the second embodiment is provided. Further, the memory unit 2A is the same, and is connected to the high-sensitivity sense amplifier 5A via the signal lines Bit and BitB. An embodiment in which a high-sensitivity sense amplifier 5A that replaces the SRAM portion 1 is provided is provided. The form of this figure is a high-sensitivity, high-speed sense amplifier as the local sensitivity sense amplifier 500, and a high-sensitivity and high-speed sense amplifier function' has a latch function. The high-sensitivity sense amplifier 5A is provided with PM〇s transistors 501, 502, 503, 504, and 505. The gate of the transistor 501 (power supply transistor) is connected to the terminal of the activation signal SET, the drain is connected to the power source, and the source is connected to the drain of the transistor 5〇2 and 37 201001420 503. The gate of the transistor 502 is connected to the source of the signal line Bit and the transistor 503. The gate of the transistor 503 is connected to the source of the signal line BitB and the transistor 502. The gate of the transistor 504 is connected to the word line WL, the drain is connected to the data line DL, and the source is connected to the source of the transistor 502. The gate of the transistor 505 is connected to the word line WL, the drain is connected to the data line inversion signal line DLB, and the source is connected to the drain of the transistor 503. Ρ Μ O S transistor 5 0 1 ' is the activation signal SET for the setting and activation of the sense amplifier at the gate input. The PMOS transistors 502 and 503 are sense and latched transistors, and the transistors 5 〇 4 and 5 0 5 are used to transfer data to the transfer transistors of the data line DL and the data line inversion signal line DLB. An operation waveform of the mode shown in Fig. 16 is shown in Fig. 17. The data line DL and the data line inversion signal line DLB are pre-charged. It is assumed that the non-volatile semiconductor memory device 201 has been written to the 'non-volatile semiconductor memory device 202 as being erased. At time t41', "l" is input to the input terminal of the activation signal SET, and after the activation signal SET becomes "1", the high-sensitivity sense amplifier 500 is activated. Thereby, since the potential of the signal line Bit is kept substantially at "1", the signal line BltB is charged", so the potentials of the signal lines Bit and BitB are determined at a high speed. Thereafter, at time t42, "η" is input to the word line WL, and the potential of the word line WL becomes "η", and the potential of the data line DL and the data line inversion signal line DLB is determined, and the reading can be ended. 38 201001420 [Embodiment] FIG. 18 shows an embodiment 1 of a modification of the ninth embodiment. In the part which is changed in the first embodiment, the same reference numerals will be given to the unaltered portions, and the description will be omitted with reference to the ninth embodiment. Although the high-speed sense amplifier 5A shown in the ninth embodiment is the same, it has a replacement portion 2 0 0 d instead of the d memory portion 2 0 0 a. Further, in the form similar to the case and the part 2 〇 〇 d, there is the memory unit 2〇〇c shown in the eighth embodiment. The description of the memory unit 200d will be described in comparison with the memory unit 20〇c. The 6 memory unit 2 ○ 1 ′ is provided with non-volatile semiconductor memory elements 2 〇 1, 2 〇 2, and transistors 207 and 208. The drain of the non-volatile semiconductor memory device 20 1 is transmitted through the signal line BitB to the high-speed sense amplifier 500, and the source is connected to the transistor of the transistor 2〇7. The drain of the non-volatile semiconductor memory device 202 is connected to the high-speed sense amplifier 500 through the signal line Bit, and the source is connected to the drain of the transistor 2〇8.闸 The gate of the transistor 207 is connected to the input terminal of the signal SEL, and the source I is connected to the control signal terminal S. The gate of the transistor 208 is connected to the input terminal of the signal SEL, and the source is connected to the control signal terminal S. The memory unit 200d includes transistors 2〇7 and 2〇8 through which an appropriate current can flow, instead of the resistors 205 and 206 included in the memory unit 200c. The transistor 2〇7, 208 causes the current to operate, or the capacity of the transistor is small, reducing the drain current. At the gate terminal of the transistor 2〇7, 2〇8, the signal SEL having the selection signal is input. 39 201001420 It is composed of a transistor, which has the advantage that the configuration area can be compared with the resistor J, and the memory unit that can be activated by the signal SEL. For example, the matrix in Fig. 8 or Fig. 1 In this configuration, the control signal terminal S of the full memory unit can be a common terminal and selected by the signal SEL. As described above, according to the embodiments of the present invention, a nonvolatile semiconductor memory (i.e., a nonvolatile semiconductor memory device and a semiconductor device using the same) can be realized by a standard logic CMOS process. Therefore, in the non-volatile semiconductor memory of the present invention in the standard logic, the logic mixed memory can be realized easily and locally. Further, the present invention is not limited to the above-described embodiments, and modifications may be made without departing from the spirit and scope of the invention. It is also not particularly limited by the number of constituent elements or the connection form of the active elements of the semiconductor device of the present invention. According to the present invention, it is possible to realize a non-volatile semiconductor memory device of a one-layer polycrystalline stone early structure by a standard logic CMOS process and to realize a logical mixed memory easily and at low cost by using the same. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A shows an embodiment of a nonvolatile semiconductor memory device of the present invention. Fig. 1B shows an embodiment of the nonvolatile semiconductor memory device of the present invention. Fig. 1C shows the configuration of the non-volatile semiconductor memory device of the present invention. Fig. 2 is an isometric circuit diagram showing an embodiment of Figs. 1A to 1C. 40 201001420 FIG. 3 is a characteristic diagram for explaining an embodiment of FIGS. 1A to 1(1). Fig. 4A is an explanatory view showing an operation of the embodiment of Figs. 1A to 1c. Fig. 4B is an explanatory view showing an operation of the embodiment of the figure (1). Fig. 5A is a view showing a configuration of an embodiment (Embodiment 1) of the nonvolatile semiconductor memory device of Figs. 1A to 1c. Fig. 5B is a view showing a configuration of an embodiment (Embodiment 1) of the nonvolatile semiconductor memory device of 1A to 1c. ® 6 is an explanatory diagram of the embodiment of Fig. 5A' (7) of the embodiment i. Fig. 7 is a configuration diagram showing an application example of the nonvolatile semiconductor memory device of the second embodiment. Fig. 7 is a configuration diagram showing an application example of the nonvolatile semiconductor memory device of the second embodiment. Fig. 7C is a view showing the configuration of an application example of the nonvolatile semiconductor memory device of the second embodiment. f Fig. 8 shows a case where the matrix array is constructed using the embodiment of Figs. 7A to 7C of the third embodiment. Fig. 9 is a view showing the configuration of an application example of the nonvolatile semiconductor memory device of the fourth embodiment. Fig. 10 shows a case where the matrix array is used in the embodiment of Fig. 9 of the fifth embodiment. Fig. 11 is a view showing the configuration of an application example of the nonvolatile semiconductor memory device of the sixth embodiment. Fig. 12 is a view showing the operation of the embodiment of Fig. 11 of the sixth embodiment. 41 201001420. Fig. 1 is a configuration diagram showing an application example of the nonvolatile semiconductor memory device of the seventh embodiment. Fig. 14 is an explanatory view showing the operation of the embodiment of the seventh embodiment. Fig. 15 is a view showing the configuration of an application example of the nonvolatile semiconductor memory device of the eighth embodiment. Fig. 16 is a view showing the configuration of an application example of the nonvolatile semiconductor memory device of the ninth embodiment. Fig. 17 is an explanatory view showing the operation of the embodiment of Fig. 16 of the ninth embodiment. Fig. 8 is a view showing the configuration of an application example of the nonvolatile semiconductor memory device of the tenth embodiment. [Description of main component symbols] 100 200 1〇1, 102, 1〇3 104, 1〇5 106 '1〇7 SRAM section Memory section PMOS transistor NMOS transistor Transferring NM〇S transistor 42

Claims (1)

201001420 VII. Patent application scope: κ-type semiconductor device, having: memory part by the first non-volatile semiconductor memory element, and storing the opposite logic state of the ith non-volatile semiconductor memory element § The second non-volatile semiconductor memory device stores one piece of information; and the f-measurement portion transmits and stores the first and second non-volatile semiconductor memories in the first signal line and the second signal line. The information of the component; Γ is characterized in that: each of the first and second non-volatile semiconductor memory components are at least i 3 ^ / floating gate, drain, and source formed on the semiconductor substrate; a state in which a voltage is applied between the source and the drain to charge the charge into the floating gate and accumulate; and as an erased state, when the charge accumulated on the floating gate is erased, the semiconductor substrate is A voltage is applied between the drain or the source to enable a hot carrier between the band and the band to be generated in the semiconductor substrate, and the charge accumulated in the floating gate is erased by the hot carrier. 2. The semiconductor device according to claim 2, wherein the first non-volatile semiconductor memory device has a drain connected to the second signal line and a source connected to the first control signal terminal; a drain of the non-volatile semiconductor memory device is connected to the first signal line, and a source is connected to the second control signal terminal; and the source of each of the first and second non-volatile semiconductor memory devices is connected 1 control signal terminal and the second control signal terminal, which is the same as the reference potential when respectively using the different potentials when the '9 writers and the erasers are respectively used. [3] The semiconductor device of claim 1, wherein the non-volatile semiconductor memory device line is connected to the second signal, and the source is connected to the first control signal terminal; the second non- a volatile semiconductor (4) body element & pole connected to the first signal line, a source connected to the ith control signal terminal; " common connection of the first control signal terminal, at the time of erasing and writing The predetermined potential becomes the reference potential at the time of reading. 4. The semiconductor device according to claim 1, further comprising: first and second transistors; a drain of the first non-volatile semiconductor memory device connected to the source of the i-th transistor, The source is connected to the second control signal terminal; the drain of the second non-volatile semiconductor memory device is connected to the source and the source of the second transistor is connected to the second control signal terminal; the first transistor The gate is connected to the activation signal input terminal, the drain is connected to the D-Hai second signal line, and the source is connected to the drain of the first non-volatile semiconductor memory device; a gate of the second transistor is connected to the activation signal input terminal, a drain is connected to the first signal line, and a source is connected to the drain of the second non-volatile semiconductor memory device; 1 control signal terminal, which is a predetermined potential during erasing and writing, and becomes a reference potential during reading; by the activation signal input to the activation signal input terminal, 44 201001420 the first and second thunder曰 达 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , A voltage is applied between the semiconductor substrate and the drain or the source, so that a hot carrier between the semiconductor and the source is generated in the semiconductor substrate, and the charge accumulated in the floating gate is erased by the hot carrier. 5. The semiconductor device according to claim 1, further comprising: first and second resistors; D first, the first non-volatile semiconductor memory device has a drain connected to the second signal line and the source through the 帛1 a resistor is connected to the first control signal terminal; a second non-volatile semiconductor memory device has a gate connected to the first signal line, and a source through the second resistor is connected to the ith control signal terminal; The control signal terminal is a predetermined potential at the time of erasing and writing, and becomes a reference potential at the time of reading. 6. The semiconductor device of claim 1, further comprising: first and second transistors; a drain of the first non-volatile semiconductor memory device connected to the second signal line and a source connected to the first a drain of the second non-volatile semiconductor memory device; the drain of the second non-volatile semiconductor memory device is connected to the first signal line, and the source is connected to the drain of the second transistor; the gate of the first transistor is connected to The input terminal and the source of the activation signal are connected to the first control signal terminal; the gate of the second transistor is connected to the input terminal of the activation signal, and the source is connected to the first control signal terminal; The second transistor is activated by the input of the activation signal; 45 201001420 / The third control terminal of the control terminal is a predetermined potential at the time of erasing and writing, and becomes a reference potential when reading. 7. For example, in the semiconductor device of the third to the sixth of the patents (4), the sensing device includes a power supply line connected to the power supply through a transistor, and a signal is applied to the flip-flop circuit; In contrast, the circuit applies a voltage to the power supply by controlling the on state and the off state of the power supply transistor to maintain the output signals of the first and second nonvolatile semiconductor memory elements. 8. The semiconductor device according to any one of claims 6 to 6, wherein the sensing unit includes: a flip-flop circuit connected to the power source through a power supply transistor, and connected to the grounding power S-body The reference potential is connected to the memory via the pair of 帛i and the second signal lines; and the signal amplifying unit amplifies the output signal from the flip-flop circuit. A semiconductor device comprising: a memory unit in which a memory unit and a sensing unit are combined, wherein: at least a matrix array and a sense amplifier in which the memory cells are arranged in a row and a column direction; each of the memory cells The memory unit includes: first and second non-volatile semiconductor memory cells including at least a drain gate and a source formed on the semiconductor substrate; and a sensing portion through the power transmitting transistor Connected to the positive circuit of the power supply to maintain the signal; ° 46 201001420 Received the first and second non-volatile semiconductor memory components, which are used to erase the accumulated 1 in the floating gate. #士"寸寸' in the semiconductor A thermal carrier between the substrate and the drain or the source is applied to the semiconductor substrate, and the charge accumulated in the floating gate is erased by the hot carrier, the flip-flop The circuit includes: a, sensing, by the activation signal, controlling the conduction state and the off state of the power supply transistor, applying power to the flip-flop circuit '. source line for using the second and second Nonvolatile semiconducting The source of the memory component is connected to each row; the row line is used to transmit the selection signal of the sensing part and the activation signal to each row; and the bit 7L line is used to transmit the information of the sensing section to Each of the sense amplifiers has a reading means for connecting the signal outputted by the sensing portion to each of the bit lines to read the bit line and the row line designated by the non-volatile semiconductor memory Information stored in the state of charge accumulated by the floating parts of the component. A semiconductor device comprising: a memory unit in which the memory unit and the sensing unit are combined, wherein at least a matrix array in which the memory cells are arranged in a row and a column direction and a sense amplifier are included; The memory unit includes: a memory portion including: first and second non-volatile semiconductor memory devices including at least a floating gate, a drain, and a source formed on a semiconductor substrate; and the first and second 2 non-volatile semiconductor memory device device, and 47 201001420 to select or not select the second and second transistors of the second and second non-volatile semiconductor memory devices in an on state or an off state; The measuring unit holds the signal by a flip-flop circuit connected to the power supply through a power supply transistor; the non-volatile semiconductor memory element turns the first and second transistors into an on state, Applying a voltage between the source and the drain of the non-volatile semiconductor memory device to inject a charge into the floating gate and accumulating it for erasing accumulation in the first and second non-volatile semiconductor memory cells When a charge of the floating gate is applied, a voltage is applied between the semiconductor substrate and the drain or source of the first and second non-volatile semiconductor memory devices, and the thermal carrier between the band and the semiconductor is applied to the semiconductor. Produced in the substrate, the charge accumulated in the floating gate is erased by the hot carrier; the flip-flop circuit includes: a sensing portion, wherein the conductive transistor is controlled to be turned on and off by the activation signal a state in which a power source is applied to the flip-flop circuit; a source line for connecting the sources of the first and second non-volatile semiconductor memory devices to each row; "n-row lines for controlling the first The control signals of the gates of the first and second transistors, the activation signal, and the selection signal of the sensing portion are transmitted to each line; and the enemy line is used to transmit the information of the sensing unit to each column; The non-volatile semiconductor memory device and the sensing portion can be selectively blocked according to the signal input to the row line; the flip-flop circuit has a reading means for reading the bit line and 48 201001420 The line is specified as a non-volatile half Information stored in the state of charge accumulated by the floating gate of the body memory element. 11. A semiconductor device comprising: a memory unit having a first non-volatile semiconductor memory device, and having the same 1 non-volatile semiconductor memory S piece opposite logic state of the second non-volatile semiconductor memory element; hold. 卩, with · activated signal input terminal, by input / tongue ί · biochemical 5 hole number reading The sensing circuit of the information of the memory unit and the flip-flop circuit for maintaining the information read by the sensing circuit and outputting the signal; pre-charging 4, when the information of the memory unit is read, the signal holding unit Charging; and amplifying the detection 4, amplifying the signal outputted by the signal holding portion and applying the non-volatile semiconductor memory (4) to the 1 and 2, and the transistor is formed by the floating gate formed on the semiconductor substrate. a source structure, each source is connected to the first control signal terminal; and a voltage is applied between the source and the drain as a write-type sorrow to inject a charge into the floating gate and accumulate the charge of the floating gate Lead = beam: state, generated in the thermal carrier between the ... + conductor substrate and the drain or source between the application of the band - semiconductor substrate, by the hot carrier erase accumulated in the floating gate Charge. A 12' type semiconductor device comprising: a portion 帛1 non-volatile semiconductor memory device, and a second logic state having a reverse logic state of a non-volatile semiconductor memory device: 1 49 201001420 Non-volatile semiconductor memory And a signal holding unit connected to the memory unit through a pair of second and second signal lines, and maintaining and outputting information read from the memory unit by a flip-flop of the active circuit; 1 and a second non-volatile semiconductor memory device, which is composed of a floating gate, a drain, and a source formed on a semiconductor substrate, wherein each source is connected to the first control signal terminal; a state in which a voltage is applied between the source and the drain to inject a charge into the floating gate and accumulate; D and as an erased state, when the charge accumulated on the floating gate is erased, the semiconductor substrate and the drain are formed A voltage is applied between the source and the source to enable heat between the band and the band, which is generated in the semiconductor substrate, and is accumulated by the hot carrier erasing. The ignorance of the first illuminating semiconductor memory device is connected to the first signal line, the source is connected to the (4) 1 control signal terminal, and the second non-volatile semiconductor memory device is The pole is connected to the line 2^, and the source is connected to the 帛1 control signal terminal, and the first control signal terminal connected in common is a predetermined potential at the time of erasing and writing, and becomes a reference potential when being read. The signal holding unit includes an activation circuit, and includes a power supply transistor connected to the power supply side of the flip-flop circuit. The semiconductor device of the present invention is characterized in that it includes: a non-volatile semiconductor memory device, a second non-volatile semiconductor memory device having a logic state opposite to the first non-volatile semiconductor memory device, and a first transistor in series with the second non-volatile semiconductor memory device And a second transistor connected in series with the second non-volatile semiconductor 50 201001420 body memory element; and a signal holding unit constituting a flip-flop circuit having an activation circuit; 1 and the second non-volatile semiconductor memory device are electrically formed by a floating gate, a gate electrode and a source structure formed on the semiconductor substrate: each source is connected to the second control signal terminal; In the state, a voltage is applied between the source and the drain to charge the charge into the floating gate and accumulate; ° r and as an erased state, when erasing the charge accumulated in the floating gate, Applying a voltage between the semiconductor substrate and the drain or source, the hot carrier between the band and the band is generated in the semiconductor substrate, and the charge accumulated in the floating gate is erased by the hot carrier; In the memory unit, the drain of the first non-volatile semiconductor memory device is connected to the high-speed sense amplifier through the second signal line, and the source is connected to the drain of the Xiaxia transistor, and the second non-volatile semiconductor memory device The first 1st afL line is connected to the idle sense amplifier, and the source is connected to the drain of the 2^th transistor, and the gate of the second transistor is connected to the activation signal κ,.. — the input terminal and the source are connected to the first control signal terminal, the first 2, the open end of the transistor is connected to the input terminal of the activated signal, and the source is connected to the first control signal terminal 'the first control signal terminal, and the predetermined potential at the time of erasing and writing' becomes a reference potential; the signal holding unit includes an activation circuit including a power supply transistor connected to a power supply side of the flip-flop circuit; the signal holding unit is stored in the control signal given to the activation circuit The information of the non-volatile semiconductor memory device is amplified and detected by 51 201001420, and the read information is kept and output. VIII. Schema (such as the next page) 52