201008098 六、發明說明： 【發明所屬之技術領域】 * 本發明係有關—種充電栗式昇Μ電路，尤其關於一種 • 產生輸入電壓的非整數倍的輸出電壓之電路。 【先前技術】 第2圖係各知的充電栗式昇壓電路的電路圖。該充電 泵式㈣電路2係由下列要件所構成··充電㈣4，係將 ❹輸入電壓VIN昇壓至3倍；以及調節器部6，係將充電栗 部4的輸出電壓VlN予以降麗，並對輸出端子產生期 望的輸出電壓VQUT。 狀充電泵部4係具有三個串聯連接在輸入端子VjN與調 節器之間的切換（SWitching)元件SW1、s们。 於SW1 # SW2的連接點Νι連接有第一電容器^的一方 端子，於SW2與SW3的連接點n2連接有第二電容器C2 的-方端子。輸入端子Nin係連接於電路的驅動電源，該 ❹電源電壓係作為輸入電壓VIN。 於電谷盗C1的另一方端子與電源電壓（=輸入電壓 VIN)之間連接有切換元件SW4，而於電容器C1的另一方 端子與接地電壓GND(=0V)之間連接有切換元件SW5。 同樣地，在電容器C2的另一方端子與ViN之間連接有切換 元件SW6,而在電容器C2的另—方端子與g·之間連接 有切換元件SW7。 SW1、SW3係藉由控制時脈(clockpulse)CLKl進行切 換SW2係藉由與CLK1為反相的控制時脈clk2進行切 3 320512 201008098 換。SW4、SW5係根據控制時脈CLK1而互補性地進行切 換。SW6、SW7係根據控制時脈CLK2而互補性地進行切 • 換。例如構成為、SW3、SW5、SW6在CLK1為Η位 , 準時（此時CLK2變成L位準）選擇性地變成導通（〇Ν) 狀態，而SW2、SW4、SW7在CLK2為Η位準時（此時 CLK1變成L位準）選擇性地變成導通狀態。 在充電泵部4與調節器部6的連接點Nr連接有用以 將充電泵部4的輸出電壓予以平滑化的電容器Ccmt。 在靜態狀態下，當CLIC1為Η位準時，ci會被充電 至端子間電壓變成VlN的狀態，故Νι的電位會變成Vin。 當CLK2變成η位準時’由於C1的另—方端的電位：藉 由SW4的導通而從GND上昇至Vin，因此乂的電位會變 成2VIN。此時，由於SW2與SW7為導通狀態，因此^ 會被充電至端子間電壓變成2Vin的狀態。.此外，在clki 為Η位準時，C1與Cout會同時進行充電。具體而言，充 ❹電至0端子間電壓2VIN的C2的另一方端的電位會因為 SW6的導通而從GND上昇至乂爪，故\的電位會變成 3VIN。此時，由於SW3為導通狀態，因此c〇m會被充電， 於NR可獲得電壓3VIN。 雖然上述充電泵部4為兩段的充電泵，但一般能將充 電泵作成（η-l)段而於Nr獲得nVlN這種n倍的昇壓電 壓。 调郎器部6係包含有p通道MOS電晶體>^與放大器 A而構成Tr的源極係連接於nr，汲極係連接於n 。 320512 4 201008098 放大器A係構成非反轉放大電路，放大器A的輸出電壓係 施加至Tr的閘極，以控制Tr的通道電流。於非反轉輸入 端子（+ )施加基準電廢Vref，於反轉輪入端子（一）與 Νουτ之間連接有成為反饋電阻的R1，反轉輸入端子係經 由電阻R2而連接至GND。放大器Α與ρ通道的m〇S電 晶體Tr係以將ri與R2的連接點的電位設為Vref之 方式對Tr的汲極電流Id進行反饋控制。結果，於Ν〇υτ能 獲得下式所表示的輸出電壓乂01；1·。 ® V〇ut= ( 1 + R1/R2) VREF……（1) 調卽器部6係能在施加至Tr的汲極之電壓ηγΙΝ以下 的範圍内，根據電阻比R1/R2來產生VIN的非整數倍的 V〇ut。 專利文獻1 :日本特開2006-280160號公報 【發明内容】 (發明所欲解決之課題） ❿ 調節器部6係被施加充電栗部4所產生的高電壓。亦 ^調節器部6係存在有需要構成為高耐壓之問題。例如， 虽為了提昇耐壓而加大勘8電晶體Tr的尺寸時，在將充 電I式幵壓電路2作為積體電路而構成時，會有晶片尺寸 的門題此外，爲了抑制因c〇ut的放電所導致的ν〇υτ =’調節器部6 一般係以降低Id之方式來構成。在此 ^ ，ΤΓ會變成在幾乎接近關斷（OFF)的狀態下進行 $ 4的閘極電壓可能會變成對應從爲施加至源極的 電堡之高電壓。因此 i & b用以產生該閘極電壓的放大器A亦 320512 5 201008098 I · 被要求構成為兩耐麼，而存在有尺寸變大之 本發明乃爲解決上述問題點而研創者，Iβ .供一種不使用高耐>1的調節器部，即可彦目的在於提 -之非整數倍的輪出電壓ν〇υτ之充電栗式昇電壓VIN (解決課題的手段） 1電路。 本發明的充電系式昇壓電路係將施 輸入電壓予以昇壓，並從輸出端子輸出昇壓輪t端子的 該昇跑之特徵為具有:複數個切換元:輪2壓者; 於前述輸入端子與前述輸出端子之間糸串聯連接 元件係交互地成為 導通狀態;電容接的切換 彼此鄰接的一對前述切換元件的相互連接點·^係連接於 電路，係供給時脈脈波至前述電容器的另1方!容器驅動 於該電容器的一方端，與位於前述輸入端子側二並迷接 ⑩ 位，且亦連接於前述電容步器的方， 子侧的前述切換元件的前述導通狀雜门4位於前述輪出端 端作為第二電位，·以及，反:^同步，將前述另一方 壓 電位 輸出電麼’並以使該昇屢輸出電屋成為對前述昇愿 上 雄 乂調整刖述時脈脈波的前述第一命 或剛述第二電位之反饋控制。 (發明之效果） 準電壓的值 該監視電壓 馬了將昇壓輸出電壓控制成對應預定基 饋控制電路係監視昇壓輸出電壓的變動。 係只要能麵行反倾㈣把祕壓輸出電壓 發月爲了將昇壓輸出電壓控制成對應預定基 壓的值，反饋控告，丨發m 邊私。 6 320512 201008098 的增減即足夠，無須為昇壓輸出電壓，例如能設成經過分 壓之電壓等較低的電壓。亦即，在本發明中，不需要被施 .加昇壓輸出電壓之高耐壓的調節器。此外，用以產生輸入 電壓的非整數倍的電壓之反饋控制電路不會直接被施加昇 壓輸出電壓，因此不須構成為高耐壓。因此，依據本發明， 能減少應構成為高耐壓的部分，而可將電路小型化。 【實施方式] 以下根據圖式說明本發明的實施形態（以下稱為實施 罾形態）。 第1圖係本發明實施形態的充電泵式昇壓電路20的 概略電路圖。充電泵式昇壓電路20係能例如於單一個半導 體晶片上作為積體電路而構成者，且包含有充電泵部22 與反饋控制電路24而構成。在此，充電泵部22係構成為 進行兩段昇壓。充電泵部22係包含有分別作為切換元件而 發揮功能的MOS電晶體SW1至SW7、昇壓電容器ci、 © C2、以及輸出電容器c〇ut而構成。另一方面，反饋控制 電路24係包含有電阻元件ri、R2、放大器A、以及基準 電壓源VREF而構成。 SW1至SW3係例如為以n通道MOS電晶體所構成， 且串聯連接於輸入端子Νιν與輸出端子Ν〇υτ之間。SW1 至SW3各者的閘極係從未圖示的切換控制電路被施加時 脈信號CLK1或CLK2。CLK1與CLK2係具有以固定週期 切換電壓VH的Η位準與電壓VL (電壓Vl<Vh)的L位 準，且彼此相位為反轉之關係。SW1、SW3係被施加 7 320512 201008098 CLK1 ’ SW2係被施加CLK2。藉此，SW1至sW3彼此相 鄰接的一對會互補性地動作，當一方被施位準而成為 • 導通(on)狀態時，另一方會被施加L位準而成為關斷(〇ff) 狀態。 • C1的一方端係連接於SW1與SW2的連接點，另 一方端係連接於由SW4與SW5所構成的電容器驅動電路 30。此外，C2的一方端係連接於SW2與SW3的連接點 Ns，另一方端係連接於由SW6與SW7所構成的電容驅動 ❹電路32。 • 構成電容驅動電路3〇、32之SW4、SW6係例如由p , 通道MOS電晶體所構成，另一方面，SW5、SW6係例如 由η通道MOS電晶體所構成。SW4、SW6的源極係分別 連接至放大器.Α的輸出端’ SW5、SW7的源極係分別連接 至GND。於C1的另一方端連接有SW4、SW5各者的没極。 SW4、SW5各者的閘極係共通地被施加CLK1。在此，p ❹通道MOS電晶體的閘極被施加L位準時會成為導通狀 態，而η通道MOS電晶體則相反，閘極被施加η位準時 會成為導通狀態。因此’ SW4、SW5會根據CLK1而互補 性地切換。另一方面，於C2的另一方端連接有SW6、SW7 各者的汲極。SW6、SW7各者的閘極係共通地被施加 CLK2，且根據CLK2而互補性地切換。201008098 VI. Description of the Invention: [Technical Field to Which the Invention Is Applicable] * The present invention relates to a charge-pump type circuit, and more particularly to a circuit for generating an output voltage of a non-integer multiple of an input voltage. [Prior Art] Fig. 2 is a circuit diagram of a known charge pump booster circuit. The charge pump type (4) circuit 2 is composed of the following requirements: · charging (4) 4, the ❹ input voltage VIN is boosted to 3 times; and the regulator unit 6 is to reduce the output voltage VlN of the charging pump portion 4, A desired output voltage VQUT is generated for the output terminal. The charge pump unit 4 has three SWitching elements SW1 and S connected in series between the input terminal VjN and the regulator. A terminal of the first capacitor ^ is connected to the connection point SW1 of SW1 #SW2, and a - terminal of the second capacitor C2 is connected to the connection point n2 of SW2 and SW3. The input terminal Nin is connected to a driving power source of the circuit, and the ❹ power supply voltage is used as an input voltage VIN. The switching element SW4 is connected between the other terminal of the electric thief C1 and the power supply voltage (= input voltage VIN), and the switching element SW5 is connected between the other terminal of the capacitor C1 and the ground voltage GND (=0 V). Similarly, a switching element SW6 is connected between the other terminal of the capacitor C2 and ViN, and a switching element SW7 is connected between the other terminal of the capacitor C2 and g. SW1 and SW3 are switched by controlling the clock pulse CLK1. The SW2 is switched by the control clock clk2 which is inverted from CLK1 3 320512 201008098. SW4 and SW5 are complementarily switched in accordance with the control clock CLK1. SW6 and SW7 are complementarily switched in accordance with the control clock CLK2. For example, SW3, SW5, and SW6 are clamped at CLK1, and punctual (when CLK2 becomes L-level) selectively becomes conductive (〇Ν) state, and SW2, SW4, and SW7 are clamped to CLK2 (this When CLK1 becomes the L level, it selectively becomes an on state. A capacitor Ccmt for smoothing the output voltage of the charge pump unit 4 is connected to the connection point Nr of the charge pump unit 4 and the regulator unit 6. In the static state, when CLIC1 is clamped, ci will be charged until the voltage between terminals becomes VlN, so the potential of Νι will become Vin. When CLK2 becomes n-level, the potential of the other terminal of C1 is raised from GND to Vin by the conduction of SW4, so the potential of 乂 becomes 2 VIN. At this time, since SW2 and SW7 are in an on state, ^ will be charged until the voltage between the terminals becomes 2Vin. In addition, when clki is clamped, C1 and Cout will be charged simultaneously. Specifically, the potential of the other end of C2 that is charged to the 0-terminal voltage 2VIN is raised from GND to the claw due to the conduction of SW6, so the potential of \ becomes 3 VIN. At this time, since SW3 is in an on state, c〇m is charged, and a voltage of 3 VIN is obtained at NR. Although the above-described charge pump unit 4 is a two-stage charge pump, it is generally possible to form the charge pump as (η-1) and Nr to obtain n times the boost voltage of nVlN. The illuminator unit 6 includes a p-channel MOS transistor > and the amplifier A, the source of the Tr is connected to nr, and the drain is connected to n. 320512 4 201008098 Amplifier A forms a non-inverting amplifier circuit, and the output voltage of amplifier A is applied to the gate of Tr to control the channel current of Tr. The reference electric waste Vref is applied to the non-inverting input terminal (+), and R1, which is a feedback resistor, is connected between the inverting wheel input terminals (1) and Νουτ, and the inverting input terminal is connected to GND via the resistor R2. The amplifier Α and the mρS transistor Tr of the ρ channel are feedback-controlled to the drain current Id of Tr so that the potential of the connection point of ri and R2 is Vref. As a result, the output voltage 乂01;1· represented by the following equation can be obtained at Ν〇υτ. ® V〇ut= ( 1 + R1/R2) VREF (1) The regulator unit 6 can generate VIN according to the resistance ratio R1/R2 within the range of the voltage ηγΙΝ applied to the drain of Tr. Non-integer multiple of V〇ut. [Problem to be Solved by the Invention] 调节 The regulator unit 6 applies a high voltage generated by the charging pump portion 4. Also, the regulator unit 6 has a problem that it is necessary to constitute a high withstand voltage. For example, when the size of the oscillating transistor Tr is increased in order to increase the withstand voltage, when the charging type I squeezing circuit 2 is configured as an integrated circuit, there is a problem of the size of the wafer. The ν 〇υ τ = ' adjuster portion 6 caused by the discharge of 〇 ut is generally configured to reduce Id. At this point, ΤΓ will become a voltage close to OFF (OFF). The gate voltage of $4 may become a high voltage corresponding to the electric bunker applied to the source. Therefore, the amplifier A for generating the gate voltage of i & b is also 320512 5 201008098 I · It is required to constitute two resistances, and the present invention has the advantage of increasing the size of the present invention to solve the above problems, Iβ. For a regulator that does not use high resistance > 1, the purpose is to increase the voltage of the pumping voltage VIN of the non-integer multiple of the wheel-out voltage ν 〇υ τ (the means to solve the problem) 1 circuit. The charging system boosting circuit of the present invention boosts the input voltage and outputs the boosting wheel t terminal from the output terminal. The running is characterized by: a plurality of switching elements: the wheel 2 is pressed; The series connection elements between the input terminal and the output terminal are alternately turned on; the mutual connection points of the pair of switching elements adjacent to each other for switching the capacitance connection are connected to the circuit, and the pulse wave is supplied to the foregoing The other side of the capacitor: the container is driven at one end of the capacitor, and is connected to the input terminal side and is connected to the capacitor block, and is also connected to the capacitor side of the capacitor side. The door 4 is located at the aforementioned wheel end as a second potential, and, in the opposite direction, is synchronized, and the other piezoelectric bit is outputted, and the output is adjusted to the above-mentioned wish. The aforementioned first life of the pulse wave or the feedback control of the second potential is described. (Effect of the Invention) The value of the quasi-voltage The monitoring voltage is controlled so that the boost output voltage is controlled so as to monitor the fluctuation of the boost output voltage in accordance with a predetermined reference feed control circuit. As long as it can face the anti-dip (four) to the secret pressure output voltage in order to control the boost output voltage to a value corresponding to the predetermined base pressure, the feedback complaint, the m edge private. The increase or decrease of 6 320512 201008098 is sufficient. It does not need to be the boost output voltage, for example, it can be set to a lower voltage such as a divided voltage. That is, in the present invention, it is not necessary to apply a regulator having a high withstand voltage of a boosted output voltage. Further, the feedback control circuit for generating a voltage which is not a multiple of the input voltage is not directly applied with the boost output voltage, and therefore does not have to be formed to have a high withstand voltage. Therefore, according to the present invention, it is possible to reduce the portion which should be configured to have a high withstand voltage, and to downsize the circuit. [Embodiment] Hereinafter, an embodiment (hereinafter referred to as an embodiment) of the present invention will be described with reference to the drawings. Fig. 1 is a schematic circuit diagram of a charge pump type booster circuit 20 according to an embodiment of the present invention. The charge pump booster circuit 20 can be configured as an integrated circuit on a single semiconductor wafer, for example, and includes a charge pump unit 22 and a feedback control circuit 24. Here, the charge pump unit 22 is configured to perform two-stage boosting. The charge pump unit 22 includes MOS transistors SW1 to SW7 that function as switching elements, boosting capacitors ci, ©C2, and an output capacitor c〇ut. On the other hand, the feedback control circuit 24 includes resistor elements ri, R2, an amplifier A, and a reference voltage source VREF. SW1 to SW3 are, for example, an n-channel MOS transistor, and are connected in series between the input terminal Νιν and the output terminal Ν〇υτ. The gate of each of SW1 to SW3 is supplied with a clock signal CLK1 or CLK2 from a switching control circuit (not shown). CLK1 and CLK2 have an L-level in which the voltage VH is switched at a fixed period and an L-level of the voltage VL (voltage Vl < Vh), and the phases are inverted. SW1, SW3 are applied 7 320512 201008098 CLK1 ' SW2 is applied with CLK2. Thereby, the pair of adjacent ones of SW1 to sW3 will complementarily operate, and when one is applied to be in the on state, the other side is applied with the L level to be turned off (〇ff ) Status. • One end of C1 is connected to the connection point of SW1 and SW2, and the other end is connected to capacitor drive circuit 30 composed of SW4 and SW5. Further, one end of C2 is connected to the connection point Ns of SW2 and SW3, and the other end is connected to a capacitance drive ❹ circuit 32 composed of SW6 and SW7. • SW4 and SW6 constituting the capacitor drive circuits 3A and 32 are formed, for example, by p and channel MOS transistors. On the other hand, SW5 and SW6 are formed of, for example, n-channel MOS transistors. The source of SW4 and SW6 is connected to the output of the amplifier. The output terminals of SW5 and SW7 are connected to GND. The other end of C1 is connected to the non-polarity of each of SW4 and SW5. The gates of each of SW4 and SW5 are commonly applied with CLK1. Here, the gate of the p ❹ channel MOS transistor is turned on when the L level is applied, and the n channel MOS transistor is reversed, and the gate is turned on when the η level is applied. Therefore, 'SW4, SW5' will switch complementarily according to CLK1. On the other hand, the drain of each of SW6 and SW7 is connected to the other end of C2. The gates of each of SW6 and SW7 are commonly applied with CLK2, and are switched complementarily according to CLK2.
Cout的.一方端係連接至輸出端子Ν〇υτ ’另一方端传· 連接至GND。Cout係根據SW3的切換而被充放電，其充 電電壓係作為充電泵式昇壓電路20的輸出電壓ν〇υτ而從 320512 8 201008098 N〇UT輸出。為了將因切換所導致的V〇UT的變動予以平滑 化，Cout係可設定成較大的電容。One end of Cout is connected to the output terminal Ν〇υτ ′ and the other end is connected to GND. Cout is charged and discharged according to the switching of SW3, and the charging voltage is output from 320512 8 201008098 N UT as the output voltage ν 〇υ τ of the charge pump type boosting circuit 20. In order to smooth the variation of V〇UT due to switching, Cout can be set to a larger capacitance.
Rl、R2係串聯連接於n〇ut與GND之間。Ri、反2係 作為將V0UT予以分壓之分壓電路而發揮功能，而於、 R2的連接點Nb產生下式所示的分壓電壓VB。Rl and R2 are connected in series between n〇ut and GND. The Ri and the inverse 2 functions as a voltage dividing circuit that divides the VOUT, and the divided voltage VB shown by the following equation is generated at the connection point Nb of R2.
Vb = V〇utXR2/ (R1+R2) ...... (2) 放大器A的反轉輸入端子（一）係連接至，非反 轉輸入端子（+ )係連接至基準電壓源VREF。放大器a的 ❹ 輸出電壓Va係施加至SW4、SW6的源極。放大器a係監 視對應V0UT的電壓VB，並控制充電泵部22的動作狀態以 調整V〇UT。 在此，放大器A係構成一種非反轉放大電路，係以將 反轉輸入端子所連接的nb的電壓vB保持於基準電壓Vref 之方式來控制充電泵部22。反饋控制電路24係藉由該放 大器A的動作而進行用以將VOUT設為對應基準電壓Vref ❹之值的反饋控制。因此，根據關係式（2) ’藉由將VB保 持於Vref的控制所獲得之V〇ut係成為： V〇ut = Vref (1 + R1/R2) ...... ( 3 ) 接者’說明本充電栗式昇壓電路20的動作。如上戶斤 述’當CLK1為Η位準（CLK1 = H)時，CLK2為L位準 (CLK2 = L) ’ 另一方面，當 CLK1 為 L 位準（CLKl = l) 時，CLK2變成Η位準（CLK2 = H)。 當CLK1 = H時，C1的一方端係經由SW1而連接至 Nin，並被施加VIN，另一方端係藉由電容器驅動電路 320512 9 201008098 而被施加GND，藉此Cl會被充電。達到靜態狀態時的C1 的充電電壓會變成VIN。 • 當CLK2 = H時，SW2會變成導通狀態，c2的一方端 係連接至川而被施加化的電位’另一方端係藉由電容器 驅動電路32而被施加GND。此時’在c 1與C2之巧會產 生電荷移動’俾使N!的電位與Ns的電位平衡，而C1所 放電的部分會對C2充電。在此，由於C1的另一方端係藉 ❹由電容器驅動電路30而被施加放大器a的輪出電堡> 〇)，因此在CLK2 = H的時間點，&的電位會變成（ VlN + VA)。N!的電位會施加至C2的一方端。達到靜態狀態 的C2的充電電壓會變成（Vin + va)。 此外’當CLK1 = H時，不僅是SW1，SW3亦會變成 導通狀態，而同時進行上述C1的充電與Cout的充電。藉 由SW3變成導通，Cout的一方端係連接至N2而被施加 N2的電位。此時，在C2與Cout之間會產生電荷移動，俾 ❹使A的電位與Ν〇υτ的電位平衡，而C2所放電的部分會 對Cout充電。在此，由於C2的另一方端係藉由電容器驅 動電路32而被施加放大器a的輸出電壓Va(>〇)，因 此在CLK1 = Η的時間點，]s[2的電位會變成（Vin + 2VA )。 A的電位係施加至Cout的一方端。達到靜態狀態時的Cout 的充電電壓會變成（VIN+2VA)，該充電電壓會作為V〇ut 輸出。亦即， V〇ut= VIN + 2Va------- (4) 在此，從關係式（3)、（4)可獲得 10 320512 1 201008098 νΑ= { Vref (1 + R1/R2) -Vin) /2…·.· (5) 放大器A係將關係式（5)所表示的VA作為動作點， 進行非反轉放大動作。例如，當因VOUT從關係式（3)所 獲得的值上昇而使輸入至反轉輸入端子的輸入電壓VB上 昇時，非反轉輸入端子（+ )的電位V+與反轉輸入端子 的電位V-的差（V+ — V-)會變成負值，與此對應，VA會從 關係式（5)的動作點降低。結果，關係式（4)所表示的 Vout亦會降低。反之，當V0UT比關係式（3 )所獲得的值 ® 低時，放大器A會動作，俾使V0UT上昇。如此，反饋控 制電路24係以使V0UT成為對應關係式（3 )所表示的基準 電壓VREF之值的方式來進行反饋控制。 如關係式（3)所示，本充電泵式昇壓電路20係可對 應VREF與IU、R2的比（R1/R2)而獲得VIN之非整數倍 的Vout。尤其，只要將（Rl / R2 )設大·，不用將Vref設 成南電壓即能產生南電壓的V〇ut。亦即’放大器A的輸 ❹入端子電壓V+、V-不用設定成高電壓。 再者，在進行習知昇壓的充電泵式昇壓電路2中，只 要構成為進行（η—1)段的昇壓，即能獲得nVIN以下的 Vout。充電泵式昇壓電路20的昇壓段數並未限定於上述 之二段，能設成任意的段數。為了以相同的條件進行比較， 設想將充電泵式昇壓電路20作成昇壓段數（η-1)，能獲 得nVin以下的V〇ut之情形。在該情形中的Va係相當於關 係式（4)的下式： 由 V〇ut= Vllv[+ ( η—1 ) Va...... (6) Π 320512 201008098 求得 vA= (volJT—Vin} / (n—〇 ••…⑺Vb = V〇utXR2/ (R1+R2) (2) The inverting input terminal (1) of amplifier A is connected to, and the non-inverting input terminal (+) is connected to the reference voltage source VREF. The ❹ output voltage Va of amplifier a is applied to the sources of SW4 and SW6. The amplifier a monitors the voltage VB corresponding to the VOUT and controls the operation state of the charge pump unit 22 to adjust V〇UT. Here, the amplifier A constitutes a non-inverting amplifying circuit that controls the charge pump unit 22 such that the voltage vB of nb to which the inverting input terminal is connected is held at the reference voltage Vref. The feedback control circuit 24 performs feedback control for setting VOUT to a value corresponding to the reference voltage Vref 藉 by the operation of the amplifier A. Therefore, according to the relation (2) 'V〇ut obtained by the control of keeping VB at Vref is: V〇ut = Vref (1 + R1/R2) (3) 'Description of the operation of the charge pump type booster circuit 20. As mentioned above, when CLK1 is the Η level (CLK1 = H), CLK2 is the L level (CLK2 = L). On the other hand, when CLK1 is the L level (CLKl = l), CLK2 becomes the clamp. Quasi (CLK2 = H). When CLK1 = H, one end of C1 is connected to Nin via SW1, and VIN is applied, and the other end is applied with GND by capacitor driving circuit 320512 9 201008098, whereby Cl is charged. The charging voltage of C1 when it reaches the quiescent state will become VIN. • When CLK2 = H, SW2 becomes conductive, one end of c2 is connected to the applied potential, and the other end is applied with GND by capacitor drive circuit 32. At this time, 'c1 and C2 happen to generate a charge shift', so that the potential of N! is balanced with the potential of Ns, and the portion where C1 is discharged charges C2. Here, since the other end of C1 is applied by the capacitor driving circuit 30, the potential of the amplifier a is applied, and therefore, at the time point of CLK2 = H, the potential of & becomes (VlN + VA). The potential of N! is applied to one end of C2. The charging voltage of C2 that reaches the static state will become (Vin + va). In addition, when CLK1 = H, not only SW1 but also SW3 will be turned on, while charging of C1 and charging of Cout are performed at the same time. When SW3 becomes conductive, one end of Cout is connected to N2 and a potential of N2 is applied. At this time, a charge shift occurs between C2 and Cout, and the potential of A is balanced with the potential of Ν〇υτ, and the portion discharged by C2 charges Cout. Here, since the other end of C2 is applied with the output voltage Va of the amplifier a by the capacitor drive circuit 32 (> 〇), at the time point of CLK1 = ,, the potential of the s[2 becomes (Vin + 2VA ). The potential of A is applied to one end of Cout. When the quiescent state is reached, the charging voltage of Cout becomes (VIN+2VA), and the charging voltage is output as V〇ut. That is, V〇ut= VIN + 2Va------- (4) Here, 10 320512 1 201008098 νΑ= { Vref (1 + R1/R2) can be obtained from the relations (3) and (4). -Vin) /2... (5) The amplifier A performs the non-inverting amplification operation by using the VA indicated by the relational expression (5) as an operating point. For example, when the input voltage VB input to the inverting input terminal rises due to the increase in the value obtained by the relationship (3) from VOUT, the potential V+ of the non-inverting input terminal (+) and the potential V of the inverting input terminal The difference (V+ - V-) will become a negative value, and correspondingly, VA will decrease from the operating point of relation (5). As a result, the Vout represented by the relation (4) is also lowered. Conversely, when VOUT is lower than the value ® obtained by relation (3), amplifier A will operate and cause VOUT to rise. In this manner, the feedback control circuit 24 performs feedback control such that the VOUT becomes the value of the reference voltage VREF indicated by the relational expression (3). As shown in the relation (3), the charge pump type booster circuit 20 can obtain Vout which is a non-integer multiple of VIN in accordance with the ratio (R1/R2) of VREF to IU and R2. In particular, if (Rl / R2) is set to be large, V〇ut of the south voltage can be generated without setting Vref to the south voltage. That is, the input terminal voltages V+ and V- of the amplifier A are not set to a high voltage. Further, in the charge pump type booster circuit 2 for performing conventional boosting, Vout of nVIN or less can be obtained only by performing boosting in the (η-1) stage. The number of boosting stages of the charge pump type booster circuit 20 is not limited to the above two stages, and can be set to an arbitrary number of stages. In order to compare the same conditions, it is assumed that the charge pump type booster circuit 20 is configured as the number of boosting stages (?-1), and V?ut of nVin or less can be obtained. The Va in this case corresponds to the following equation of the relation (4): vA = (volJT) is obtained from V〇ut = Vllv[+ ( η - 1 ) Va... (6) Π 320512 201008098 —Vin} / (n—〇••...(7)
Va的上限Va (max)為V〇UT = nVIN時的值，該值係 由關係式（7)在下式所求得。 VA (max) =VIN...... (8) 亦即，放大Is A的輸出電壓Va基本上亦無須設成高 電壓°亦即’放大器A的輸人端子與輸出端子皆無須設成 高電壓’故無須構成為高耐壓^The upper limit Va (max) of Va is a value at V 〇 UT = nVIN, which is obtained by the following equation from the relation (7). VA (max) = VIN... (8) That is, the output voltage Va of the amplified Is A does not need to be set to a high voltage, that is, the input terminal and the output terminal of the amplifier A need not be set to be High voltage' does not need to be formed as high withstand voltage^
在充電系式昇壓電路2〇令，由於^亦能設定成超過 VIN的電壓，因此在放大器A的耐壓範圍内，將每一段的 昇壓電壓設定成超過VIN的值，而能以少數的昇壓段數獲 得比習知退南的:V〇ut。 如上述說明可知，每一段的昇壓電壓係以電容器驅動 電路30、32施加至昇壓電容ci、C2的另一方端之電容器 驅動時脈的振幅來設定。因此，與將·電容驅動時脈下降時 的電壓Vcl固定於GND、並以放大器a的輸出電壓乂八控 ❹制上昇時的電壓vch之上述構成相反，亦可為固定VCH| 以含有放大器A的電路將vCL進行反饋控制之構成。在此 情形中，例如當Vout上昇時，與上述構成相反，以使γΑ 上昇並縮小電容驅動時脈的振幅之方式來構成反饋控制電 路。例如，在該情形中使用放大器A來構成反轉放大電路， 而非構成上述的非反轉放大電路。 上述實施形態雖為使電壓朝正方向昇壓的正電壓昇 壓電路，但亦可作成使電壓的絕對值朝負方向增加的負電 壓昇壓電路。例如，負電壓昇壓電路係可藉由作成在第1 12 320512 201008098 圖所示的電路中施加CLK2至電容器驅動電路3〇的SW4 與SW5的閘極、並把加CLK1至電容器驅動電路32的sw6 與SW7的閘極之構成來實現《在此構成中，c〇ut的充電 電壓V〇ut係代入關係式（4 )所表示的電壓，而變成（vin —2VA)。該VOUT係在VIN為負電壓時與該Vin相比絕對 值明顯地朝負方向增加之電壓’理解到能獲得經過昇塵的 負電壓。此外，只要作成昇壓段數（η—υ，ν〇υτ會代入 關係式（6 )而成為VIN —（ η — 1 ) νΑ。 ❹ 依據本發明，無須高耐壓的調節器，且構成反饋控制 電路24的放大器A亦未要求高耐壓，因此能減少在電路 内要求高财壓的部分。因此，由於抑制為了確保耐壓而導 致的電晶體尺寸的大型化’因此晶片尺寸容易小型化。 此外，供、給CLK1、CLK2的切換控制電路係可形成 於形成有充電泵式昇壓電路20的半導體晶片外，亦可形成 於同一個晶片上。 7 ❹ 【圖式簡單說明】 第1圖係本發明實施形態的充電泵式昇壓電路的概略 電路圖。 第2圖係S知的充電泵式昇壓電路的電路圖。 【主要元件符號說明】 2、20 充電泵式昇壓電路 4、22 充電泵部 6 調節器部 24 反饋控制電路 320512 13 201008098In the charging system booster circuit 2, since the voltage can be set to exceed VIN, the boost voltage of each segment is set to exceed the value of VIN within the withstand voltage range of the amplifier A, and A small number of boost segments are obtained from the conventional retreat: V〇ut. As is apparent from the above description, the boosted voltage of each stage is set by the amplitude of the capacitor driving clock applied to the other ends of the boosting capacitors ci and C2 by the capacitor driving circuits 30 and 32. Therefore, the voltage Vcl when the capacitor driving clock is lowered is fixed to GND, and the voltage vch when the output voltage of the amplifier a is increased by ❹8 is reversed, and the VCH| can be fixed to include the amplifier A. The circuit consists of a feedback control of the vCL. In this case, for example, when Vout rises, contrary to the above configuration, the feedback control circuit is constructed such that γ 上升 rises and the amplitude of the capacitance drive clock is reduced. For example, in this case, the amplifier A is used to constitute the inverting amplifying circuit instead of the above-described non-inverting amplifying circuit. The above embodiment is a positive voltage boosting circuit that boosts the voltage in the positive direction, but may be a negative voltage boosting circuit that increases the absolute value of the voltage in the negative direction. For example, the negative voltage boosting circuit can be applied to the gates of SW4 and SW5 of the capacitor driving circuit 3A by applying CLK2 to the circuit shown in the first 12 320512 201008098, and adding CLK1 to the capacitor driving circuit 32. The composition of the gates of sw6 and SW7 is realized. In this configuration, the charging voltage V〇ut of c〇ut is substituted into the voltage represented by the relation (4), and becomes (vin — 2VA). This VOUT is a voltage at which the absolute value of the VIN is negatively increased in the negative direction when the VIN is a negative voltage. It is understood that a negative voltage that can be lifted can be obtained. In addition, as long as the number of boosting sections (η-υ, ν〇υτ is substituted into relation (6), it becomes VIN —( η — 1 ) νΑ. ❹ According to the present invention, a regulator having no high withstand voltage is required, and constitutes feedback Since the amplifier A of the control circuit 24 is not required to have a high withstand voltage, it is possible to reduce a portion where high fuel pressure is required in the circuit. Therefore, since the size of the transistor is large in order to ensure the withstand voltage, the wafer size is easily miniaturized. Further, the switching control circuit for supplying and supplying CLK1 and CLK2 may be formed outside the semiconductor wafer on which the charge pump type boosting circuit 20 is formed, or may be formed on the same wafer. 7 ❹ [Simple description of the drawing] 1 is a schematic circuit diagram of a charge pump type booster circuit according to an embodiment of the present invention. Fig. 2 is a circuit diagram of a charge pump type booster circuit known as S. [Description of main component symbols] 2. 20 charge pump type booster Circuit 4, 22 Charge pump section 6 Regulator section 24 Feedback control circuit 320512 13 201008098
30、32 電容器驅動電路 A 放大Is CLK1 ' CLK2 控制時脈 Cout 輸出電容器 Cl、C2 昇壓電容器 GND 接地電壓 Nin 輸入端子 N〇ut 輪出端子 N!、N2、Nb 連接點 R1、R2 電阻 SW1 至 SW7 MOS電晶體（切換元件) Tr MOS電晶體 vA 輸出電壓 VB 分壓電壓 VIN 輸入電壓 V〇ut 輸出電壓 Vin 輸入電壓 V〇ut 輸出電壓 Vref 基準電壓（源） V+、V- 電位 14 32051230, 32 Capacitor drive circuit A Amplify Is CLK1 ' CLK2 Control clock Cout Output capacitor Cl, C2 Boost capacitor GND Ground voltage Nin Input terminal N〇ut Wheel terminal N!, N2, Nb Connection point R1, R2 Resistance SW1 To SW7 MOS transistor (switching element) Tr MOS transistor vA Output voltage VB Divided voltage VIN Input voltage V〇ut Output voltage Vin Input voltage V〇ut Output voltage Vref Reference voltage (source) V+, V- Potential 14 320512