201004509 九、發明說明： 【發明所屬之技術領域】 本發明涉及電路板製造技術，尤其涉及一種覆銅基板 : 裁切方法。 【先前技術】 隨著電子產業之飛速發展，作為電子產品基本構件之 電路板製作技術顯得越來越重要，線路與孔之製作要求亦 越來越精細。電路板具有單面板、雙面板以及多層板之分， 均由覆銅基板經裁切、鑽孔、蝕刻、曝光、顯影等一系列 製程製作而成。具體可參閱C.H. Steer等人於Proceedings of the IEEE，Vol.39，No.2 (2002 年 8 月）中發表之 “Dielectric characterization of printed circuit board substrates” 一文。 電路板加工製作過程中，通常需要將大尺寸之覆銅基 板裁切成若干小尺寸之電路板單元。覆銅基板之主要組成 材料包括玻纖布以及銅箔。其中，玻纖布作為銅箔之載體， 係由玻璃纖維以平織法製造而成。 然而，由於玻纖布自身之纖維結構於經緯方向之排佈 密度與方式不同，造成覆銅基板於經緯方向具有不同結 構，進而使得覆銅基板於經緯方向之漲縮率不同。因而， 為保證裁板品質，先前覆銅基板於裁切時採用單一之排版 方式，該單一之排版方式使得覆銅基板具有較大之餘料無 法利用，具有較低之覆銅基板利用率，從而增加電路板製 作成本。 7 201004509 有鑑於此，提俾一^ 基板裁切方法實屬^心提高覆銅基板利用效率之覆銅 【發明内容】 以下將以具體竇始y, 率之覆銅基板裁切方法明—種可提高覆銅基板利用效 A板裁切方法，其包括以下步驟：提供覆銅 排版後之覆銅基板包括排版，並使得 :電長度方向平行於覆銅基板緯向之複數 記號，於第二電路^ _板単70製作第—經緯向識別 覆銅Α纟早兀製作第二經緯向識別記號；裁切 板有第-經緯向識別記號之第-電路 t70與㈣具有第二經緯向識別記號之第二電路板單 有如it先前技術，本技術方案之覆銅基板裁切方法具 銅基板^ 先’於覆銅基板上進行長度方向平行於覆 緯：之；°:第一電路板單元與長度方向平行於覆銅基板 面積，單元之混合排版，有效利用覆銅基板之 別記號=板材料與成本；其次，利用經緯方向識 之顛倒.# /反早凡進行標記’避免電路板單元經緯方向 號，於第艾Γ板單元製作第―經緯向識別記 區分第—雷 ί早兀衣作第二經緯向識別記號，可有效 〜路板單7G與第二電路板單元，避免兩者混合而 8 201004509 把成後續製程中出現漲縮不一致、線路錯位以及孔位偏差 等不良。 '【實施方式】 下面將結合實施例與附圖對本技術方案之覆銅基板裁 切方法作進一步之詳細說明。 本技術方案實施例提供之覆銅基板裁切方法包括以下 步驟： 第一步，提供覆銅基板10 ,其具有經向與緯向。 覆銅基板10可為玻纖布基覆銅基板、紙基覆銅基板、 複合基覆銅基板、芳醯胺纖維無紡布基覆銅基板以及合成 纖維基覆銅基板等。 請參閱圖1，本實施例中，該覆銅基板1〇為矩形，該 矩形覆銅基板10之原始尺寸較大，需裁切成複數小尺寸電 路板單元以便於後續加工製造，進而形成電路板成品。該 電路板單元通常亦為矩形。 第二步’根據預定電路板單元20之尺寸對覆銅基板W 進行排版，並使得排版後之覆銅基板10包括長度方向平行 於覆銅基板10經向之複數第一電路板單元22與長度方2 平行於覆銅基板10緯向之複數第二電路板單元24。 请參閱圖2’建立直角坐標系χογ，其中γ軸方向代 表覆銅基板10之經向，X軸方向代表覆銅基板1〇之緯向。 本實施例中，該覆銅基板10之長度方向即長邊平行於Y轴 方向，寬度方向即短邊平行於X軸方向。 9 201004509 對覆銅基板10進行排版時，以使覆銅基板10可排佈 最多電路板單元20為佳。本實施例中，於覆銅基板10上 : 排佈九個第一電路板單元22以及兩個第二電路板單元24。 ; 具體地，首先，於覆銅基板10上根據電路板單元20 之尺寸沿X軸方向依次排佈第一組之三個第一電路板單元 22,該第一電路板單元22之長度方向平行於Y軸方向，寬 度方向平行於X軸方向。其次，於上述第一組三個第一電 路板單元22之下方再沿X軸方向依次排佈第二組之三個第 一電路板單元22。再次，於上述第二组三個電路板單元之 下方再沿X軸方向依次排佈第三組之三個第一電路板單元 22。最後，由於覆銅基板10於排佈九個第一電路板單元22 後還有很大之餘料，該餘料於Y軸方向之長度小於電路板 單元20之長度，而大於電路板單元20之寬度。因此，可 於覆銅基板10之餘料沿X軸方向依次排佈兩個第二電路板 早元24 ’該弟二電路板早元24之長度方向平行於X轴方 向，寬度方向平行於Y軸方向。從而，按照圖2之方式進 行排版時，可有效利用覆銅基板10之面積。 當然，相鄰電路板單元20之間應預留一定間隙。本實 施例中，該間隙約為0.5mm〜2mm，以避免裁切時對相鄰電 路板單元20產生影響。 另外，亦可於覆銅基板10先排佈第二電路板單元24， 再排佈第一電路板單元22，僅需最大限度地利用覆銅基板 10之面積即可。 第三步，於第一電路板單元22製作第一經緯向識別記 10 201004509 破，=二電路板單元24製作第二經緯向識別記號。 Π 3’利用機械加工、雷射加工或化學钱刻等方 單元22上製作第一經緯向識別記號，於 電路板Μ24上製作第二經緯向識別記號。該第-^向朗記號與第；輯向酬記號可為—個或複數通 、匕。當第-經緯向識別記號與第二經緯向識別記號為一個 通孔時，該通孔之橫截面可為不等腰三㈣，該不等腰三 角形之長邊對應第-電路板單元22之長度方向，短邊對應 1電路板單70 22之寬度方向；於第二電路板單元24亦 製作一個通孔，該通孔之橫截面亦為不等腰三角形，該不 專腰一角开》之長邊對應第二電路板單元24之長度方向，短 邊對應第二電路板單元24之寬度方向。或者僅於第一電路 板單元22製作不等腰三角形通孔，第二電路板單元24不 製作不等腰三角形通孔，以識別第一電路板單元22與第二 電路板單元24。 當第一經緯向識別記號與第二經緯向識別記號為複數 通孔時，該第一經緯向識別記號包括第一識別記號22〇2與 第二識別記號2222，該第二經緯向識別記號包括第三識別 記號2402、第四識別記號2422與第五識別記號2424。該 第一識別記號2202、第二識別記號2222、第三識別記號 2402、第四識別記號2422與第五識別記號2424可為圓形 通孔、方形通孔或五邊形通孔等。本實施例中，該第一識 別記號2202、第二識別記號2222、第三識別記號2402、第 四識別記號2422與第五識別記號2424均為圓形通孔，其 11 201004509 直控均約為1mm。 具體地，於該第一電路板單元22定義出相對之第一端 部220與第二端部222，該第一端部22〇與第二端部222 為第一電路板單元22相對之兩長邊或兩短邊所在之兩區 域。本實施例中，以第一電路板單元22兩短邊所在之兩區 域分別作為第-端部22〇與第二端部222。該第一識別記號 2202位於第一端部220之頂角區域，該第二識別記號2222 位於第二端部222之中間區域。 類似地，該第二電路板單元24具有相對之第三端部 240與第四端部242。該第三識別記號24〇2位於第三端部 240之頂角區域，該第四識別記號2422位於第四端部a" 之頂角區域，其與第三識別記號蠢相對；該第五識別記 號2424位於第四端部242之令間區域。優選地，該第三識 別記號2402與第四識別記號2422之丫軸座標相同，該第 四識別記號2422與第五識別記號2424之χ軸座標相同， 即第二識別記號2402與第四識別記號2422位於同一緯 度，第四識別記號2422與第五識別記號2424位於同一^ 度。 、 ^ 從而，操作人員僅需根據第一識別記號22〇2、第二識 別記號2222、第三識別記號繼、第四識別記號助: 及第五識別記號2424之相對位置與數量關係即可識別電路 板單元20之經緯方向，並能對第一電路板單元與第二 電路板單元24進行區分，以避免後續疊板時出現顛倒㈣ 亂0 、 12 201004509 當然，該經緯向識別記號之開設並不限於以上所描述 之方式，僅需可幫助操作人員識別電路板單元20之經緯方 : 向以及將第一電路板單元22與第二電路板單元24區分開 之經緯向識別記號均於本方法保護範圍内。 第四步，裁切覆銅基板10以得到第一電路板單元22 與第二電路板單元24。 利用裁切裝置（圖未示）對覆銅基板10進行裁切後， 還可進一步分別將第一電路板單元22與第二電路板單元 24進行分類堆疊加工製作。分類製作之前，可利用第一電 路板單元22之第一經緯向識別記號與第二電路板單元24 之第二經緯向識別記號將第一電路板單元2 2與第二電路板 單元24進行區分並堆疊，如圖4所示，以方便進行後續製 程。 堆疊作業完成後，再將電路板單元進行鑽孔、鍍銅、 蝕刻、曝光以及顯影等一系列製程，以製造電路板成品。 本技術方案之覆銅基板裁切方法可有效利用覆銅基板 10之面積。例如，當提供之覆銅基板10之尺寸為72mmx 48mm，預定設計之電路板單元20之尺寸為17.5mmx 15.6mm 時，採用本技術方案之覆銅基板裁切方法進行排版時，最 後能裁切得到Η—個電路板單元20，具有較高之覆銅基板 10利用率。 並且，本技術方案利用經緯方向識別記號對電路板單 元20進行標記，避免電路板單元20經緯方向顛倒，並且 可有效區分第一電路板單元22與第二電路板單元24,避免 13 201004509 線路錯位以 兩者混合而造成後續製程中出現漲縮不—致 及孔位偏差等不良。 絲上所述，本發明確已符合發明專利之 提出專射請。惟’以上所述者僅為本發明之較佳實^方 式’自不能以此限制本案之申請專利範圍 二 士援:本發明之精神所作之等效修飾或變= 應涵盍於以下申請專利範圍内。 【圖式簡單說明】 圖ί係本技術方案實_提供之覆銅基板之示音圖。 示意圖 圖2係本技術方案實_提供之對覆銅基板排版後之 圖3係本技術方案實施例提供之於第—電路板單元標 =第-經緯向朗記號與於第二電路板單元標示第二經緯 向識別記號之示意圖。 $ 4係本技術方案實施例提供之裁切覆銅基板後堆疊 弟-電路板單元與第二電路板單元之示意圖。 【主要元件符號說明】 覆銅基板 10 電路板單元 20 第一電路板單元 22 第二電路板單元 24 弟一識別記號 2202 第二識別記號 2222 201004509 第三識別記號 2402 第四識別記號 2422 第五識別記號 2424 第一端部 220 第二端部 222 第三端部 240 第四端部 242 15201004509 IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board manufacturing technology, and more particularly to a copper-clad substrate: a cutting method. [Prior Art] With the rapid development of the electronics industry, the circuit board manufacturing technology, which is the basic component of electronic products, is becoming more and more important, and the production requirements for lines and holes are becoming more and more refined. The circuit board has single panel, double panel and multi-layer board, which are all made by a series of processes such as cutting, drilling, etching, exposure and development of the copper-clad substrate. For details, see "Dielectric characterization of printed circuit board substrates" by C. H. Steer et al., Proceedings of the IEEE, Vol. 39, No. 2 (August 2002). During the manufacturing process of a circuit board, it is usually necessary to cut a large-sized copper clad substrate into a plurality of small-sized circuit board units. The main components of the copper-clad substrate include fiberglass cloth and copper foil. Among them, the glass fiber cloth is used as a carrier of the copper foil, and is made of glass fiber by a plain weave method. However, since the fiber structure of the fiberglass cloth itself is different in the arrangement in the warp and weft direction, the copper-clad substrate has different structures in the warp and weft directions, and the copper-clad substrate has different shrinkage rates in the warp and weft directions. Therefore, in order to ensure the quality of the panel, the previous copper-clad substrate adopts a single typesetting method during cutting, and the single typesetting method makes the copper-clad substrate have a large residual material and cannot be utilized, and has a low utilization ratio of the copper-clad substrate. Thereby increasing the manufacturing cost of the board. 7 201004509 In view of this, the method of cutting the substrate is actually a copper coating to improve the utilization efficiency of the copper-clad substrate. [Inventive content] The following will be based on the specific sinus y, the rate of the copper substrate cutting method The invention can improve the copper-clad substrate using the A-board cutting method, which comprises the following steps: providing the copper-clad substrate after the copper-clad typesetting comprises typesetting, and making the electrical length direction parallel to the complex symbol of the latitudinal direction of the copper-clad substrate, in the second Circuit ^ _ plate 制作 70 to make the first - latitude and longitude identification copper Α纟 Α纟 兀 兀 兀 兀 兀 兀 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The second circuit board has the same as the prior art, and the copper substrate cutting method of the technical solution has a copper substrate. First, the length direction is parallel to the weft covering on the copper-clad substrate; °: the first circuit board unit and The length direction is parallel to the area of the copper-clad substrate, and the unit is mixed and typeset, effectively utilizing the mark of the copper-clad board = board material and cost; secondly, using the warp and weft direction to identify the reverse. # / anti-early mark - 'avoid the board The latitude and longitude direction number, in the first Γ Γ 单元 单元 第 ― 经 经 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷 雷Mixed and 8 201004509 into the subsequent process in the process of inconsistent expansion and contraction, line misalignment and hole position deviation. [Embodiment] The copper-clad substrate cutting method of the present technical solution will be further described in detail below with reference to the embodiments and the accompanying drawings. The copper-clad substrate cutting method provided by the embodiment of the present technical solution includes the following steps: In the first step, a copper-clad substrate 10 having a warp direction and a weft direction is provided. The copper-clad substrate 10 may be a fiberglass-based copper-clad substrate, a paper-based copper-clad substrate, a composite copper-clad substrate, an alimentamide-based nonwoven fabric-based copper-clad substrate, or a synthetic fiber-based copper-clad substrate. Referring to FIG. 1 , in the embodiment, the copper-clad substrate 1 is rectangular, and the rectangular copper-clad substrate 10 has a large original size, and needs to be cut into a plurality of small-sized circuit board units for subsequent processing and manufacturing, thereby forming a circuit. Finished board. The board unit is also typically rectangular. The second step 'types the copper-clad substrate W according to the size of the predetermined circuit board unit 20, and causes the copper-clad substrate 10 after the layout to include the plurality of first circuit board units 22 and the length direction parallel to the copper-clad substrate 10 The square 2 is parallel to the plurality of second circuit board units 24 in the weft direction of the copper clad substrate 10. Referring to Fig. 2', a Cartesian coordinate system χογ is established, wherein the γ-axis direction represents the warp direction of the copper-clad substrate 10, and the X-axis direction represents the weft direction of the copper-clad substrate 1〇. In the present embodiment, the longitudinal direction of the copper clad substrate 10, i.e., the long side, is parallel to the Y-axis direction, and the width direction, that is, the short side, is parallel to the X-axis direction. 9 201004509 When the copper clad substrate 10 is typeset, it is preferable that the copper clad substrate 10 can be arranged with the most circuit board unit 20. In the present embodiment, on the copper clad substrate 10, nine first circuit board units 22 and two second circuit board units 24 are arranged. Specifically, first, three first circuit board units 22 of the first group are sequentially arranged on the copper clad substrate 10 in the X-axis direction according to the size of the circuit board unit 20, and the length direction of the first circuit board unit 22 is parallel. In the Y-axis direction, the width direction is parallel to the X-axis direction. Next, a second group of three first circuit board units 22 are sequentially arranged in the X-axis direction below the first group of three first circuit board units 22. Further, three third circuit board units 22 of the third group are sequentially arranged in the X-axis direction below the second group of three circuit board units. Finally, since the copper clad substrate 10 has a large amount of material after the nine first circuit board units 22 are arranged, the length of the residual material in the Y-axis direction is smaller than the length of the circuit board unit 20, and larger than the circuit board unit 20 The width. Therefore, two pieces of the second circuit board can be arranged in the X-axis direction in the X-axis direction of the remaining material of the copper-clad substrate 10, and the length direction of the second board 24 is parallel to the X-axis direction, and the width direction is parallel to Y. Axis direction. Therefore, when the layout is performed in the manner shown in Fig. 2, the area of the copper clad substrate 10 can be effectively utilized. Of course, a certain gap should be reserved between adjacent circuit board units 20. In the present embodiment, the gap is about 0.5 mm to 2 mm to avoid the influence of the adjacent circuit board unit 20 at the time of cutting. Further, the second circuit board unit 24 may be arranged first on the copper clad substrate 10, and the first circuit board unit 22 may be arranged, and only the area of the copper clad substrate 10 may be utilized to the maximum extent. In the third step, the first warp and weft identification mark 10 201004509 is broken on the first circuit board unit 22, and the second circuit board unit 24 creates the second warp and weft identification mark. Π 3' creates a first warp and weft identification mark on the unit 22 by machining, laser processing or chemical money engraving, and creates a second warp and weft identification mark on the circuit board 24. The first-to-horizontal sign and the first-order sign can be one- or plural-numbered. When the first latitude and longitude direction identification mark and the second latitude and longitude direction identification mark are one through hole, the cross section of the through hole may be unequal waist three (four), and the long side of the unequal waist triangle corresponds to the first circuit board unit 22 In the length direction, the short side corresponds to the width direction of the single circuit board unit 70 22; a through hole is also formed in the second circuit board unit 24, and the cross section of the through hole is also an isosceles triangle, which is not a waist angle. The long side corresponds to the length direction of the second circuit board unit 24, and the short side corresponds to the width direction of the second circuit board unit 24. Alternatively, the isosceles triangular through holes are formed only in the first circuit board unit 22, and the second circuit board unit 24 does not form the isosceles triangular through holes to identify the first circuit board unit 22 and the second circuit board unit 24. When the first warp and weft identification mark and the second warp and weft identification mark are plural through holes, the first warp and weft identification mark includes a first identification mark 22〇2 and a second identification mark 2222, and the second warp and weft identification mark includes The third identification mark 2402, the fourth identification mark 2422, and the fifth identification mark 2424. The first identification mark 2202, the second identification mark 2222, the third identification mark 2402, the fourth identification mark 2422, and the fifth identification mark 2424 may be circular through holes, square through holes, or pentagonal through holes. In this embodiment, the first identification mark 2202, the second identification mark 2222, the third identification mark 2402, the fourth identification mark 2422 and the fifth identification mark 2424 are all circular through holes, and the 11 201004509 direct control is about 1mm. Specifically, the first circuit board unit 22 defines an opposite first end portion 220 and a second end portion 222. The first end portion 22 and the second end portion 222 are opposite to the first circuit board unit 22 The two areas where the long side or the two short sides are located. In this embodiment, the two regions where the two short sides of the first circuit board unit 22 are located serve as the first end portion 22 and the second end portion 222, respectively. The first identification mark 2202 is located at a top corner area of the first end portion 220, and the second identification mark 2222 is located at an intermediate portion of the second end portion 222. Similarly, the second circuit board unit 24 has opposing third and second ends 240, 242. The third identification mark 24〇2 is located at a top corner area of the third end portion 240, and the fourth identification mark 2422 is located at a top corner area of the fourth end portion a", which is stupid with the third identification mark; the fifth identification The indicia 2424 is located in the inter-interval region of the fourth end 242. Preferably, the third identification mark 2402 is the same as the axis coordinate of the fourth identification mark 2422, and the fourth identification mark 2422 is the same as the axis coordinate of the fifth identification mark 2424, that is, the second identification mark 2402 and the fourth identification mark. The 2422 is located at the same latitude, and the fourth identification mark 2422 is located at the same level as the fifth identification mark 2424. Therefore, the operator only needs to recognize the relative position and quantity relationship of the first identification mark 22〇2, the second identification mark 2222, the third identification mark follow-up, the fourth identification mark help: and the fifth identification mark 2424. The latitude and longitude direction of the circuit board unit 20, and can distinguish the first circuit board unit from the second circuit board unit 24 to avoid the reverse of the subsequent stacking. (4) Chaos 0, 12 201004509 Of course, the warp and weft identification mark is opened and Not limited to the manner described above, it is only necessary to assist the operator in identifying the warp and weft of the circuit board unit 20: the latitude and longitude identification marks that distinguish and distinguish the first circuit board unit 22 from the second circuit board unit 24 are in the present method. Within the scope of protection. In the fourth step, the copper clad substrate 10 is cut to obtain the first circuit board unit 22 and the second circuit board unit 24. After the copper clad substrate 10 is cut by a cutting device (not shown), the first circuit board unit 22 and the second circuit board unit 24 may be further classified and stacked. Before the classification is made, the first circuit board unit 22 and the second circuit board unit 24 can be distinguished by using the first warp and weft identification mark of the first circuit board unit 22 and the second warp and weft identification mark of the second circuit board unit 24. And stacked, as shown in Figure 4, to facilitate subsequent processes. After the stacking operation is completed, the circuit board unit is subjected to a series of processes such as drilling, copper plating, etching, exposure, and development to manufacture a finished circuit board. The copper-clad substrate cutting method of the present invention can effectively utilize the area of the copper-clad substrate 10. For example, when the size of the copper-clad substrate 10 provided is 72 mm x 48 mm, and the size of the circuit board unit 20 of the predetermined design is 17.5 mm x 15.6 mm, when the copper-clad substrate cutting method of the present technical solution is used for typesetting, the final cutting can be performed. A circuit board unit 20 is obtained, which has a higher utilization ratio of the copper-clad substrate 10. Moreover, the technical solution marks the circuit board unit 20 by using the warp and weft direction identification marks, avoiding the circuit board unit 20 from being reversed in the warp and weft direction, and effectively distinguishing the first circuit board unit 22 from the second circuit board unit 24 to avoid the 13 201004509 line misalignment. The combination of the two causes the expansion and contraction in the subsequent process, which is not caused by the hole position deviation. As stated on the silk, the present invention has indeed met the proposed patent for the invention patent. However, 'the above is only the preferred embodiment of the present invention'. The patent application scope of the present invention is not limited by this. The equivalent modification or variation of the spirit of the present invention should be applied to the following patent application. Within the scope. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sound diagram of a copper-clad substrate provided by the present technical solution. FIG. 2 is a schematic diagram of the present invention. The third embodiment of the present invention provides the first circuit board unit mark=the first-latitude and longitude mark and the second circuit board unit. A schematic diagram of the second latitude and longitude identification mark. $4 is a schematic diagram of stacking a chip-board unit and a second circuit board unit after cutting the copper-clad substrate provided by the embodiment of the present technical solution. [Description of main component symbols] Copper-clad substrate 10 Circuit board unit 20 First circuit board unit 22 Second circuit board unit 24 Brother-identification mark 2202 Second identification mark 2222 201004509 Third identification mark 2402 Fourth identification mark 2422 Fifth identification Symbol 2424 first end 220 second end 222 third end 240 fourth end 242 15