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TW200933762A - Integrated circuit package system with offset stacking and anti-flash structure - Google Patents

Integrated circuit package system with offset stacking and anti-flash structure

Info

Publication number
TW200933762A
TW200933762A TW097142595A TW97142595A TW200933762A TW 200933762 A TW200933762 A TW 200933762A TW 097142595 A TW097142595 A TW 097142595A TW 97142595 A TW97142595 A TW 97142595A TW 200933762 A TW200933762 A TW 200933762A
Authority
TW
Taiwan
Prior art keywords
integrated circuit
carrier
package
flash
device structure
Prior art date
Application number
TW097142595A
Other languages
Chinese (zh)
Other versions
TWI469230B (en
Inventor
Seng Guan Chow
Heap Hoe Kuan
Linda Pei Ee Chua
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of TW200933762A publication Critical patent/TW200933762A/en
Application granted granted Critical
Publication of TWI469230B publication Critical patent/TWI469230B/en

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Classifications

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An integrated circuit packaging method includes: mounting a device structure in an offset location over a carrier with the device structure having a bond pad and a contact pad; connecting an electrical interconnect between the bond pad and the carrier; forming an anti-flash structure over the device structure with the anti-flash structure exposing the contact pad; and forming a package encapsulation adjacent to the anti-flash structure and over the carrier.

Description

I 200933762 m 六、發明說明： ^ [相關申請案之交互參照] 本申請案含有與由 Heap Hoe Kuan、Seng Guan Chow、 Linda Pei Ee Chua 及 Dioscoro A. Merilo 所同時提出申 請相關之美國專利申請案的主題標的，該申請案之名稱為 “Mountable Integrated Circuit Package System with Mountable Integrated Circuit Die” 。該相關申請索已 讓渡給STATS ChipPAC股份有限公司，其案件編號為 ❹ 27-449 〇 本申請案亦含有與由Heap Hoe Kuan、Seng Guan Chow、 Linda Pei Ee Chua 及 Dioscoro A. Meri lo 所同時提出申 請之美國專利申請案相關的主題標的，該申請案之名稱為 “Integrated Circuit Package System with Interconnect Lock” ，該申請案已讓渡給 STATS ChipPAC 股份有限公司，其案件編號為27-450。 本申請案復含有與由Seng Guan Chow、Linda Pei Ee Chua及Heap Hoe Kuan所同時提出申請之美國專利申請案 相關的主題標的，該申請案之名稱為“Integrated Circuit Package System with Offset Stacking”，該申 請案已讓渡給STATS ChipPAC股份有限公司，其案件編號 為 27-493 〇 【發明所屬之技術領域】 本發明大體係有關於積體電路封裝件系統，尤其是關 於帶有包覆體（encapsulation)的積體電路封裝件系統。 3 94511 200933762 . 【先前技術】 ， 為求介接（interface)積體電路與其他電路，通常會將 積體電路安裝於導線架上或基板上。每個積體電路具有連 結墊（bondingpad)，該連結墊係使用極纖細的金線或鋁線 或者如銲球之導電球而個別地連接至基板的接觸點 (contact)或終端墊（terminal pad)。屆時藉由個別地將組 件包覆於模造塑膠或陶竟體（ceramic body )中而予以封 裝，以產生積體電路封裝件。 積體電路封裝技術已藶經在單一電路板或基板上所安 裝之積體電路之數量上的增加《新穎的封霁設計係更加縮 小的形狀因素（form factor)，例如物理尺寸及經封裝的積 體電路的形狀，且提供整體積體電路密度之顯著增加。 然而，積體電路密度持續受限於可用於安裝個別的積 體電路於基板上之「基板面（real estate)」。即使如個人 電腦（personal computer, PC)、計算伺服器（conipute 0 server)及儲存伺服器（st〇rage server)等的較大形狀因 素系統’係需要粟多積體電路於相同或較小的「基板面」 中。特別尤其是如行動電話、數位相機、音樂播放器.、個 人數位助理（personal digital assistant, PDA)及定位裝 置（location-based device)之可攜式（portable)個人電 子商品’已進一步驅使增加積體電路密度之需求。 所增加的積體電路密度已導致能夠封裝多於一個積體 電路之多晶片封裝件之發展。每個封裝件係提供用於個別 積體電路及能夠使積體電路電性連接至週邊電路之一層或 94511 4 200933762 多層互連線之機:械支援。 目前多晶片封裝件亦常被稱為多晶片模組，典型地由 有一組分開的積體電路零件直接接置於其上之印刷電路板 (printed circuit board’ PCB)基板所組成。已發現此種 多晶片封裝件來增加積體電路密度和最小化、改善訊號傳 遞速度、減縮整體積體電路尺寸及重量、改善效能以及降 低成本一所有電腦工業之主要目的。 ΟI 200933762 m VI. INSTRUCTIONS: ^ [Reciprocal References for Related Applications] This application contains US patent applications related to applications filed by Heap Hoe Kuan, Seng Guan Chow, Linda Pei Ee Chua and Dioscoro A. Merilo The subject matter of the application is "Mountable Integrated Circuit Package System with Mountable Integrated Circuit Die". The relevant application has been transferred to STATS ChipPAC Co., Ltd., the case number is ❹ 27-449. This application also contains the same time as Heap Hoe Kuan, Seng Guan Chow, Linda Pei Ee Chua and Dioscoro A. Meri lo. The subject matter of the U.S. patent application filed with the name of the application is "Integrated Circuit Package System with Interconnect Lock", which has been assigned to STATS ChipPAC Co., Ltd., with case number 27-450. The present application contains subject matter related to the U.S. Patent Application Serial No. 5, the entire disclosure of which is incorporated herein by reference. The application has been transferred to STATS ChipPAC Co., Ltd., and its case number is 27-493. [Technical Fields of the Invention] The large system of the present invention relates to an integrated circuit package system, especially regarding an encapsulation (encapsulation). Integrated circuit package system. 3 94511 200933762 . [Prior Art] In order to interface an integrated circuit with other circuits, the integrated circuit is usually mounted on a lead frame or on a substrate. Each integrated circuit has a bonding pad that is individually connected to a contact or terminal pad of the substrate using a very thin gold wire or aluminum wire or a conductive ball such as a solder ball. ). The assembly is then packaged by individually wrapping the component in a molded plastic or ceramic body to produce an integrated circuit package. Integrated circuit packaging technology has increased the number of integrated circuits installed on a single board or substrate. "The novel package design is a more compact form factor, such as physical size and packaged The shape of the integrated circuit and provides a significant increase in the density of the entire bulk circuit. However, the integrated circuit density continues to be limited to the "real estate" that can be used to mount individual integrated circuits on the substrate. Even large form factor systems such as personal computers (PCs), computing servers (conipute 0 servers), and storage servers (st〇rage servers) require the same or smaller integrated circuits. In the "substrate surface". In particular, portable personal electronic products such as mobile phones, digital cameras, music players, personal digital assistants (PDAs) and location-based devices have further driven the increase. The need for bulk circuit density. The increased integrated circuit density has led to the development of multi-chip packages capable of packaging more than one integrated circuit. Each package provides an individual support circuit and a device that enables the integrated circuit to be electrically connected to one of the peripheral circuits or the 94511 4 200933762 multilayer interconnect: mechanical support. Multi-chip packages are also commonly referred to as multi-wafer modules, typically consisting of a printed circuit board (PCB) substrate with a separate set of integrated circuit components directly attached thereto. Such multi-chip packages have been found to increase the density and minimize the integrated circuit, improve signal transfer speed, reduce the size and weight of the entire bulk circuit, improve performance, and reduce cost. Ο

G 因夕曰曰片封裝件通常必須於積體電路及積體電路連接 能被測試之前便預先組裝，故多晶片封裝件不論是垂直或 水平配置’都可能呈關題。因此，當安裝並連接積體電 路於夕μ片模組巾時，無法個別地測試個別的積體電路及 連接，且不可能於_至較大電路之前確認「已知良好晶 粒a_-g〇〇d-die，KGD)」。目此，習知多晶片封裂件會 導致組裝製程良率的問題。此無法確認之製造 因此較不可靠且更易導致組裝缺陷。 再者’於典型的多晶片封裝件中，垂直堆疊之積體電 γ斤呈現的_可能會多於持配置之㈣祕纽件之 3二進一步複雜其製造流程。這會變得較難以測試而 積體電路之實際故障模式。再者，基板 或測試期間受損，而複雜其製造流 程且增加成本。 缺對於垂直及水平之多晶片料件二者而言，於多重積 體電路、經堆疊封裝之藉驴带 夕里積 門，^ 電路或其結合之積體電路之 曰夕日曰、之組裂必須具有可靠的電性及機械性接 94511 200933762 置。舉例而’用於形成經封裝的積體電路之包覆製程可 能造成如模造溢料（Hash)及鑄漏（bleed)之污染，進而妨 礙可靠的接置。另一範例中，對於在其包覆體中具有凹部 之積體電路封裝件而言，係使用順形的（contoured)模具 (mold chase)以形成該凹部，該凹部係增加模造溢料風 險、由於與模具之順形部分接觸而對封裝結構造成傷害、 以及用以於包覆體中之所需凹部而設計特定模具之製造成 本。 〇G-in-situ package must usually be pre-assembled before the integrated circuit and integrated circuit connections can be tested, so multi-chip packages, whether vertical or horizontal, may be relevant. Therefore, when the integrated circuit is mounted and connected to the wiper blade, individual integrated circuits and connections cannot be individually tested, and it is impossible to confirm "known good die a_-g" before _ to a larger circuit. 〇〇d-die, KGD)". For this reason, conventional multi-wafer sealing members can cause problems in assembly process yield. This unconfirmable manufacturing is therefore less reliable and more susceptible to assembly defects. Furthermore, in a typical multi-chip package, the vertically stacked integrated body _ _ _ may present more than the configuration of the (4) secret components to further complicate its manufacturing process. This can become more difficult to test and the actual failure mode of the integrated circuit. Furthermore, the substrate or the test period is damaged, which complicates its manufacturing process and increases the cost. In the case of both vertical and horizontal multi-chip materials, the multi-integrated circuit, the stacked package, the integrated circuit, the circuit or the combination of the integrated circuit must be With reliable electrical and mechanical connection to 94511 200933762. For example, the cladding process used to form the packaged integrated circuit can cause contamination such as molded and bleed, which can impede reliable attachment. In another example, for an integrated circuit package having a recess in its cladding, a contoured chase is used to form the recess, which increases the risk of molding flash, The cost of designing a particular mold is due to damage to the package structure due to contact with the conforming portion of the mold, as well as the desired recesses used in the cladding. 〇

因此，對積體電路封裝件系統而言，仍需提供低製造 成本、增進的良率、改善的可靠度及較佳的靈活度 (flexibility)’以提供更多功能性及於印刷電路板上較少 的佔板面積（footprint)。有鑑於對節省成本及增進效率的 持續增加之需求，發現這些問題的答案變得愈來愈重要。 尋求這些問題的解答已持續了好一段時間，但是習知 發展並未教示或建議任何解答，因此，該項技術中熟習技 術者長期以來皆引頸期盼這些問題的解答。 【爹明内容】 本發明係提供一種積體電路封裝方法，係包含：以傾 移位置安裝裝置結構於承載件上面，該裝置結構具有連為 墊及接觸墊；於該連結墊與該承餅之間連接電性互連； 於該裝置結構上面形成防溢料結構，該防溢料結構係外潭 該接觸墊；以及於該承載件上面相鄰於該防溢料結構形居 封裝件包覆體。 本發明之特定實施例具有另外附加或取代該些從上过 94511 200933762 ..所提及之其他實施態樣。熟習該項技術者在參照附加的圖 . 式時，可從閱讀詳盡的下文中，明瞭該等態樣。 J實施方式】 接下來的具體實施例係經過充分詳細描述，以使孰習 該項技術者得以製作及使用本發明。應理解的是，皇它'實 施例會根據本揭露内容而變得明顯，而系統、製程或機械 變化可加以達成，而不背離本發明之範嘴。 . 在下列描述中’係給定許多特定細節以提供本發明完 整的理解。然而，將清楚的是，毋需該些特定細節也能實 施本發明。為求避免混淆本發明，一些廣為周知的電路、 系統組構及製程步驟並未詳盡地揭露。同樣地，顯示該系 統之具體實施例的附圖係部分圖解且不按比例的，尤其之 中的-些尺寸則為了表達清楚而於圖式中顯得特別誇張。 一般而言，本發明能於任何方位上進行操作。 此外為求α楚且易於將其朗、描述及理解，所揭 ©露及描述之具有某些共同特徵之多個具體實施例中 ，彼此 類似或相同的特徵通常以相同的㈣符號描述。為了描述 上的方便，該些具體實施例係已經以第一具體實施例、第 .二具體實施=等等來予以標號，而並非有意對本發明具有 任何其他含意或提供限制。 為了附註之目的’於此使用之術語「水平（h〇riz〇ntai、 係定義為平行於麵電路之平誠表m管其方位， (〇rientatlQn)。術語「垂直（谱ticaD」指的是垂直於: 才疋義之水千之方向。例如「上方（above)」、「下方⑽⑽ 94511 7 200933762 「底部（bottom)」、「頂部（t〇p)」、「侧（side)」（如「側壁 (sidewa ⑴」）、「較高(higher)」、「較低 方（upper)」、「上面（over)」、「下面(under)」之術語則對 應於該水平平面而定義。術語「上（⑻」聽指元件間的 直接接觸。使用於此之術語「處理（passing)」則包含 材料的沉積、圖案化、曝光、顯影、侧、清洗、模造及/ 或材料的移除，或如形朗述結構之所需者。於此使用之 ❹ Ο 術語「系統」則意指依據該詞所使用之内容中本發明之方 法及設備。 現在參照第1圖，其俦龜；士 &amp; 矛'顯不本發明之第一具體實施例 體電路封裝件系、统1〇〇之上視圖。該上視圖係描綠 :覆盍(⑽相體電路封裝件系統1〇〇。該上視圖係描 緣具有接觸塾1〇4及連結塾⑽之裳置結構1〇2(如基板） =承載件108(如基板）上面。該裝置結構1〇2之侧邊〈s㈣ 110係顯不成平行於該承齡⑽之邊緣112。該裝置結構 102係顯示成位於該承载件⑽上面之偏移位置，而非該 承載件108上面之中央位置。 、接觸墊104係顯示於裳置結構1()2之週邊區域上面之 =溢料結構114之環内，該防溢料材料114_如非導電 環氧基樹脂1封劑、聚合物材料、固線樹脂材料（如 lock resin material)或可f透的轉（卿咐敝心 adheS1Ve)。如轉（bQnd _)或帶狀導線（他⑽_ 町e)之電性互連116能於連結#1〇6與承載件⑽之間連 接。該防溢料結構114係覆蓋連接_裝置料1()2之該 94511 200933762 . 電性互連116之末端。 . 如積體電路晶粒（dice)或經封裝的積體電路之第一積 體電路裝置118以及如離散的（discrete)電阻器或電容器 之被動裝置120，係安裝於該承載件1〇8上面。為求說明 之目的，該第一積體電路裝置118係顯示成相同類型之裝 置，然而應理解的是，該第一積體電路裝置118能彼此相 異，例如松異的類型、功能、尺寸或技術。亦為求說明之 目的，該被動裝置】20係顯示成相同類型之零件，然而應 理解的是，該被動裝置120能彼此相異。舉例而言，被動 裝置120能包含相異的電阻器、電容器、電感器（induct〇r) 或上述之結合。 現在參照第2圖，其係顯示第】圖沿線2之積體電 路封裝件系統100之剖面圖。該剖面圖係描繪如積體電路 晶粒之第二積體電路222安裝於該承載件108上面。如膜 膠之間隔件224能提供空隙（ciearance)予電性互連He以 ❹於該第二積體電路裝置222與該承載件108之間進行連接。 裝置結構102係安裝於該第二積體電路裝置222及該 承載件108上面。該裝置結構1〇2係顯示成位於該承載件 108上面之偏移位置，而非該承载件1〇8上面之中央位置。 於該裝置結構102之週邊區域上面之防溢料結構114、該 裝置結構102、該間隔件224及該第二積體電路裝置^ 能決定於該承载件108上面之封裝件包覆體⑽之 高度226。 吼锻· 封裝件包覆體228係於該承載件1〇8上面且覆蓋第一 94511 9 200933762 積體電路裝置118、被動裝置120、第二積體電路裝置222、 ’電性互連116及間隔件224。該封裝件包覆體228能相鄰 於該防溢料結構114，而形成外露該裝置結構1〇2之接觸 墊104之四部230 〇 卩方溢料賴114能提供多種功舉例而f，該防溢 料結構114係減輕或消除與裝置結構1〇2連接之電性互連 116之導線短路（wire sweep) ’從而改善良率並降低成本。 如另一範例，該防溢料結構.114能減輕或消除接觸墊1〇4 上面之模造溢料（mold f lashing)，從而改善可靠度、增進 良率以及降低成本。 如積體電路或被動元件之安裝裝置（m〇unting device) 232能視需要地（optionally)安裝於積體電路封裝件系統 100上面，而形成積體電路層疊封I系、统 (package-on-package system)。該安裝裝置 232 係以虛線 描繪。該安裝裝置232能安裝於裝置結構1〇2上面且於該 ❹ 凹部230内。 應理解的是’顯示於具體實施例中之第一積體電路裳 置118、第二積體電路裝置222以及安裝裝置232係用於 說明之目的。該第一積體電路裝置U8、該第二積體電路 裝置222以及該安裝裝置232能為晶圓級晶片尺寸封裝 (wafer level chip scale package，WLCSP)、重新佈線 (redistributed line, RDL)晶粒、陣列封裝件、無導腳封 裝件（leadless package)、導腳封裝件（leaded package)、 系統級封裝(system-in-package，SiP)、堆疊晶粒封裝 94511 10 200933762 牛封裝内封裝（package_ln_package，pip)、内嵌晶粒基 •板（embedded die substrate)或增進散熱封裝、腿蔽 封裝。 、現在參照第3圖，係顯示本發明之第二具體實施例中 以第1圖之上視圖為例之積體電路封裝件系統3〇〇之剖面 圖。該剖面圖係描繪被動裝置320及第一積體電路裝置 顺如積體電路晶粒）安裝於承載件繼上面。第二積體電 ❹路裝置322(如經封裝的積體電路）係以黏膠334安裝於承 载件308上面，且能相鄰於其中一個該第一積體電路裝置 318 〇 &lt; 該第二積體電路裝置322包含裝置結構3〇2作為其基 板。該第二積體電路裝置322係顯示成位於該承載件3〇8 上面之偏移位置而非該承載件308上面之中央位置。電性 互連316能連接該裝置結構302與該承載件3〇8。如一範 •例，該第二積體電路裝置322係顯示成倒置組構（inverted ❹ configuration)而使裝置結構302背對該承载件3〇8。 防溢料結構314係位於該裝置結構3〇2之週邊區域上 面及於該裝置結構302上面之電性互連316之一部份的上 面。該防溢料結構314及該第二積體電路裝置322能決定 於該承載件308上面之封裝件包覆體328之包覆體高度 326 〇 口又 封裝件包覆體328係於談承載件308上面且覆蓋第一 積體電路裝置318、被動裝置320、第二積體電路裝置322 及該電性互連316。該封裝件包覆體328能相鄰於該防溢 94511 11 200933762 . 料結構314，而形成外露該裝置結構302之接觸墊304之 . 凹部330。 如積體電路或被動元件之安裝裝置332能視需要地安 裝於積體電路封裝件系統300上面，而形成積體電路層叠 封裝系統。該安裝裝置332係以虛線描繪。該安裝裝置332 能安裝於裝置結構302上面且於該凹部330内。 現在參照第4圖，其係顯示本發明之第三具體實施例 中，積體電路封裝件系統400之上視圖。該上視圖係插矣會 ® 裝置結構402之接觸墊404外露於由防溢料結構414所形 成之凹部430中。封裝件包覆體428係相鄰於該防溢料結 .構 414 〇 現在參照第5圖’係顯不第4圖沿線5—5之積體電路 封裝件系統400之剖面圖。該剖面圖係描繪被動裝置52〇 及第一積體電路裝置518(如積體電路晶粒）安裝於承載件 508上面。第二積體電路裝置522(如經封裝的積體電路） ❹係以黏膠534安裝於第三積體電路裝置536(如覆晶晶片 (flip chip))上面，其中，第三積體電路裝置536係安裝 於該承載件508上面。該第三積體電路裝置536能相鄰於 其中一個第一積體電路裝置518。該第二積體電路裝置522 能懸空（overhang)於該其中一個第一積體電路裝置518。 該第二積體電路裝置522係包含裝置結構4〇2作為其 基板。該第一積體電路裝置522係顯示成位於該承載件508 上面之偏移位置，而非該承载件5〇8上面之中央位置。電 性互連516能連接該裝置結構402與該承載件508。如一 94511 12 200933762 - 範例，該第二積體電路裝置522係顯示成倒置組構而使裝 . 置結構402背對該承載件508。 防溢料結構414係位於該裝置結構4〇2之週邊區域上 面及於該裝置結構402上面之電性互連516之一部份的上 面。該防溢料結構414、該第二積體電路裝置522及該第 二積體電路裝置536能決定於該承載件5〇8上面之封裝件 包覆體428之包覆體高度526。 封裝件包覆體428係於該承載件508上面且覆蓋第一 積體電路裝置518、被動裝置520、第二積體電路裝置522、 該第三積體電路裝置536及該電性互連516。該封裝件包 覆體428能相鄰於該防溢料結構414，而形成外露該裝置 結構402之接觸塾4〇4之凹部430。 如積體電路或被動元件之安裝褒置532能視需要地安 裝於積體電路封展件系統棚上面，而形成積體電路層疊 封裝系統。該安裝裝置532係以虛線描繪。該安裝裝置532 ❹忐女裝於裝置結構402上面且於該凹部430内。 現在參照第6 ® ’其侧示本發明之第四具體實施例 中’積體電路封震件系统6〇〇之上視圖。該上視圖係描繪 無覆蓋的積體電路封裝件系統_。該上視圖係描! 會於承 載件608(如基板）上面之裝置結構6〇2(如基板），而各該裝 置結構602係具有接觸墊604及連結墊606。各該裝置結 構602之侧邊610係顯示成平行於該承載件之邊緣 612。各該裝置結構6〇2係顯示成位於該承載件⑽8上面之 偏移位置’而非該承载件6〇8上面之中央位置。 94511 13 200933762 _為^目㈣’該裝置結構602係顯示成彼此相同 =應理解的是，該裝置結構602能於尺寸、形狀、 Π 塾604之組構以及連結墊606之組構等方面上 置‘：結構6°2而言，接觸墊6〇4係顯示於裝 導域上面之防溢料結構614之環内。如 Ο Ο m2電性互連616能於連結墊咖與承載件 基:St該防溢料結構614係覆蓋連接於該裳置結 構602之該電性互連616之末端。 f ^1^路晶粒或_裝的積體電路之第—積體電路 ^坡以及如離散的電阻器或電容器之被動裝置620, 係女裝於該承载件_上面。為求說明之目的，該被動裝 置侧示成相同_之元件’然而應理解的是 動裝置62◦能為彼此相異的元件。舉例而言，被動裝置62〇 能包3相異的電阻器、電容器、電感器或上述之結合。 現在參照第7圖’其係顯示第6圖沿線7—7之積體電 路封裝件系統_之剖面圖。該·圖係⑽如積體電路 晶粒之第二積體電路722安裝於該承載件_上面。如膜 膠之間隔件724能提供空隙予電性互連㈣以於該第二積 體電路裝置722與料载件·之間進行連接。為求說明 之目的，該第二積體電路I置722係顯示成相同類型之裝 置’然而應理解岐，該第二積體電路裝置722能彼此相 異，例如相異的類型、功能、尺寸或技術。 裝置結構602係安裝於該第二積體電路裝i 722及該 94511 14 200933762 承載件608上面。該裝置結構6〇2係顯示成位於該承載件 ，608上面之偏移位置’而非該承载件6〇8上面之中央位置。 於該裝置結構602之週邊區域上面之防溢料結構614、該 裝置結構602、該間隔件724及該第二積體電路裳置^ ^決定於該承載#_上面之封裂件包覆體m之包覆體 高度726。 封裝件包覆體728係於該承載件6〇8上面且覆蓋第6 ❹21積體電路裝置618、被動裝置韻、第二積體電路 裝置722、電性互連616及間隔件724。該封裳件包覆體 728 t相鄰於該防溢料結構614，而形成從各該裝置結 602外露接觸墊6〇4之凹部730。 防溢料結構614能提供多種功能。舉例而言，該防溢 料結構614係減輕或消除與裝置結構6〇2連接之電二互連 616之導線短路，從而改善良率並降低成本。如另一範例， 該防溢料結構614能減輕或消除接觸塾_上面之模决 〇料，從而改善可靠度、增進良率以及降低成本。…皿 ㈣體電路或被動元件之安裝裝置732能視需要地安 裝於频封裝㈣統_上面，㈣成_電路層疊 封裝系統。該安裝裝置732係以虛線描繪。該安裝裝置7犯 此安裝於裝置結構6〇2上面且於讀凹部73〇内。為邰明 之目的，該安裝裝置732係顯示成相同類型之裝置^而 應理解的是，該安裝裝置732能彼此相異，'例如相㈣類 型、功能、尺寸或技術。 、 現在參照第8圖’其係顯示本發明之第五具體實施例 . 94511 15 200933762 中’積體電路封裝件系統800之上視圖。該上視圖係福紛 無覆盍的積體電路封裝件系統800。該上視圖係描終罝' 接觸墊804及連結墊806之裝置結構802(如基板）於&amp;^ 件808(如基板）上面。該裝置結構8〇2之侧邊81〇係顯示 成非平行於該承載件8〇8之邊緣812。該裝置結構8〇2 : 顯示成位於該承載件808上面之偏移位置，而非該承载件 808上面之中央位置。 ΟTherefore, for integrated circuit package systems, there is still a need to provide low manufacturing cost, improved yield, improved reliability, and better flexibility to provide more functionality and on printed circuit boards. Less footprint. In view of the ever-increasing demand for cost savings and increased efficiency, the answers to these questions have become increasingly important. The search for answers to these questions has been going on for a while, but the developments have not taught or suggested any answers, so those skilled in the technology have long been eager to answer these questions. [Description of the present invention] The present invention provides an integrated circuit packaging method, comprising: mounting a device structure on a carrier member in a tilting position, the device structure having a pad and a contact pad; the bonding pad and the carrier Connecting an electrical interconnection; forming an anti-flash structure on the device structure, the anti-flash structure is an outer pad; and a package package adjacent to the anti-overflow structure on the carrier Cover. Particular embodiments of the present invention have additional or additional aspects that have been mentioned in the above-mentioned 94511 200933762.. Those skilled in the art will be able to clarify such aspects from the following detailed description when referring to the appended drawings. J Embodiments The following specific embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It will be appreciated that the present invention will be apparent from the disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the invention. In the following description, numerous specific details are set forth to provide a complete understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps have not been disclosed in detail. Similarly, the drawings showing a particular embodiment of the system are illustrated and not to scale, and in particular, some of the dimensions are particularly exaggerated in the drawings for clarity. In general, the invention can operate in any orientation. In addition, various features that are similar or identical to each other are generally described by the same (four) symbol in the various embodiments having certain features in common. For the sake of convenience in the description, the specific embodiments have been described with reference to the first embodiment, the second embodiment, and the like, and are not intended to have any other meaning or limitation. For the purpose of the note, the term "level" (h〇riz〇ntai, defined as parallel to the plane circuit of the surface circuit, is the direction of the tube, (〇rientatlQn). The term "vertical (spectrum ticaD) refers to Perpendicular to: The direction of the water of the righteousness. For example, "above", "below (10) (10) 94511 7 200933762 "bottom", "top (t〇p)", "side" (such as " The terms sidewall (1), "higher", "upper", "over", and "under" are defined corresponding to the horizontal plane. The term " Upper ((8)" direct contact between the fingers. The term "passing" as used herein includes deposition, patterning, exposure, development, side, cleaning, molding, and/or removal of material, or As used herein, the term "system" means the method and apparatus of the present invention in the context of the use of the word. Referring now to Figure 1, the tortoise; The spear does not show the first embodiment of the present invention, the circuit package The top view is the top view of the system. The top view is green: the cover ((10) phase circuit package system 1〇〇. The top view is the touch of the contact 塾1〇4 and the connection 塾(10) Structure 1〇2 (eg substrate) = above the carrier 108 (eg substrate). The side of the device structure 1〇<s(4) 110 is not parallel to the edge 112 of the age (10). The device structure 102 is shown as Located at an offset position above the carrier (10), rather than the central position above the carrier 108. The contact pad 104 is shown in the ring of the flash structure 114 above the peripheral region of the skirting structure 1 () 2, The anti-flash material 114_ such as a non-conductive epoxy resin 1 sealant, a polymer material, a solid-line resin material (such as a lock resin material) or a translucent turn (clear adh S1Ve). _) or the electrical connection 116 of the strip conductor (he (10)_machi e) can be connected between the connection #1〇6 and the carrier (10). The anti-overfill structure 114 covers the connection_device material 1 () 2 The 94511 200933762. The end of the electrical interconnect 116. The first integrated circuit such as an integrated circuit die or a packaged integrated circuit A 118 and a passive device 120, such as a discrete resistor or capacitor, are mounted over the carrier 1 。 8. For illustrative purposes, the first integrated circuit device 118 is shown as the same type of device However, it should be understood that the first integrated circuit device 118 can be different from each other, such as a loose type, function, size or technique. For the purpose of illustration, the passive device 20 is displayed in the same type. Parts, however, it should be understood that the passive devices 120 can be different from one another. For example, passive device 120 can include dissimilar resistors, capacitors, inductors (induct〇r), or a combination thereof. Referring now to Figure 2, there is shown a cross-sectional view of the integrated circuit package system 100 along line 2. The cross-sectional view depicts a second integrated circuit 222, such as an integrated circuit die, mounted on the carrier 108. The spacer 224, such as a film adhesive, can provide a ciear to the electrical interconnect He for connection between the second integrated circuit device 222 and the carrier 108. The device structure 102 is mounted on the second integrated circuit device 222 and the carrier 108. The device structure 1〇2 is shown in an offset position above the carrier 108, rather than the central position above the carrier 1〇8. The anti-flash structure 114, the device structure 102, the spacer 224 and the second integrated circuit device on the peripheral portion of the device structure 102 can be determined by the package covering body (10) on the carrier 108. Height 226. The upset and package wrap 228 is attached to the carrier 1 且 8 and covers the first 94511 9 200933762 integrated circuit device 118, the passive device 120, the second integrated circuit device 222, the 'electrical interconnection 116 and Spacer 224. The package covering body 228 can be adjacent to the anti-overfill structure 114, and the four portions 230 of the contact pads 104 exposing the device structure 1〇2 can provide various work examples. The flashover structure 114 mitigates or eliminates wire sweeps of the electrical interconnects 116 that are connected to the device structure 112 to improve yield and reduce cost. As another example, the anti-flash structure 114 can reduce or eliminate mold flashing on the contact pads 1〇4, thereby improving reliability, increasing yield, and reducing cost. For example, an integrated circuit or a passive component mounting device 232 can be optionally mounted on the integrated circuit package system 100 to form an integrated circuit package. -package system). The mounting device 232 is depicted in dashed lines. The mounting device 232 can be mounted over the device structure 1〇2 and within the recess 230. It should be understood that the first integrated circuit arrangement 118, the second integrated circuit arrangement 222, and the mounting means 232 shown in the specific embodiment are for illustrative purposes. The first integrated circuit device U8, the second integrated circuit device 222, and the mounting device 232 can be a wafer level chip scale package (WLCSP) or a redistributed line (RDL) die. , array package, leadless package, leaded package, system-in-package (SiP), stacked die package 94511 10 200933762 package in cattle package (package_ln_package , pip), embedded die-based (embedded die substrate) or enhanced thermal package, leg package. Referring now to Fig. 3, there is shown a cross-sectional view of an integrated circuit package system 3 of the second embodiment of the present invention, taken as an upper view of Fig. 1. The cross-sectional view depicts the passive device 320 and the first integrated circuit device as the integrated circuit die mounted on the carrier. The second integrated electrical circuit device 322 (such as a packaged integrated circuit) is mounted on the carrier 308 with an adhesive 334 and adjacent to one of the first integrated circuit devices 318 〇 &lt; The second integrated circuit device 322 includes the device structure 3〇2 as its substrate. The second integrated circuit device 322 is shown in an offset position above the carrier 3〇8 and not at a central position above the carrier 308. Electrical interconnect 316 can connect the device structure 302 to the carrier 3〇8. As an example, the second integrated circuit arrangement 322 is shown in inverted ❹ configuration such that the device structure 302 faces away from the carrier 3〇8. The flashover structure 314 is located above the peripheral region of the device structure 3〇2 and over a portion of the electrical interconnect 316 above the device structure 302. The anti-flash structure 314 and the second integrated circuit device 322 can be determined by the package height 326 of the package covering 328 on the carrier 308, and the package covering 328 is attached to the carrier. The first integrated circuit device 318, the passive device 320, the second integrated circuit device 322, and the electrical interconnection 316 are overlaid 308. The package wrap 328 can be adjacent to the anti-overflow 94511 11 200933762 material structure 314 to form a recess 330 that exposes the contact pads 304 of the device structure 302. A mounting circuit 332 such as an integrated circuit or a passive component can be mounted on the integrated circuit package system 300 as needed to form an integrated circuit package system. The mounting device 332 is depicted in dashed lines. The mounting device 332 can be mounted over the device structure 302 and within the recess 330. Referring now to Figure 4, there is shown a top view of integrated circuit package system 400 in a third embodiment of the present invention. The top view is the contact pad 404 of the device structure 402 exposed to the recess 430 formed by the anti-overfill structure 414. The package wrap 428 is adjacent to the anti-flash junction. 414 〇 Referring now to Figure 5, a cross-sectional view of the integrated circuit package system 400 along line 5-5 is shown. The cross-sectional view depicts the passive device 52A and the first integrated circuit device 518 (e.g., integrated circuit die) mounted on the carrier 508. The second integrated circuit device 522 (such as a packaged integrated circuit) is mounted on the third integrated circuit device 536 (such as a flip chip) with an adhesive 534, wherein the third integrated circuit Device 536 is mounted on the carrier 508. The third integrated circuit device 536 can be adjacent to one of the first integrated circuit devices 518. The second integrated circuit device 522 can be overhanged to the one of the first integrated circuit devices 518. The second integrated circuit device 522 includes the device structure 4〇2 as its substrate. The first integrated circuit device 522 is shown in an offset position above the carrier 508, rather than a central location above the carrier 5〇8. Electrical interconnect 516 can connect the device structure 402 to the carrier 508. As an example, the second integrated circuit device 522 is shown in an inverted configuration such that the mounting structure 402 faces away from the carrier 508. The flashover structure 414 is located over a peripheral region of the device structure 4〇2 and over a portion of the electrical interconnect 516 above the device structure 402. The anti-flash structure 414, the second integrated circuit device 522, and the second integrated circuit device 536 can be determined by the package height 526 of the package wrap 428 on the carrier 5〇8. The package cover 428 is attached to the carrier 508 and covers the first integrated circuit device 518, the passive device 520, the second integrated circuit device 522, the third integrated circuit device 536, and the electrical interconnection 516. . The package wrap 428 can be adjacent to the anti-flood structure 414 to form a recess 430 that exposes the contact 塾4〇4 of the device structure 402. For example, an integrated circuit or passive component mounting device 532 can be mounted on the integrated circuit enclosure system shed as needed to form an integrated circuit package system. The mounting device 532 is depicted in dashed lines. The mounting device 532 is worn over the device structure 402 and within the recess 430. Referring now to the sixth embodiment, a side view of the integrated circuit sealer system 6 中 in the fourth embodiment of the present invention is shown. This top view depicts an uncovered integrated circuit package system_. The top view is a device structure 6〇2 (e.g., a substrate) on a carrier 608 (e.g., a substrate), and each of the device structures 602 has a contact pad 604 and a bond pad 606. The sides 610 of each of the device structures 602 are shown as being parallel to the edge 612 of the carrier. Each of the device structures 6〇2 is shown as being located at an offset position above the carrier (10) 8 rather than at a central location above the carrier 6〇8. 94511 13 200933762 _ _ ^ (4) 'The device structure 602 is shown to be identical to each other = It should be understood that the device structure 602 can be in terms of size, shape, configuration of the 塾 604 and the structure of the connection pad 606, etc. In the case of the structure: 6° 2, the contact pads 6〇4 are shown in the ring of the anti-flash structure 614 above the mounting domain. For example, the Ο m2 electrical interconnect 616 can be coupled to the pad and carrier base: St. The anti-flash structure 614 is attached to the end of the electrical interconnect 616 that is coupled to the skirt structure 602. The first-integral circuit of the f ^1 ^ road dies or the integrated circuit of the _ mounted circuit and the passive device 620 such as discrete resistors or capacitors are mounted on the carrier _. For purposes of illustration, the passive device side is shown as the same element. However, it should be understood that the moving device 62 can be an element that is distinct from one another. For example, the passive device 62 can include three different resistors, capacitors, inductors, or a combination thereof. Referring now to Figure 7, there is shown a cross-sectional view of the integrated circuit package system of Figure 7 along line 7-7. The second integrated circuit 722 such as the integrated circuit die is mounted on the carrier_. A spacer 724, such as a film adhesive, can provide a gap to the electrical interconnect (4) for connection between the second integrated circuit device 722 and the carrier member. For purposes of illustration, the second integrated circuit I 722 is shown as the same type of device'. However, it should be understood that the second integrated circuit device 722 can be different from each other, such as different types, functions, and sizes. Or technology. The device structure 602 is mounted on the second integrated circuit package i 722 and the 94511 14 200933762 carrier 608. The device structure 6〇2 is shown in an offset position on the carrier 608, rather than a central position above the carrier 6〇8. The anti-flash structure 614 on the peripheral region of the device structure 602, the device structure 602, the spacer 724 and the second integrated circuit are disposed on the top of the device The wrap height of m is 726. The package cover 728 is attached to the carrier 6〇8 and covers the sixth integrated circuit device 618, the passive device, the second integrated circuit device 722, the electrical interconnection 616, and the spacer 724. The cover wrap 728 t is adjacent to the anti-flood structure 614 to form a recess 730 from each of the device junctions 602 that exposes the contact pads 6〇4. The anti-overfill structure 614 can provide a variety of functions. For example, the anti-overfill structure 614 reduces or eliminates shorting of the wires of the electrical interconnect 616 that is connected to the device structure 〇2, thereby improving yield and reducing cost. As another example, the anti-flood structure 614 can alleviate or eliminate the contact enthalpy of the contact 塾_, thereby improving reliability, increasing yield, and reducing cost. The (four) body circuit or passive component mounting device 732 can be mounted on the frequency package (4) system, and (4) into a circuit stack package system. The mounting device 732 is depicted in dashed lines. The mounting device 7 is mounted on the device structure 6〇2 and in the reading recess 73〇. For the purposes of clarity, the mounting device 732 is shown as the same type of device. It should be understood that the mounting device 732 can be different from one another, such as a phase (four) type, function, size or technique. Referring now to Figure 8, there is shown a fifth embodiment of the present invention. 94511 15 200933762 A top view of the integrated circuit package system 800. This top view is a system 800 of integrated circuit package packages. The top view depicts the device structure 802 (e.g., substrate) of the contact pad 804 and the bond pad 806 over the &amp; 808 (e.g., substrate). The side 81 of the device structure 8〇2 is shown to be non-parallel to the edge 812 of the carrier 8〇8. The device structure 8〇2: is shown in an offset position above the carrier 808, rather than a central location above the carrier 808. Ο

接觸墊804係顯示於裝置結構8〇2之週邊區域上面之 防溢料結構814之環内。如導線或帶狀導線之電性互連816 月t*於連、纟。墊806與承載件808之間連接。該防溢料結構814 係覆蓋連接於該裝置結構8〇2之該電性互連816之末端。 如積體電路晶粒或經封裝的積體電路之第一積體電路 裝置818以及如離散的電阻器或電容器之被動襞置82〇, 係安裝於該承载件_上面。為求制之目的，該第一積 體電路I置818中的某些裝置係顯示成與其餘的裝置不同 而其他的裝置為相同的，然而應理解的是，該第—積體電 ^裝置818的所有裝置驗此相異或彼此相同。亦為求說 月之目的該被動裝置82〇係顯示成相同類型之元件，然 而應^解岐’該被純置82G料彼此相異的元件。舉 ^ 口被動裳置82〇能包含相異的電阻器、電容器、電 感器或上述之結合。 路封梦徠：、、第9圖，其係顯不第8圖沿線9__9之積體電 曰錢8G〇之剖面圖。該剖面圖係描繪如積體電路 積體電路922安裝於該承載件8〇8上面。如膜 94511 16 200933762 膠之間隔件924能提供空隙予電性互連816以於該第二積 .體電路裝置922與該承载件8〇8之間進行連接。 裝置結構802係安裝於該第二積體電路裝置922及該 承載件808上面。钱置結構8〇2係顯示成位於該承載件 808上面之偏移位置，而非該承載件8{)8上面之中央位置。 於該裝置結構802之週邊區域上面之防溢料結構814、該 裂置結構802、該間隔件924及該第二積體電路裝置概 ❹二紅於該承載件808上面之封裝件包覆體娜之包覆體 向度926 〇 封裝件包覆體928係於該承載件_上面且覆蓋第一 積體電路裝置818、被動裝置82()、第二積體電路裝置犯2、 電性互連816及間隔件924。該封裝件包覆體928能相鄰 於該防溢料結構814，而形成外露該裝置結構8〇2之接觸 墊804之凹部930。 防溢料結構814能提供多種功能。舉例而言，該防溢 ❹料結構814係減輕或消除與裝置結㈣〇2連接之電性互連 816之導線短路，從而改善良率並降低成本。如另一範例， 該防溢料結構814能減輕或消除接觸墊8〇4上面之模造溢 料’從而改善可靠度、增進良率以及降低成本。、 #積體電路或被動元件之安裝裝置932能視需要地安 裝於積體電路封裝件系統_上面，而形成積體電路層# 封裝系統。該安裝裝置932係以虛線描繪。該安裝裝置卯2 能安裝於裝置結構802上面且於該凹部93〇内。 現在參照第1G圖，其係顯示本發明之第六具體實施例 94511 17 200933762 中，積體電路封裝件系統1000之上視圖。該上視圖 ，裝置結構1002之接觸墊1004外露於由防溢料結構^田繪 形成之凹部1030中。封裝件包覆體1028係相鄰於4所 料結構1014。 邳鄰於該防溢 現在參知第1 1圖，其係顯示第1 〇圖沿線1卜 Ξ = 封::系統10°°之剖面圖。該剖面圖係描纷被3 及如積體電路晶粒之第一積體電路襞置 ο 於承載件1108上面。如積體電路晶粒之第二積^置 ⑽係以黏膠⑽安裝於件 該第一積體電路裝置⑽。 且月匕相鄰於 r提：膜膠(Wire_in-film adhesive)之間隔件 1124 匕一隙予電性互連ms以於該第二積體 之該電性互連1116之末端亦於該間隔件 〇 該承係安裝於該第二積體電路裝置1122及 之連轉11 ί)β上面。電性互連1116係連接該I置結構1002 载件1108。該連結塾1106係於該裝 區域。該裝置結構1002係顯示成位於 之 面之偏移位置，而非該承載件H08上面 邊區域上面且:於該裝置結構之週 Λ運、'、口墊U06與該接觸墊1004之間。該 連’Ilk结才V〇14並未覆蓋連接至該連結墊1106之電性互 116。該防溢料結構_、該裝置結構1002、該間隔 94511 18 200933762 .件1124及該第二積體電路裝置ιΐ22能決定於該承载件 •謂上面之封裝件包覆體1G28之包覆體高度ιΐ26。 封裝件包覆體1028係於該承載件UG8上面且覆 -積體電路裝置U18、被動裝置⑽、第二積體電路装置 1122、電性互連1116及間·跡韻裝件包覆體議 能相鄰於該防溢料結構1014，而形成外露該裝置結構· 之接觸墊1004之㈣1〇3〇。該防溢料結構1〇14能提供多 ❹種功能。舉例而言，該防溢料結構1〇14能減輕或消除接觸 塾1004上面之模找料，從而改善可靠度、增進良率以及 降低成本。 如積體電路或被動元件之安裝裝置1132能視需要地 安裳於積體電路封裝件系統_上面，而形成積體電路層 疊封裝系統。該安裝《置1132係以虛線猶。該安震裝置 1132能安裝於裝置結構1〇〇2上面且於該凹部刪内。 、現在參照第12圖，_示本發明之第七具體實施例中 以第10 @之上視®為例之積體電路封裝㈣統丨之剖 =圖。該剖面圖係崎被動裝置1220及如積體電路晶粒之 ^ 一積體電路I置1218安裝於承载件腫上面。如經封 j積體電路之第二積體電路裝置1222係以間隔件㈣ :、於如積體f路晶粒之第三積體電路裝置I〗％上面，其 該第一積體電路裝置1236係安裝於該承載件 1208 上 晉=一積體電路裝置1236能相鄰於該第一積體電路褒 1 1218 〇 該第-積體電路1置1222係包含裝置結構 1202作為 94511 19 200933762 f9f板。該第二積體電路裝置體係顯示成位於該承載件 • _上面之偏移位置’而非該承载件刪上面之中央位 置。電性互連1216能連接該裝置結構12〇2之連結塾工寫 與該承载件測。如-範例，該第二積體電路裝置㈣ 係顯不成倒置組構而使裝置結構12〇2背對該承載件12〇8。 如包線膜膠之間隔件1224能提供空隙予電性互連 1216以於該第二碰裝置1222與該第三積體電路装 ❹置1236之間進行連接。連接至該第三積體電路裝置η% 之該電性互連1216之末端亦於該間隔件1224中。 該連結墊1206係於該裝置結構12〇2之週邊區域。防 溢料結構1214能於該裝置結構12〇2之週邊區域上面且於 該連結=1206與該接觸墊1204之間。該防溢料結構i2i4 並未覆盍連接至該連結墊1206之電性互連1216。該防溢 料結構1214、該裝置結構1202、該間隔件1224及二第^ 積體電路裝置1222能決定於該承載件12〇8上面之封裝件 ❹包覆體1228之包覆體高度1226。 封裝件包覆體1228係於該承載件12〇8上面且覆蓋該 第一積體電路裝置1218、該被動裝置1220、該第二積體電 路裝置1222、該電性互連1216、該第三積體電路裝置1236 及該間隔件1224。該封裝件包覆體1228能相鄰於該防溢 料結構1214，而形成外露該裝置結構12〇2之接觸墊12〇4 之凹部1230。該防溢料結構1214能提供多種功能。舉例 而言，該防溢料結構1214能減輕或消除接觸塾1204上面 之模造溢料，從而改善可靠度、增進良率以及降低成本。 94511 20 200933762 Α如積體電路或被動元件之安裝裝置1232能視需要地 安裳於積體電路封裝件系統1200上面，而形成積體電路層 1封裝系統該安裝裝置1232係以虛線描緣。該安裳装置 1232能安裝於裝置結構1202上面且於該凹部1230内。 現在參照第13圖’其係顯示本發明之第人具體實施例 中，積體電路封裝件系統刪之上視圖。該上視圖係描繪 無覆蓋的積體電路封裝件系統_。該上視圖係描緣被動 〇 Ο 裝置1320及如經導線連結之積體電路晶粒之第-積體電 路裝置1318安裝於承载件13〇8上面。為求說明之目的， 積體電路|置1318係顯示成彼此不同尺寸然而應 =解的是，該第-積體電路裝置1318能為相同類型之裝 置。 該上視圖亦描緣具有接觸墊1304及連結墊13〇6之梦 置結構1302(如積體電路晶粒）於承載件」、 二構1_之側__示成平行於該3 件1308之邊緣1312。該裝置位； 載件⑽8上面之—€ 顯不成位於該承 央位置。 偏移位置，而非該承載件13G8上面之中 接觸塾摘係顯示於裝置結構⑽之週邊區域上面 之防溢料結構1314之環内。帶暮 面 ⑶6能於連結墊_與承載 接於該裝置結讀之 ==裝置結構1302溢出至該承載件·。 /照第14圖，其係顯示第13圖沿線14__14之積 94511 21 200933762 Ο 體電路縣件系統麗之剖面圖。該剖面圖係 該承載件刪上面之該裝置結構職^該電性互連文= 係連接於該裝置結構纖與該承載件刪之間。6 結構1302係顯示成位於該承载件13〇8上面之偏移^置 而非該承载件1308上面之中央位置。該防溢料結’ 係於該裝置結構題之週邊區域上面且溢出至柏鄰於該 裝置結構13G2之該承載件13Q8的―部分。該防溢料結^ 1314及該裝置結構1302能決定於該承載件13〇8上面之 裝件包覆體1428之包覆體高度1426。 、 封裝件包覆體1428係於該承載件13〇8上面且覆蓋 一積體電路裝置1318、被動裝置132〇、裝置結構13〇2及 電性互連1316。該聽件包覆體1428能相鄰於該防溢料 結構1314，而形成外露該裝置結構1302之接觸墊13〇4 凹部1430。 之 防溢料結構1314能提供多種功能。舉例而言，該防溢 ©料結構1314係減輕或消除與裝置結構1302連接之電性互 連1316之導線短路，從而改善良率並降低成本。如另一範 例，該防溢料結構1314能減輕或消除接觸墊ι3〇4上面之 模造溢料，從而改善可靠度、增進良率以及降低成本。之 如積體電路或被動元件之安裝裝置1432能視需要地 安裝於積體電路封裝件系統1300上面，而形成積體電路層 _疊封裝系統。該安裝裝置1432係以虛線描繪。該安裴骏^ 1432能安裝於裝置結構13〇2上面且於該凹部143〇^。 現在參照第15圖，其係顯示第2圖之積體電路封裝件 94511 22 200933762 系統100於形成包覆體1502之步驟中之剖面圖。平面模具 • (planar mold chase) 1504能於該防溢料結構114上面。 該平面模具1504亦能於模造停止件（m〇id stop) 1506上 面’例如非導電環氧基樹脂、密封劑、聚合物材料、固線 樹脂材料或可穿透的膜膠所製成之停止件。該模造停止件 1506為視需要的。該防溢料結構114、該模造停止件1506 或上述之結合能緩衝來自平面模具1504之力量而防止對 _ 於裝置結構102之傷害。該防溢料結構114及該模造停止 ❹ 件1506係包含彈回特性（resilient property)而補償因 積體電路封裝件系統100之組裝製程中之傾斜之共面誤差 (coplanarity error) ° 包覆體1502係形成於承載片（carrier strip)1508上 面’覆蓋該第一積體電路裝置118、該被動裝置120、該間 隔件224及該第二積體電路裝置222。該防溢料結構114 係減輕或消除裝置結構102之接觸墊104上面之模造溢 ❹料。該包覆體結構（encapsulated structure)能被切劃 (singulated)形成該積體電路封裝件系統1〇〇。 如另一範例，該平面模具1504能為視需要的。該模造 停止件1506能作用為如欄壩填充（dam-ahd-fill)方法之 模造製程中之攔壩（dam)，此處液態包覆體製程能鋪設於該 承載片1508上面而覆蓋該第一積體電路裝置118、該被動 裝置120、該間隔件224及該第二積體電路裝置222。該防 溢料結構114亦能作用為模造製程中之攔壩而外露該裝置 結構102之接觸墊1〇4。 23 94511 200933762 在此已發現本發明係藉由裝置結構與防溢料結構之偏 ' 移位置而增進良率且降低成本。該偏移位置及角度能有各 種變化以散佈模造化合物流（molding compound flow) ’而 使安裝於承載件上之被動裝置或其他積體電路將不會如因 導線短路而不慎短路，不會抬起裝置而造成連接破損或於 包覆體中產生裂縫。流壓（fl〇Wpressure)之分布亦能容許 局流1、高壓的模造製程而得以增進生產率（throUghpUt)、 ^ 增加生產力（productivity)且增加收益（profitability)。 現在參照第16圖，其係顯示本發明之具體實施例中， 用於製造積體電路封裝件系統之積體電路封裝方法1600 之流程圖。諒方法16〇〇係包含：於方塊16〇2中，將裝置 結構安裝於承載件上面之偏移位置，該裝置結構係具有連 結墊及接觸墊；於方塊1604中，於該連結墊與該承載件之 間連接電性互連；於方塊1606中，於該裝置結構上面形成 防溢料結構’該防溢料結構係外露該接觸墊；以及於方塊 ❹ 1608中，於該承載件上面相鄰於該防溢料結構形成封裝件 包覆體。 — 本發明之又一重要的實施態樣在於本發明有益於支持 且維蔓降低成本、簡〈匕糸統及增加效能之歷史趨勢。 本發明之該些以及其他有益的實施態樣因此而將技術 水平提升到至少下一個等級。 因此，已發現到本發明之積體電路封裝件系統提供了 重要、迄今未知且未曾達到的解決方案、性能及功能態樣， 以用於電路系統之增進良率、增加可靠度及降低成本。所 94511 24 200933762 . 得到的製程及組構係直接的、符合成本效益的、非複雜的、 * 高度多用途的、精確的、靈敏的且有效的，還能夠採取已 知元件而實施，以用於迅速、有效率且經濟的製造、應用 及使用。 本發明雖然已揭露結合特定最佳模式來描述，然而應 理解的是對於熟習該項技藝者而言，根據先前描述的内 容，許多替代方案、修改及變更將變得清楚。因此，本發 明係意於囊括所有落入所包含之申請專利範圍之範疇内之’ ® 此等替代方案、修改及變更。至今於此所提及或顯示於附 圖之所有標的皆為例示說明且無限制之意味。 【圖式簡單說明】 第1圖係本發明之第一具體實施例中，積體電路封裝 件糸統^上視圖， 第2圖係第1圖沿線2—2之積體電路封裝件系統之剖 面圖； ❿ 第3圖係本發明之第二具體實施例中以第1圖之上視 圖為例之積體電路封裝件系統之剖面圖； 第4圖係本發明之第三具體實施例中，積體電路封裝 件系統之上視圖； 第5圖係第4圖沿線5--5之積體電路封裝件系統之剖 面圖； 第6圖係本發明之第四具體實施例中，積體電路封裝 件系統之上視圖； 第7圖係第6圖沿線7—7之積體電路封裝件系統之剖 25 94511 200933762 面圖； * 第8圖係本發明之第五具體實施例中，積體電路封裝 件系統之上視圖， 第9圖係第8圖沿線9—9之積體電路封裝件系統之剖 面圖； 第10圖係本發明之第六具體實施例中，積體電路封裝 件系統之上視圖； 第11圖係第10圖沿線11--11之積體電路封裝件系統 〇 之剖面圖； 第12圖係本發明之第七具體實施例中以第10圖之上 視圖為例之積體電路封裝件系統之剖面圖； 第13圖係本發明之第八具體實施例中，積體電路封裝 件系統之上視圖； 第14圖係第13圖沿線14—14之積體電路封裝件系統 之剖面圖； Q 第15圖係第2圖之積體電路封裝件系統於形成包覆體 之步驟中之剖面圖；以及 第16圖係本發明之具體實施例中，積體電路封裝件系 統之積體電路封裝件製造方法之流程圖。 【主要元件符號說明】 100、300、400、600、800、1000、1200、1300 積體電路 封裝件系統 102、302、402、602、802、1002、1202、1302 裝置結構 104、304、404、604、804、1004、1204、1304 接觸墊 26 94511 200933762 . 106、606、806、1106、1206、1306 連結墊 • 108、308、508、608、808、1108、1208、1308 承載件 110、610、810、1310 侧邊 112、612、812、1312 邊緣 114、314、414、614、814、1014、1214、1314 防溢料結構 116、316、516、616、816、1116、1216、1316 電性互連 118、318、518、618、818、1118、1218、1318 第一積 體電路裝置 〇 120、320、520、620、820、1120、1220、1320 被動裝置 222、322、522、722、922、1122、1222 第二積體電路裝置 224、724、924、1124、1224 間隔件 226、326、526、726、926、1126、1226、1426 包覆體高度 228、328、428、728、928、1028、1228、1428 封裝件 包覆體 230、330、430、730、930、1030、1230、1430 凹部 ❿ 232、332、532、832、932、1132、1232、1432 安裝裝置 334、534、1134 黏膠 536、1236 第三積體電路裝置 1502 包覆體 1504 平面模具 1506 模造停止件 1508 承載片 2--2、5—5、7--7、9--9、11—11、14--14 線 1600 方法 1602、1604、1606、1608 方塊 27 94511Contact pads 804 are shown in the loop of the anti-flash structure 814 above the peripheral region of the device structure 8〇2. For example, the electrical interconnection of wires or ribbon wires is 816 months t*, 连, 纟. Pad 806 is coupled to carrier 808. The anti-flash structure 814 covers the end of the electrical interconnect 816 that is connected to the device structure 8〇2. A first integrated circuit device 818, such as an integrated circuit die or a packaged integrated circuit, and a passive device 82, such as a discrete resistor or capacitor, are mounted on the carrier. For the purpose of the system, some of the devices in the first integrated circuit I 818 are shown to be different from the rest of the devices, while other devices are the same, however, it should be understood that the first integrated device All devices of 818 are different or identical to each other. Also for the purpose of the month, the passive device 82 is shown as the same type of component, but the component that is purely 82G different from each other should be interpreted. It can contain different resistors, capacitors, inductors or a combination of the above. Lufeng Nightmare:,, Figure 9, which is a cross-sectional view of the 8G 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 The cross-sectional view is depicted as an integrated circuit integrated circuit 922 mounted on the carrier 8A. A spacer 924, such as a film 94511 16 200933762, can provide a gap to the electrical interconnect 816 for connection between the second integrated circuit device 922 and the carrier 8A. The device structure 802 is mounted on the second integrated circuit device 922 and the carrier 808. The money setting structure 8〇2 is shown in an offset position above the carrier 808, rather than the central position above the carrier 8{)8. The anti-flash structure 814 on the peripheral region of the device structure 802, the cracking structure 802, the spacer 924 and the second integrated circuit device are generally red on the package wrapper on the carrier 808 The covering body 926 of the cover body 926 is attached to the carrier member _ and covers the first integrated circuit device 818, the passive device 82 (), the second integrated circuit device 2, electrical mutual Connect 816 and spacer 924. The package wrap 928 can be adjacent to the anti-flood structure 814 to form a recess 930 that exposes the contact pads 804 of the device structure 8〇2. The anti-overfill structure 814 can provide a variety of functions. For example, the anti-overfill structure 814 reduces or eliminates shorting of the wires of the electrical interconnect 816 connected to the device junction (4), thereby improving yield and reducing cost. As another example, the anti-flash structure 814 can reduce or eliminate the molded overfill on the contact pads 8〇4 to improve reliability, increase yield, and reduce cost. The #integrated circuit or passive component mounting device 932 can be mounted on the integrated circuit package system _ as needed to form an integrated circuit layer # package system. The mounting device 932 is depicted in dashed lines. The mounting device 卯2 can be mounted on the device structure 802 and within the recess 93〇. Referring now to Figure 1G, there is shown a top view of an integrated circuit package system 1000 in a sixth embodiment of the present invention, 94511 17 200933762. In the top view, the contact pad 1004 of the device structure 1002 is exposed in a recess 1030 formed by the anti-overflow structure. The package wrap 1028 is adjacent to the four material structures 1014. Adjacent to the anti-overflow Now, see Figure 1 1 , which shows a cross-sectional view of the first 〇 diagram along line 1 Ξ = 封:: system 10°°. The cross-sectional view is drawn by 3 and the first integrated circuit such as the integrated circuit die on the carrier 1108. For example, the second integrated circuit (10) of the integrated circuit die is mounted on the first integrated circuit device (10) with an adhesive (10). And the spacer is adjacent to the r: a spacer of the wire_in-film adhesive 1124 is electrically connected to the ms so that the end of the electrical interconnection 1116 of the second integrated body is also at the interval The carrier is mounted on the second integrated circuit device 1122 and the serial 11 )) β. Electrical interconnect 1116 is coupled to I-structure 1002 carrier 1108. The link 塾 1106 is attached to the mounting area. The device structure 1002 is shown offset from the surface, rather than over the upper edge of the carrier H08 and between the device structure, the mouth pad U06 and the contact pad 1004. The 'Ilk junction V〇14 does not cover the electrical mutual 116 connected to the bond pad 1106. The anti-flash structure _, the device structure 1002, the interval 94511 18 200933762, the piece 1124 and the second integrated circuit device ι 22 can be determined by the height of the package of the package covering body 1G28 Ϊ́26. The package covering body 1028 is attached to the carrier UG8 and the overlying integrated circuit device U18, the passive device (10), the second integrated circuit device 1122, the electrical interconnection 1116, and the intervening package assembly It can be adjacent to the anti-flash structure 1014 to form (4) 1〇3〇 of the contact pad 1004 exposing the device structure. The anti-overfill structure 1〇14 can provide a variety of functions. For example, the anti-flash structure 1〇14 can reduce or eliminate the mold lookup on the contact 塾1004, thereby improving reliability, increasing yield, and reducing cost. A mounting device 1132 such as an integrated circuit or a passive component can be mounted on the integrated circuit package system as needed to form an integrated circuit package package system. The installation "Set 1132 is a dotted line. The ampoule device 1132 can be mounted on the device structure 1〇〇2 and deleted in the recess. Referring now to Figure 12, there is shown a cross-sectional view of the integrated circuit package (4) of the seventh embodiment of the present invention. The cross-sectional view of the Osaki passive device 1220 and the integrated circuit die I 1218 are mounted on the carrier. For example, the second integrated circuit device 1222 of the sealed integrated circuit is a spacer (4): the first integrated circuit device is mounted on the third integrated circuit device I. The 1236 is mounted on the carrier 1208. The integrated circuit device 1236 can be adjacent to the first integrated circuit 褒1 1218. The first integrated circuit 1 is disposed 1222. The device structure 1202 is included as a 94511 19 200933762 f9f board. The second integrated circuit device system is shown in an offset position above the carrier _ rather than the central location of the carrier. The electrical interconnect 1216 can be connected to the connector structure of the device structure 12〇2 and written to the carrier. As an example, the second integrated circuit arrangement (4) does not exhibit an inverted configuration such that the device structure 12〇2 faces away from the carrier 12〇8. The spacer 1224 of the epoxy film can provide a gap to the electrical interconnect 1216 for connection between the second touch device 1222 and the third integrated circuit device 1236. The end of the electrical interconnect 1216 connected to the third integrated circuit device η% is also in the spacer 1224. The connection pad 1206 is attached to a peripheral region of the device structure 12〇2. The flashover structure 1214 can be over the peripheral region of the device structure 12〇2 and between the bond=1206 and the contact pad 1204. The anti-overfill structure i2i4 does not cover the electrical interconnect 1216 connected to the bond pad 1206. The anti-overfill structure 1214, the device structure 1202, the spacer 1224 and the second integrated circuit device 1222 can be determined by the package height 1226 of the package ❹ cladding 1228 on the carrier 12〇8. A package covering 1228 is attached to the carrier 12 〇 8 and covers the first integrated circuit device 1218 , the passive device 1220 , the second integrated circuit device 1222 , the electrical interconnection 1216 , and the third The integrated circuit device 1236 and the spacer 1224. The package wrap 1228 can be adjacent to the anti-overfill structure 1214 to form a recess 1230 that exposes the contact pads 12〇4 of the device structure 12〇2. The anti-flood structure 1214 can provide a variety of functions. For example, the anti-flood structure 1214 can reduce or eliminate the molded flash above the contact 1204, thereby improving reliability, increasing yield, and reducing cost. 94511 20 200933762 For example, an integrated circuit or passive component mounting device 1232 can be mounted on the integrated circuit package system 1200 as needed to form an integrated circuit layer. 1 Package System The mounting device 1232 is depicted by a dashed line. The amps 1232 can be mounted over the device structure 1202 and within the recess 1230. Referring now to Figure 13 which shows a first embodiment of the present invention, the integrated circuit package system is shown in a top view. This top view depicts an uncovered integrated circuit package system_. The top view is a passive 〇 装置 device 1320 and a first integrated circuit device 1318 such as a wire-connected integrated circuit die mounted on the carrier 13 〇 8 . For purposes of illustration, the integrated circuits |1318 are shown as being of different sizes from one another. However, it should be understood that the first integrated circuit arrangement 1318 can be the same type of device. The top view also depicts the dream structure 1302 (such as the integrated circuit die) having the contact pad 1304 and the bonding pad 13〇6 on the side of the carrier, the side of the two structures 1_ is parallel to the 3 pieces 1308. The edge 1312. The device position; the top of the carrier (10) 8 is not located at the center of the support. The offset position, rather than the contact pick-up in the upper portion of the carrier 13G8, is shown in the loop of the anti-flash structure 1314 above the peripheral region of the device structure (10). The belt surface (3) 6 can be spilled onto the carrier member with the connection pad _ and the device structure 1302 that is attached to the device. / According to Figure 14, it shows the product of Figure 14 along line 14__14. 94511 21 200933762 Ο Body circuit county system Lizhi section. The cross-sectional view is the structure of the device on which the carrier is removed. The electrical interconnection is connected between the structural fiber of the device and the carrier. The structure 1302 is shown with an offset above the carrier 13〇8 rather than a central location above the carrier 1308. The anti-flash knot is attached to the peripheral region of the device structure and overflows to a portion of the carrier 13Q8 that is adjacent to the device structure 13G2. The anti-flooding junction 1314 and the device structure 1302 can be determined by the cladding height 1426 of the package wrap 1428 above the carrier 13〇8. A package covering 1428 is attached to the carrier 13A and covers an integrated circuit device 1318, a passive device 132, a device structure 13〇2, and an electrical interconnect 1316. The listener wrap 1428 can be adjacent to the anti-flood structure 1314 to form a contact pad 13〇 recess 1430 that exposes the device structure 1302. The anti-flash structure 1314 can provide a variety of functions. For example, the anti-overflow material structure 1314 mitigates or eliminates shorting of the wires of the electrical interconnection 1316 that is coupled to the device structure 1302, thereby improving yield and reducing cost. As another example, the anti-flash structure 1314 can reduce or eliminate the molding flash on the contact pads ι3 〇 4, thereby improving reliability, increasing yield, and reducing cost. A mounting device 1432 such as an integrated circuit or a passive component can be mounted on the integrated circuit package system 1300 as needed to form an integrated circuit layer stacking system. The mounting device 1432 is depicted in dashed lines. The ampoule 1432 can be mounted on the device structure 13〇2 and in the recess 143. Referring now to Fig. 15, there is shown a cross-sectional view of the integrated circuit package of Fig. 2, 94511 22 200933762, in the step of forming the cladding 1502. A planar mold chase 1504 can be placed over the anti-flood structure 114. The planar mold 1504 can also be stopped on the mold stop stop 1506, such as a non-conductive epoxy resin, a sealant, a polymer material, a solid resin material, or a penetrating film glue. Pieces. The mold stop 1506 is as desired. The anti-flood structure 114, the mold stop 1506, or a combination thereof, can cushion the force from the planar mold 1504 to prevent damage to the device structure 102. The anti-flash structure 114 and the mold stop member 1506 include a resilient property to compensate for the coplanarity error of the tilt in the assembly process of the integrated circuit package system 100. The 1502 is formed on the carrier strip 1508 to cover the first integrated circuit device 118, the passive device 120, the spacer 224, and the second integrated circuit device 222. The anti-flood structure 114 mitigates or eliminates overmolding of the overlying contact pads 104 of the device structure 102. The encapsulated structure can be singulated to form the integrated circuit package system. As another example, the planar mold 1504 can be as desired. The molding stop 1506 can function as a dam in a molding process such as a dam-ahd-fill method, where a liquid coating process can be laid over the carrier sheet 1508 to cover the dam. An integrated circuit device 118, the passive device 120, the spacer 224, and the second integrated circuit device 222. The anti-overfill structure 114 can also act as a dam in the molding process to expose the contact pads 1〇4 of the device structure 102. 23 94511 200933762 It has been found herein that the present invention enhances yield and reduces cost by biasing the position of the device structure with the anti-flash structure. The offset position and angle can be varied to disperse the molding compound flow' so that the passive device or other integrated circuit mounted on the carrier will not be inadvertently shorted due to a short circuit of the wire, and will not Lifting the device causes the connection to break or cracks in the cladding. The distribution of flow pressure (fl〇Wpressure) also allows for a flow-through, high-pressure molding process to increase productivity (throUghpUt), increase productivity, and increase profitability. Referring now to Figure 16, there is shown a flow diagram of an integrated circuit package method 1600 for fabricating an integrated circuit package system in accordance with a particular embodiment of the present invention. The method 16 includes: in block 16〇2, mounting the device structure at an offset position on the carrier, the device structure having a connection pad and a contact pad; in block 1604, the connection pad and the An electrical interconnection is connected between the carriers; in block 1606, an anti-flash structure is formed on the structure of the device. The anti-flash structure exposes the contact pad; and in the block 608 1608, on the carrier Adjacent to the anti-flash structure, a package covering body is formed. - Another important embodiment of the present invention is that the present invention is useful for supporting and maintaining the historical trend of cost reduction, simplicity, and efficiency. These and other advantageous embodiments of the invention thus raise the skill level to at least the next level. Accordingly, it has been discovered that the integrated circuit package system of the present invention provides important, hitherto unknown and unachieved solutions, performance and functional aspects for improved yield, increased reliability and reduced cost of the circuit system. 94511 24 200933762 . The resulting process and organization are straightforward, cost-effective, non-complex, * highly versatile, accurate, sensitive and effective, and can be implemented with known components for use Rapid, efficient and economical manufacturing, application and use. The present invention has been described in connection with the specific embodiments thereof, and it is understood that many alternatives, modifications and variations will be apparent to those skilled in the art. Therefore, the present invention is intended to cover all such alternatives, modifications and variations as fall within the scope of the appended claims. All of the subject matter referred to herein or shown in the drawings is illustrative and not limiting. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top view of an integrated circuit package according to a first embodiment of the present invention, and FIG. 2 is a first embodiment of a circuit package system along line 2-2 of FIG. FIG. 3 is a cross-sectional view showing an integrated circuit package system of the second embodiment of the present invention taken as an upper view of FIG. 1; FIG. 4 is a third embodiment of the present invention. FIG. 5 is a cross-sectional view of the integrated circuit package system of FIG. 4 along line 5-5; FIG. 6 is a fourth embodiment of the present invention, the integrated body FIG. 7 is a cross-sectional view of the integrated circuit package system along line 7-7 of FIG. 6; FIG. 8 is a plan view of the fifth embodiment of the present invention; FIG. 9 is a cross-sectional view of the integrated circuit package system of FIG. 8 along line 9-9; FIG. 10 is a sixth embodiment of the present invention, the integrated circuit package Above view of the system; Figure 11 is the integrated circuit package system of line 11-11 in Figure 10. FIG. 12 is a cross-sectional view showing an integrated circuit package system of the seventh embodiment of the present invention taken as an upper view of FIG. 10; and FIG. 13 is an eighth embodiment of the present invention. Figure 14 is a top view of the integrated circuit package system of Figure 14 along line 14-14; Q Figure 15 is the formation of the integrated circuit package system of Figure 2 A cross-sectional view of a step of covering a body; and a 16th drawing is a flow chart of a method of manufacturing an integrated circuit package of an integrated circuit package system in a specific embodiment of the present invention. [Main component symbol description] 100, 300, 400, 600, 800, 1000, 1200, 1300 integrated circuit package system 102, 302, 402, 602, 802, 1002, 1202, 1302 device structure 104, 304, 404, 604, 804, 1004, 1204, 1304 contact pads 26 94511 200933762 . 106, 606, 806, 1106, 1206, 1306 connection pads • 108, 308, 508, 608, 808, 1108, 1208, 1308 carriers 110, 610, 810, 1310 side 112, 612, 812, 1312 edge 114, 314, 414, 614, 814, 1014, 1214, 1314 anti-flash structure 116, 316, 516, 616, 816, 1116, 1216, 1316 Connected 118, 318, 518, 618, 818, 1118, 1218, 1318 first integrated circuit devices 〇 120, 320, 520, 620, 820, 1120, 1220, 1320 passive devices 222, 322, 522, 722, 922, 1122, 1222 second integrated circuit device 224, 724, 924, 1124, 1224 spacers 226, 326, 526, 726, 926, 1126, 1226, 1426 cladding heights 228, 328, 428, 728, 928, 1028 , 1228, 1428 package coverings 230, 330, 430, 730, 930, 1030, 1230, 1430 recesses 232, 332 532, 832, 932, 1132, 1232, 1432 mounting device 334, 534, 1134 adhesive 536, 1236 third integrated circuit device 1502 covering body 1504 plane mold 1506 molding stop 1508 carrier sheet 2-2, 5 - 5, 7--7, 9--9, 11-11, 14--14 Line 1600 Method 1602, 1604, 1606, 1608 Block 27 94511

Claims (1)

200933762 七、申請專利範圍·· , 1. 一種積體電路封裝方法，包括： 於承載件上方的偏移位置安裝裝置結構，該裝置結 構具有連結墊和接觸墊； 於該連結墊與該承載件之間連接電性互連； 於該裝置結構上方形成防溢料結構，該防溢料結構 係外露該接觸墊；以及 於該承載件上方相鄰於該防溢料結構形成封裝件 〇 包覆體。 2. 如申請專利範圍第1項之方法，其中，安裝該裝置結構 包含安裝插入件。 3. 如申請專利範圍第1項之方法，其中，安裝該裝置結構 包含安裝積體電路裝置。 4. 如申請專利範圍第1項之方法，其中，於該裝置結構上 方形成該防溢料結構包含於該連結墊上方的該電性互 _ 連的一部分上方形成該防溢料結構。 5. 如申請專利範圍第1項之方法，復包括於該承載件上方 安裝第一積體電路。 6. —種積體電路封裝件系統，包括： 承載件； 裝置結構，係於該承載件上方的偏移位置，該裝置 結構具有連結墊和接觸墊； 電性互連，係於該連結墊與該承載件之間； 防溢料結構’係於該裝置結構上方’該防溢料結構 28 94511 200933762 係外露該接觸墊；以及 封裝件包覆體，係於該承載件上方相鄰於該防溢料 結構。 7. 如申請專利範圍第6項之系統，其中，該裝置結構係插 入件。 8. 如申請專利範圍第6項之系統，其中，該裝置結構係積 體電路裝置。 9. 如申請專利範圍第6項之系統，其中，於該裝置結構上 方的該防溢料結構包含於該連結墊上方的該電性互連 的一部分上方的該防溢料結構。 10. 如申請專利範圍第6項之系統，復包括於該承載件上方 的第一積體電路裝置。 29 94511200933762 VII. Patent application scope ·· 1. An integrated circuit packaging method, comprising: installing a device structure at an offset position above a carrier, the device structure having a connection pad and a contact pad; and the connection pad and the carrier Connecting an electrical interconnection; forming an anti-flash structure above the device structure, the anti-flash structure exposing the contact pad; and forming a package adjacent to the anti-overfill structure over the carrier body. 2. The method of claim 1, wherein the mounting the device comprises mounting inserts. 3. The method of claim 1, wherein installing the device structure comprises installing an integrated circuit device. 4. The method of claim 1, wherein the anti-flash structure is formed over the structure of the device to form the anti-flash structure over a portion of the electrical interconnect above the connection pad. 5. The method of claim 1, wherein the first integrated circuit is mounted above the carrier. 6. An integrated circuit package system comprising: a carrier; a device structure at an offset position above the carrier, the device structure having a connection pad and a contact pad; and an electrical interconnection to the connection pad Between the carrier and the carrier; the anti-flash structure is above the device structure. The anti-flash structure 28 94511 200933762 exposes the contact pad; and the package covering body is adjacent to the carrier Anti-flash structure. 7. The system of claim 6, wherein the device structure is an insert. 8. The system of claim 6, wherein the device structure is an integrated circuit device. 9. The system of claim 6 wherein the anti-flash structure above the structure of the device comprises the anti-flash structure above a portion of the electrical interconnect above the bond pad. 10. The system of claim 6, wherein the first integrated circuit device is included above the carrier. 29 94511
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI662635B (en) * 2017-07-10 2019-06-11 力成科技股份有限公司 Package structure and manufacturing method thereof

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7049691B2 (en) * 2002-10-08 2006-05-23 Chippac, Inc. Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package
US8084849B2 (en) * 2007-12-12 2011-12-27 Stats Chippac Ltd. Integrated circuit package system with offset stacking
US7985628B2 (en) * 2007-12-12 2011-07-26 Stats Chippac Ltd. Integrated circuit package system with interconnect lock
US8536692B2 (en) * 2007-12-12 2013-09-17 Stats Chippac Ltd. Mountable integrated circuit package system with mountable integrated circuit die
US20090243069A1 (en) * 2008-03-26 2009-10-01 Zigmund Ramirez Camacho Integrated circuit package system with redistribution
US9293385B2 (en) * 2008-07-30 2016-03-22 Stats Chippac Ltd. RDL patterning with package on package system
US8987830B2 (en) 2010-01-12 2015-03-24 Marvell World Trade Ltd. Attaching passive components to a semiconductor package
US8680684B2 (en) * 2012-01-09 2014-03-25 Invensas Corporation Stackable microelectronic package structures
CN103632988B (en) * 2012-08-28 2016-10-19 宏启胜精密电子(秦皇岛)有限公司 Package-on-package structure and preparation method thereof
JP2014138035A (en) * 2013-01-15 2014-07-28 Toshiba Corp Semiconductor device
KR20140109134A (en) * 2013-03-05 2014-09-15 삼성전자주식회사 Semiconductor package having multi-channel and related electronic system
US10020236B2 (en) * 2014-03-14 2018-07-10 Taiwan Semiconductar Manufacturing Campany Dam for three-dimensional integrated circuit
US10490528B2 (en) * 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
JP6636377B2 (en) * 2016-04-08 2020-01-29 株式会社ディスコ Package wafer manufacturing method and device chip manufacturing method
US11443997B2 (en) * 2020-07-20 2022-09-13 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same

Family Cites Families (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5060234A (en) * 1984-11-19 1991-10-22 Max-Planck Gesellschaft Zur Forderung Der Wissenschaften Injection laser with at least one pair of monoatomic layers of doping atoms
US5333505A (en) * 1992-01-13 1994-08-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor pressure sensor for use at high temperature and pressure and method of manufacturing same
FR2694840B1 (en) * 1992-08-13 1994-09-09 Commissariat Energie Atomique Three-dimensional multi-chip module.
US6727579B1 (en) * 1994-11-16 2004-04-27 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US5866953A (en) * 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
US6117705A (en) * 1997-04-18 2000-09-12 Amkor Technology, Inc. Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate
US5950070A (en) 1997-05-15 1999-09-07 Kulicke & Soffa Investments Method of forming a chip scale package, and a tool used in forming the chip scale package
JP2000208698A (en) * 1999-01-18 2000-07-28 Toshiba Corp Semiconductor device
US6351028B1 (en) * 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
US6043109A (en) * 1999-02-09 2000-03-28 United Microelectronics Corp. Method of fabricating wafer-level package
US6291884B1 (en) 1999-11-09 2001-09-18 Amkor Technology, Inc. Chip-size semiconductor packages
JP2001141411A (en) 1999-11-12 2001-05-25 Sony Corp Semiconductor device for fingerprint recognition
JP2001203318A (en) * 1999-12-17 2001-07-27 Texas Instr Inc <Ti> Semiconductor assembly with multiple flip chips
US7026710B2 (en) 2000-01-21 2006-04-11 Texas Instruments Incorporated Molded package for micromechanical devices and method of fabrication
US6401545B1 (en) * 2000-01-25 2002-06-11 Motorola, Inc. Micro electro-mechanical system sensor with selective encapsulation and method therefor
US6492726B1 (en) * 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
KR100411811B1 (en) 2001-04-02 2003-12-24 앰코 테크놀로지 코리아 주식회사 Semiconductor package
US6653723B2 (en) 2002-03-09 2003-11-25 Fujitsu Limited System for providing an open-cavity low profile encapsulated semiconductor package
JP3679786B2 (en) 2002-06-25 2005-08-03 松下電器産業株式会社 Manufacturing method of semiconductor device
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
US6861288B2 (en) * 2003-01-23 2005-03-01 St Assembly Test Services, Ltd. Stacked semiconductor packages and method for the fabrication thereof
US6987058B2 (en) * 2003-03-18 2006-01-17 Micron Technology, Inc. Methods for underfilling and encapsulating semiconductor device assemblies with a single dielectric material
TWI311353B (en) 2003-04-18 2009-06-21 Advanced Semiconductor Eng Stacked chip package structure
KR100604821B1 (en) 2003-06-30 2006-07-26 삼성전자주식회사 Stacked ball grid array package and its manufacturing method
KR100574947B1 (en) 2003-08-20 2006-05-02 삼성전자주식회사 BA package, manufacturing method thereof and BA package laminated structure
KR100546374B1 (en) 2003-08-28 2006-01-26 삼성전자주식회사 Multilayer semiconductor package having a center pad and its manufacturing method
US7045888B2 (en) * 2004-06-29 2006-05-16 Macronix International Co., Ltd. Ultra thin dual chip image sensor package structure and method for fabrication
JP4443334B2 (en) * 2004-07-16 2010-03-31 Ｔｏｗａ株式会社 Resin sealing molding method of semiconductor element
US7276393B2 (en) * 2004-08-26 2007-10-02 Micron Technology, Inc. Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US8324725B2 (en) * 2004-09-27 2012-12-04 Formfactor, Inc. Stacked die module
TWI251886B (en) * 2004-11-03 2006-03-21 Advanced Semiconductor Eng Sensor chip for defining molding exposed region and method for manufacturing the same
JP2006278726A (en) 2005-03-29 2006-10-12 Sharp Corp Semiconductor device module and manufacturing method of semiconductor device module
US7364945B2 (en) * 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US7354800B2 (en) * 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
US7518224B2 (en) * 2005-05-16 2009-04-14 Stats Chippac Ltd. Offset integrated circuit package-on-package stacking system
US7746656B2 (en) * 2005-05-16 2010-06-29 Stats Chippac Ltd. Offset integrated circuit package-on-package stacking system
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
TWI292617B (en) * 2006-02-03 2008-01-11 Siliconware Precision Industries Co Ltd Stacked semiconductor structure and fabrication method thereof
US8704349B2 (en) * 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US7288835B2 (en) * 2006-03-17 2007-10-30 Stats Chippac Ltd. Integrated circuit package-in-package system
US7501697B2 (en) * 2006-03-17 2009-03-10 Stats Chippac Ltd. Integrated circuit package system
TWI309079B (en) 2006-04-21 2009-04-21 Advanced Semiconductor Eng Stackable semiconductor package
TWI298198B (en) 2006-05-30 2008-06-21 Advanced Semiconductor Eng Stackable semiconductor package
TWI339436B (en) * 2006-05-30 2011-03-21 Advanced Semiconductor Eng Stackable semiconductor package
US7468556B2 (en) 2006-06-19 2008-12-23 Lv Sensors, Inc. Packaging of hybrid integrated circuits
US7535086B2 (en) * 2006-08-03 2009-05-19 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
US8198735B2 (en) * 2006-12-31 2012-06-12 Stats Chippac Ltd. Integrated circuit package with molded cavity
US7915724B2 (en) * 2007-09-28 2011-03-29 Stats Chippac Ltd. Integrated circuit packaging system with base structure device
US8084849B2 (en) * 2007-12-12 2011-12-27 Stats Chippac Ltd. Integrated circuit package system with offset stacking
US7985628B2 (en) * 2007-12-12 2011-07-26 Stats Chippac Ltd. Integrated circuit package system with interconnect lock
US8536692B2 (en) * 2007-12-12 2013-09-17 Stats Chippac Ltd. Mountable integrated circuit package system with mountable integrated circuit die
US7683469B2 (en) 2008-05-30 2010-03-23 Stats Chippac Ltd. Package-on-package system with heat spreader

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI662635B (en) * 2017-07-10 2019-06-11 力成科技股份有限公司 Package structure and manufacturing method thereof

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