200937166 九、發明說明： 【發明所屬之技術領域】 本發明屬於-種電路’且特別是一種電流源電路。 【先前技術】 隨著科技的發展，記憶體已廣泛地運用在各種電子裝 置。特別是快閃記憶體不需電力來維持數據的儲存，而且 快閃記憶體占用很少的讀取時間並具有很高的抗震能力。 所以快閃記憶體經常用在電池供電的電子裝置，例如手機 〇 和個人數位助理（PDA)。 然而，於快閃記憶體中，多個快閃記憶體單元在進行 寫入（programming)時，由於快閃記憶體單元的臨界電壓隨 寫入電子的增加而改變，造成快閃記憶體單元所需的寫入 電流增加’亦即所需的熱電子（h〇t electron)增加，因此 加大了功耗。一旦超出外接電路所能供應的電流量，即會 造成快閃記憶體單元的寫入失敗。 基於上述原因’需要一種新的電流控制裝置，用以穩 φ 定地控制上述之寫入電流。 【發明内容】 本發明的目的就是提供一種電流控制裝置，可用以穩 定地控制上述之寫入電流。 依照本發明一實施例，一種電流控制裝置，至少包含 一偏壓電路與一壓控電流源。此偏壓電路，用以提供一偏 Μ。以及’此壓控電流源，電性連接此偏壓電路，用以根 5 200937166 據此偏壓來控制寫入電流，其中此寫入電流係由外接電路 (如電荷泵）注入於一快閃記憶體中的至少一記憶單元。 以下將以一實施例對上述之說明以及接下來的實施方 式做詳細的描述，並對本發明提供更進一步的解釋。 【實施方式】 為了使本發明之敘述更加詳盡與完備，可參照下列之 圖示及各種實施例’圖示中相同之號碼代表相同之元件。 © 另一方面，眾所週知的電路元件並未描述於實施例中，以 避免造成本發明不必要的限制。 請參照第1圖’其係繪示依照本發明一實施例的一種 控制電流的裝置100的功能方塊圖《第1圖中，此控制電 流的裝置100可包含一壓控電流源110與一偏壓電路12〇。 此壓控電流源110配置於一外接電路15〇(如電荷泵）與至 少一快閃記憶體單元165之間，且此壓控電流源11 〇電性 連接此偏壓電路120。其中’此偏壓電路120用以提供一偏 Ο 壓，此壓控電流源110用以根據此偏壓來控制一寫入電流， 其中此寫入電流係由此外接電路150經由此壓控電流源 110，並透過此位元線160注入於至少一快閃記憶體單元 165 〇 請參照第2圖，其係繪示依照本發明一實施例的一種 壓控電流源110的電路囷。第2圖中，此壓控電流源 可以包含金屬氧半導髏，像是Ν通道金屬氧半導體（nm〇s) 或者是Ρ通道金屬氧半導體（PM0S)，在此以ρ通道金屬氧 200937166 半導體為例’其中此p通道金屬氧半導體的閘極電性連接 此偏麗電路120,此P通道金屬氧半導體的源極電性連接此 外接電路150’此p通道金屬氧半導體的汲極透過此位元線 160電性連接至少一快閃記憶體單元165。當偏壓電路 提供一適當的偏壓至此p通道金屬氧半導體的閘極，使此p 通道金屬氧半導體導通，則上述之寫入電流可透過此位元 線160注入於至少一快閃記憶體單元165。應瞭解到，以上 僅為例不，並非用以限定本發明，任何熟習此技藝者，在 不脫離本發明之精神和範圍内，當可視實際應用，彈性選 D 擇此壓控電流源110所採用的半導體元件，像是雙載子電 晶體（BJT)或其他相似元件。 值得注意的是，本發明所提供之一種電流控制裝置 1〇〇,可廣泛地運用於各種快閃記憶體單元165。舉例來說， 快閃 β己憶體單元 165 可為 2T(two transistors) PMOS cel 1， 2T NMOS cell, IT PMOS cell, IT NMOS cell 或相似的記 憶體單元。 為了使本發明之敘述更加詳盡與完備，請參照第3圖， Ο 係繪示依照本發明一實施例的一種控制電流的裝查1〇〇的 電路圖。第3圖中，壓控電流源110可為一 P通道金屬氧 半導體（PMOS)310，亦可採用N通道金屬氧半導體（NMOS)， 此處以PMOS為例，其中此P通道金屬氧半導體310的閘極 電性連接一偏壓電路120,此P通道金屬氧半導體310的源 極電性連接此外接電路150,此P通道金屬氧半導體310 的汲極透過此位元線160電性連接至少一快閃記憶體單元 165。此外，於本實施例，外接電路150可提供電壓至此偏 7 200937166 壓電路120’所以，於第3圖中，此偏壓電路12〇電性連接 此外接電路150。其中，此偏壓電路12〇包含一第一分壓器 181、一第二分壓器182、一第一 N通道金屬氧半導體183、 一第一 N通道金屬氧半導體184、一控制信號產生器185 以及一反相器186。其中，此第一分壓器串聯此外接電路 150。此第二分壓器182串聯此第一分壓器，其中此第一分 壓器181與此第二分壓器182共同連接於一節點19〇上， 並透過此節點190電性連接至p通道金屬氧半導體31〇的 閘極。此第一 N通道金屬氧半導體183串聯此第二分壓器 〇 182,其中此第一 N通道金屬氧半導體183的汲極電性連接 此第二分壓器182,且此第一 N通道金屬氧半導體183的源 極接地。另外，此第二N通道金屬氧半導體184的汲極電 性連接此P通道金屬氧半導體31〇的閘極，且此第二N通 道金屬氧半導體184的源極接地❶再者，此控制信號產生 器185電性連接此第N通道金屬氧半導艎183的閘極、 此反相器186的輸入端電性連接此控制信號產生器185，且 此反相器186的輸出端電性連接此第二1^通道金屬氧半導 ❹ 趙184的閘極 於一實施例，上述之第一分壓器181可至少包含一電 阻；或者，上述之第-分壓器181可至少包含一種可作為 等效電阻的電子元件，像是半導體元件。另一方面，上述 之第二分壓器182可至少包含一電阻；或者，上述之第二 分愿器182可至少包含-種可作為等效電阻的電子元件， 像是半導體元件。 值得注意的是，若上述之至少一快閃記憶體單元165 200937166 於寫入（programming)時’控制信號產生器ι85用以產生一 第一電壓’且此反相器186用以接收此第一電壓後輸出一 邏輯低電壓，其中，第一電壓係為一邏輯高電壓，第二電 壓係為一邏輯低電壓。應暸解到，於反相器186中，可具 有至少一半導體元件，像是N通道金屬氧半導體與（或)p 通道金屬氧半導體，其中，此邏輯高電壓應大於N通道金 屬氧半導體的臨界電壓，且此邏輯高電壓與電源電壓的差 值應小於此P通道金屬氧半導體的臨界電壓，藉此，反相 器186可輸出邏輯高電壓。所以，第二n通道金屬氧半導 © 體184關閉，且此第一 N通道金屬氧半導體ί83導通並由 此節點190輸出一偏壓至此ρ通道金屬氧半導體31〇的閘 極，使此Ρ通道金屬氧半導體31〇導通，藉此，上述之寫 入電流可注入於至少一快閃記憶體單元165，達到對此快閃 記憶趙單元165寫入的目的。 另一方面，若上述電路處於抹除、讀取或待命（standby) 狀態時，控制信號產生器185用以產生一第一電壓，且此 反相器186用以接收此第一電麼後輸出一邏輯低電壓，其 ❹ 巾’第-電壓係為-邏輯低電壓，第二電壓係為一邏輯高 電壓。應瞭解到，於反相器186中，可具有至少一半導鳢 兀件，像是N通道金屬氧半導體與（或）p通道金屬氧半導 體’其中’此邏輯低電壓應小於此N通道金屬氧半導體的 臨界電壓，且此邏輯高電壓與電源電壓的差值應大於此p 通道金屬氧半導體的臨界電壓’藉此，反相器i86可輸出 邏輯低電壓。所以，此第—N通道金屬氧半導體183關閉， 且此第二N通道金屬氧半導體184導通。應瞭解到，於實 200937166 際應用上’因第二N通道金屬氧半導體184導通而造成的 電麼降很小，所以可視為此P通道金屬氧半導體310的閘 極接地’藉此，使此p通道金屬氧半導體31〇關閉。 雖然本發明已以一實施例揭露如上，然其並非用以限 定本發明’任何熟習此技藝者，在不脫離本發明之精神和 範圍内’當可作各種之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之詳細說明如下： 第1圖係綠示依照本發明一實施例的一種控制電流的 裝置的功能方塊圖。 第2圖係綠示依照本發明一實施例的一種壓控電流源 的電路囷。 第3囷係繪示依照本發明一實施例的一種控制電流的 裝置的電路圖。 【主要元件符號說明】 :電流控制裝置 12〇:偏壓電路 160 :位元線 181 :第一分壓器 110 :麼控電流源 150 :外接電路 165 :快閃記憶體單元 182 :第二分壓器 200937166 183:第一 N通道金屬氧半導184:第二N通道金屬氧半導 體 體 185:控制信號產生器 186:反相器 190:節點 310:P通道金屬氧半導體 ❹ ❹ 11200937166 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention pertains to a circuit and particularly a current source circuit. [Prior Art] With the development of technology, memory has been widely used in various electronic devices. In particular, flash memory does not require power to maintain data storage, and flash memory takes up very little read time and is highly shock resistant. Therefore, flash memory is often used in battery-powered electronic devices such as cell phones and personal digital assistants (PDAs). However, in flash memory, when a plurality of flash memory cells are programmed, the threshold voltage of the flash memory cell changes as the write electrons increase, resulting in a flash memory cell unit. The required write current increase', that is, the required amount of hot electrons (h〇t electron) increases, thus increasing power consumption. Once the amount of current that can be supplied by the external circuit is exceeded, the write failure of the flash memory unit is caused. For the above reasons, a new current control device is required to stably control the above-described write current. SUMMARY OF THE INVENTION An object of the present invention is to provide a current control device for stably controlling the above-described write current. In accordance with an embodiment of the invention, a current control device includes at least a biasing circuit and a voltage controlled current source. The bias circuit is configured to provide a bias. And the voltage control current source is electrically connected to the bias circuit for controlling the write current according to the bias voltage of the root 5 200937166, wherein the write current is injected into the fast circuit by an external circuit (such as a charge pump) At least one memory unit in the flash memory. The above description and the following embodiments will be described in detail with reference to an embodiment, and further explanation of the invention. [Embodiment] In order to make the description of the present invention more complete and complete, the same reference numerals are used to refer to the same elements in the drawings. On the other hand, well-known circuit components are not described in the embodiments to avoid unnecessarily limiting the invention. Please refer to FIG. 1 , which is a functional block diagram of a device 100 for controlling current according to an embodiment of the invention. In FIG. 1 , the device 100 for controlling current may include a voltage-controlled current source 110 and a bias. The voltage circuit 12 is turned on. The voltage-controlled current source 110 is disposed between an external circuit 15 (such as a charge pump) and at least one flash memory unit 165, and the voltage-controlled current source 11 is electrically connected to the bias circuit 120. Wherein the bias circuit 120 is configured to provide a bias voltage, and the voltage controlled current source 110 is configured to control a write current according to the bias voltage, wherein the write current is thereby controlled by the external circuit 150 via the voltage control The current source 110 is injected into the at least one flash memory unit 165 through the bit line 160. Referring to FIG. 2, a circuit diagram of a voltage controlled current source 110 in accordance with an embodiment of the present invention is illustrated. In Fig. 2, the voltage-controlled current source may comprise a metal oxygen semiconductor, such as a germanium channel metal oxide semiconductor (nm〇s) or a germanium channel metal oxide semiconductor (PM0S), where the p-channel metal oxygen 200937166 semiconductor For example, the gate of the p-channel metal oxide semiconductor is electrically connected to the bias circuit 120, and the source of the P-channel metal oxide semiconductor is electrically connected to the circuit 150. The drain of the p-channel metal oxide semiconductor passes through The bit line 160 is electrically connected to at least one flash memory unit 165. When the bias circuit supplies an appropriate bias voltage to the gate of the p-channel metal oxy-semiconductor to turn on the p-channel metal oxy-semiconductor, the write current can be injected into the at least one flash memory through the bit line 160. Body unit 165. It should be understood that the above is only an example and is not intended to limit the present invention. Any one skilled in the art can flexibly select the voltage control current source 110 according to the actual application without departing from the spirit and scope of the present invention. A semiconductor component is used, such as a bipolar transistor (BJT) or other similar component. It should be noted that the present invention provides a current control device that can be widely applied to various flash memory cells 165. For example, the flash beta memory cell 165 can be a 2T (two transistors) PMOS cel 1, 2T NMOS cell, an IT PMOS cell, an IT NMOS cell, or a similar memory cell. In order to make the description of the present invention more detailed and complete, please refer to FIG. 3, which is a circuit diagram of a control circuit for controlling current according to an embodiment of the present invention. In FIG. 3, the voltage-controlled current source 110 can be a P-channel metal oxide semiconductor (PMOS) 310 or an N-channel metal oxide semiconductor (NMOS). Here, a PMOS is taken as an example, wherein the P-channel metal-oxygen semiconductor 310 The gate is electrically connected to a bias circuit 120. The source of the P-channel metal-oxygen semiconductor 310 is electrically connected to the circuit 150. The drain of the P-channel metal-oxygen semiconductor 310 is electrically connected through the bit line 160. A flash memory unit 165. In addition, in the present embodiment, the external circuit 150 can supply a voltage to the bias voltage circuit 120'. Therefore, in the third embodiment, the bias circuit 12 is electrically connected to the circuit 150. The bias circuit 12 includes a first voltage divider 181, a second voltage divider 182, a first N-channel metal oxide semiconductor 183, a first N-channel metal oxide semiconductor 184, and a control signal generated. The device 185 and an inverter 186. Wherein, the first voltage divider is connected in series with the circuit 150. The second voltage divider 182 is connected in series with the first voltage divider, wherein the first voltage divider 181 and the second voltage divider 182 are connected in common to a node 19, and are electrically connected to the node 190 through the node 190. The gate of the channel metal oxy-semiconductor 31 。. The first N-channel metal oxide semiconductor 183 is connected in series with the second voltage divider 182, wherein the first N-channel metal oxide semiconductor 183 is electrically connected to the second voltage divider 182, and the first N-channel metal The source of the oxygen semiconductor 183 is grounded. In addition, the drain of the second N-channel metal oxide semiconductor 184 is electrically connected to the gate of the P-channel metal oxide semiconductor 31, and the source of the second N-channel metal oxide semiconductor 184 is grounded. The generator 185 is electrically connected to the gate of the Nth metal MOS transistor 183. The input end of the inverter 186 is electrically connected to the control signal generator 185, and the output of the inverter 186 is electrically connected. The first voltage divider 181 may include at least one resistor; or the first voltage divider 181 may include at least one type of resistor. An electronic component that is an equivalent resistor is like a semiconductor component. Alternatively, the second voltage divider 182 may include at least one resistor; or the second repeater 182 may include at least an electronic component such as a semiconductor component that can function as an equivalent resistor. It should be noted that if the at least one flash memory unit 165 200937166 is programmed, the control signal generator ι85 is used to generate a first voltage and the inverter 186 is used to receive the first After the voltage, a logic low voltage is output, wherein the first voltage is a logic high voltage and the second voltage is a logic low voltage. It should be understood that in the inverter 186, there may be at least one semiconductor component, such as an N-channel metal oxide semiconductor and/or a p-channel metal oxide semiconductor, wherein the logic high voltage should be greater than the criticality of the N-channel metal oxide semiconductor. The voltage, and the difference between the logic high voltage and the power supply voltage should be less than the threshold voltage of the P-channel metal-oxygen semiconductor, whereby the inverter 186 can output a logic high voltage. Therefore, the second n-channel metal oxy-oxide semiconductor 184 is turned off, and the first N-channel metal oxide semiconductor ί83 is turned on and the node 190 outputs a bias voltage to the gate of the ρ-channel metal oxy-semiconductor 31 ,, so that the Ρ The channel metal oxy-oxide 31 is turned on, whereby the write current can be injected into the at least one flash memory unit 165 to achieve the purpose of writing the flash memory unit 165. On the other hand, if the circuit is in the erase, read or standby state, the control signal generator 185 is configured to generate a first voltage, and the inverter 186 is configured to receive the first power and then output. A logic low voltage, the wiper 'the first voltage is - logic low voltage, and the second voltage is a logic high voltage. It should be understood that in the inverter 186, there may be at least half of the lead members, such as an N-channel metal oxy-semiconductor and/or a p-channel metal oxy-semiconductor, where 'the logic low voltage should be less than the N-channel metal oxygen. The threshold voltage of the semiconductor, and the difference between the logic high voltage and the power supply voltage should be greater than the threshold voltage of the p-channel metal-oxygen semiconductor', whereby the inverter i86 can output a logic low voltage. Therefore, the first N-channel metal oxide semiconductor 183 is turned off, and the second N-channel metal oxide semiconductor 184 is turned on. It should be understood that, in the actual application of 200937166, 'the electrical drop caused by the conduction of the second N-channel metal oxy-semiconductor 184 is small, so it can be seen that the gate of the P-channel metal-oxygen semiconductor 310 is grounded', thereby making this The p-channel metal oxy-semiconductor 31 is turned off. Although the present invention has been disclosed in an embodiment of the present invention, it is not intended to limit the invention to those skilled in the art, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; A functional block diagram of a device for controlling current. Figure 2 is a circuit diagram of a voltage controlled current source in accordance with an embodiment of the present invention. Figure 3 is a circuit diagram of a device for controlling current in accordance with an embodiment of the present invention. [Main component symbol description]: Current control device 12: Bias circuit 160: Bit line 181: First voltage divider 110: Control current source 150: External circuit 165: Flash memory unit 182: Second Voltage divider 200937166 183: first N-channel metal oxygen semiconductor 184: second N-channel metal oxy-oxide body 185: control signal generator 186: inverter 190: node 310: P-channel metal oxy-semiconductor ❹ ❹ 11