200921812 cjN-ζυυ/υ^υυι 24316twf.doc/n 九、發明說明： 【發明所屬之技術領域】200921812 cjN-ζυυ/υ^υυι 24316twf.doc/n IX. Description of the invention: [Technical field to which the invention belongs]
且特另IJ 本發明是有關於一種封裝結構及其製作方法， 是有關於一種晶圓級封裝結構及其製作方法。 【先前技術】 近幾年來，隨著攜帶式（p〇rtable)電子產品 通訊以及及消費性電子產品之成紐已凌駕於傳統個人 月自（pc)產品之上，電子元件不斷地朝向高容量、 的高密度化、高頻、低耗能、多功能整合方向發展。而上 積體電路（integrated Circuit, IC )封裝技術方面，為配人古 輸入/輸出（I/O)數、高散熱以及封裝尺寸縮小化的= 下’使得晶粒級封裝（chip scaie package，csp)、晶圓 封裝（wafer level package )等高階封裝技術需求不;; 有別於傳統以單—晶片（die)為加工標的的封^ ，晶圓級封裝以晶圓（wafer)為封裝處理的對象， 要目的在簡化晶片之封裝製程，以節省時間及成本。^曰 積體Ϊ路製作完成以後’便可直接對整片晶圓進： 封裝製程，其後再進行晶圓切割（wafersaw)的 ^ =形成多個晶片封|體。製作完成之晶片封裝體 於載板上。 在使晶片與載板接合時，習知技術是在晶片之焊塾上 2凸塊，並以導電膠填充於晶片封裝體之 接墊之間。導電膠可將“封魏固定在载板上 200921812And the present invention relates to a package structure and a manufacturing method thereof, and relates to a wafer level package structure and a manufacturing method thereof. [Prior Art] In recent years, as portable (p〇rtable) electronic product communication and consumer electronics products have become superior to traditional personal monthly (pc) products, electronic components are constantly moving toward high capacity. The development of high-density, high-frequency, low-energy, and multi-functional integration. On the other hand, the integrated circuit (IC) package technology, for the ancient input / output (I / O) number, high heat dissipation and package size reduction = lower 'mice chip level package (chip scaie package, Csp), wafer level package and other high-end packaging technology requirements are not;; different from the traditional single-die (die) processing of the package, wafer-level packaging with wafer (wafer) packaging processing The object is to simplify the packaging process of the wafer to save time and cost. ^曰 After the completion of the integrated circuit, the wafer can be directly processed into the package: the package process, followed by wafer cutting (^) forming a plurality of wafer packages. The finished chip package is on the carrier board. When bonding the wafer to the carrier, conventional techniques are to bump 2 bumps on the solder pads of the wafer and fill the pads of the chip package with conductive paste. Conductive adhesive can be fixed on the carrier board.
CiN-zuu/wuui 24316twf.doc/n 片封裝體與載板電性連接。然而， 合的過程中，由於凸塊的推擠，導電膠中 塾間之電性如此，會降低凸塊與接 1電1·生連接柯讀，進❿降低晶y 間的電性連接的可靠度。 謂與载板之 【發明内容】 f)The CiN-zuu/wuui 24316twf.doc/n chip package is electrically connected to the carrier. However, in the process of bonding, due to the pushing of the bumps, the electrical properties of the turns in the conductive paste are such that the bumps are connected to the electrical connections, and the electrical connections between the crystals are reduced. Reliability. Said and carrier board [Summary] f)
本發明提供一種晶圓級封裝結構的製作方法 晶片封裝體與載板之間電性連接之可靠度。 N ^發，提出—種晶圓級封裝結構，其晶片封裂體與 載板間之電性連接具有較高的可靠度。 制作問題，本發明提出—種晶81級封裝結構的 衣作方法，其包括下列步驟。首先，提供_晶圓， 0具有^焊塾以及-保護層，而保護層具有多個第一= =將焊塾暴露。接下來，進行—凸塊製程，並於各焊塾 -=形成—凸塊。之後，於各凸塊之—頂面上分別形成 ⑽明另提出—種晶圓級封裝結構，其以上述晶圓級 封衣、.，#構的製作方法製作。 在本發明之—實施例中，上述凸塊製程包括以下步 驟。首先，於各焊墊上形成一球底金屬層。接下來，於各 球底金屬層上形成一凸塊。 、合 在本發明之一實施例中，上述凸塊之材質包括金。 在本發明之一實施例中，上述形成凹槽的方法包括以 200921812 CN-200704001 24316twf,doc/n 下步驟。首先，在凸塊以及保護層上形成一圖案化罩 圖案化罩幕具有多個第二開口，暴露出凸塊之—部分區 域。接下來，藉由@案化罩幕移除第二開口所暴露出^ 塊，以於各凸塊之頂面上分別形成凹槽。之後，移除圖案 化罩幕。 '、 在本發明之一實施例中’上述各凹槽包括多個溝渠。 在本發明之一實施例中，上述溝渠之深度介於〇至' 微米之間。 ' 在本發明之一實施例中，上述溝渠之截面積介於〇至 3〇平方微米之間。 在本發明之一實施例中，上述溝渠平行排列。 在本發明之一實施例中，上述溝渠更包括多個第一溝 、與夕個弟一溝渠，而第一溝渠之延伸方向與第二溝渠之 延伸方向交錯。 、 木 在本發明之一實施例中，上述各凹槽包括多個凹陷。 在本發明之—實施例中，上述凹陷之深度介於〇至2〇 微米之間。 在本發明之一實施例中，上述凹陷之戴面積介於〇至 3〇平方微米之間。 在本發明之一實施例中，上述凹陷呈陣列排列。 在本發明之一實施例中，上述凹陷呈不規則排列。 务3本發明由於在凸塊之頂面上形成凹槽，因此，在以導 電膠連接晶片封裴體與載板時，凹槽可固定導電膠中之導 電粒子，而使導電粒子不會因凸塊與載板之間的擠壓而滑 200921812 24316twf.doc/n ;:如此’可提高凸塊與載板之細的電性連接之可靠 舉實下文特 【實施方式】 Ο 的衣作方法流程圖。請參照圖1Α至圖1Η，太』構 級封裝結構的製作方法包括下列步驟 X之晶圓 认，提供-晶圓刚，其中晶圓刚上圖 以及:保護層12。，而保護層m具有多：;=;〇 以暴露出一部分的焊墊11()。 幵’ 122 接下來，請參照圖m至圖1D，進行 =独。由第—開口 122暴露之部分上分以 Ο 上述凸塊製程可包括以下步驟。首先，請參 於各焊塾110上形成一球底金屬層14〇 (見圖iH) ° ， 實施例中，上述形成球底金屬層140之形成，·可在曰。在本 表面形成-全面覆蓋之金屬層140, ’而在後續步 金屬層140圖案化以形成球底金屬層i4〇。 等 之後，如圖1C以及® m所示，於各球底金屬 上形成一凸塊130。形成凸塊130之方式例如可用二4〇 罩幕50覆蓋部分金屬層140,，並暴露出焊墊n〇弟一 金屬層140,，如圖lc所示。然後，如圖i 上方之 叮不，進行電 200921812 / vhvv i 24316twf. doc/n 鍵以在由第-罩幕5G暴露出之金屬層i4Q，上形成凸塊 130，其中凸塊130例如為金凸塊。 接下來’請參照圖1E至圖1G，於各凸塊13〇之一頂 面132上分別形成—凹槽134。在本實施例中，上述形成 凹槽134的方法可包括以下步驟。首先，如圖ie所示， 在凸塊130以及第-罩幕5〇上形成一圖案化罩幕6〇，其 中圖案化罩幕6G具有多個第二開口 62,暴露出凸塊13〇 之一部分區域。The invention provides a method for fabricating a wafer level package structure. The reliability of electrical connection between the chip package and the carrier board. N ^ issued, proposed a wafer-level package structure, the electrical connection between the wafer cracker and the carrier has a high reliability. In the production problem, the present invention proposes a method of coating a seed crystal 81-level package structure, which comprises the following steps. First, a _ wafer is provided, 0 has a solder bump and a protective layer, and the protective layer has a plurality of first = = exposed solder bumps. Next, a bump process is performed, and bumps are formed in each of the pads -=. Thereafter, a top-level wafer-level package structure is formed on the top surface of each of the bumps, and is fabricated by the above-described wafer level sealing, . In the embodiment of the present invention, the above bump process includes the following steps. First, a ball metal layer is formed on each of the pads. Next, a bump is formed on each of the ball metal layers. In an embodiment of the invention, the material of the bump comprises gold. In one embodiment of the invention, the method of forming the recess includes the steps of 200921812 CN-200704001 24316twf, doc/n. First, a patterned mask is formed over the bumps and the protective layer. The patterned mask has a plurality of second openings exposing a portion of the bumps. Next, the second opening of the second opening is removed by the @案化幕幕, so that grooves are formed on the top surfaces of the respective bumps. After that, remove the patterned mask. 'In one embodiment of the invention' the respective grooves comprise a plurality of channels. In one embodiment of the invention, the depth of the trench is between 〇 and 'micron. In one embodiment of the invention, the trench has a cross-sectional area between 〇 and 3 〇 square microns. In an embodiment of the invention, the trenches are arranged in parallel. In an embodiment of the present invention, the trench further includes a plurality of first trenches and a Xididi ditches, and the extending direction of the first trenches is staggered with the extending direction of the second trenches. In one embodiment of the invention, each of the grooves includes a plurality of depressions. In an embodiment of the invention, the depression has a depth of between 〇 and 2 μm. In one embodiment of the invention, the recessed wearing area is between 〇 and 3 〇 square microns. In an embodiment of the invention, the depressions are arranged in an array. In an embodiment of the invention, the depressions are arranged irregularly. According to the invention, since the groove is formed on the top surface of the bump, when the wafer package body and the carrier plate are connected by the conductive adhesive, the groove can fix the conductive particles in the conductive paste, so that the conductive particles are not caused by Squeeze and slide between the bump and the carrier plate 200921812 24316twf.doc/n ;: This can improve the reliability of the fine electrical connection between the bump and the carrier plate. [Embodiment] flow chart. Referring to FIG. 1A to FIG. 1A, the method for fabricating the package structure includes the following steps: the wafer is provided, and the wafer is provided, wherein the wafer is just above and the protective layer 12. And the protective layer m has many:;=;〇 to expose a part of the pad 11().幵' 122 Next, please refer to Figure m to Figure 1D and perform = alone. The portion of the bump exposed by the first opening 122 is divided into the following steps. The above bump process may include the following steps. First, a ball-bottom metal layer 14〇 (see FIG. iH)° is formed on each of the pads 110. In the embodiment, the formation of the ball-bottom metal layer 140 is formed. A metal layer 140, which is entirely covered, is formed on the surface, and is patterned in the subsequent step metal layer 140 to form a ball-bottom metal layer i4. After that, as shown in Figs. 1C and о m, a bump 130 is formed on each of the ball base metals. The bumps 130 are formed by, for example, covering a portion of the metal layer 140 with a mask 4 and exposing the pads to a metal layer 140, as shown in FIG. Then, as shown in the upper part of FIG. i, the voltage 200921812 / vhvv i 24316twf. doc/n is performed to form a bump 130 on the metal layer i4Q exposed by the first mask 5G, wherein the bump 130 is, for example, gold. Bump. Next, referring to FIG. 1E to FIG. 1G, a groove 134 is formed on one of the top surfaces 132 of each of the bumps 13A. In the present embodiment, the above method of forming the recess 134 may include the following steps. First, as shown in FIG. 1A, a patterned mask 6 is formed on the bump 130 and the first mask 5, wherein the patterned mask 6G has a plurality of second openings 62 exposing the bumps 13 Part of the area.
D 接下來，如圖1F所示，藉由圖案化罩幕6〇移除第二 開口 62所暴露出的部分凸塊13〇，以於各凸塊13〇之頂面 132上分別形成一凹槽134。之後，如圖所示，移除圖 案化罩幕60。之後，請參照圖1H，以凸塊13〇做為罩慕 將金屬層140’圖案化，以形成球底金屬層14〇。至此，大 致完成晶圓級封農結構之製作。 圖2為圖1H之實施例中晶片封裝體與載板連接示音 圖。請參照® 1Η及圖2，在完成上述步驟後，可 ; G 級封裝結構]00,進行一切割步驟，以將晶圓級封裝^ 刚’切割成多個晶片封裝體論，並將晶片封裝體、° 安裝至-触70上，且在載板7G之接墊72與 = ^間填入導電膠80，使晶片封裝體與載板70電性連 由於在本發明之晶圓級封裝結構的製作方法中，在各 凸塊130之頂面132上形成有一凹槽134，而凹槽1 固定導電膠δ〇中之導電粒子a，因此在將本發明之晶片 200921812 w —.一* 24316twf.doc/n 封裝體100a與載板70接合時，不易因導電粒子幻滑動而 發生壓合不破的現象。如此，可提高晶片封裳體！與載 板7〇之間電性連接的可靠度。 值得注意的是，上述凹槽丨34具可有多種實施方式， 以下以具有溝渠之凹槽以及具有凹陷之凹槽為例說明。圖 3為本發明一實施例中凸塊之俯視圖。請參照圖2及圖3， 在本實施例中，凸塊130a之凹槽134可以具有多個溝渠 〇 136，而溝渠136之深度以及截面積可配合導電膠8〇之導 電粒子82之大小來設計’以使溝渠136可固定並壓破導電 粒子82。在本實施例中，溝渠136之深度例如介於〇至2〇 微米之間，而溝渠136之截面積則介於0至30平方微米之 另外，溝渠136可以平行排列，如圖3中所示，亦可 父錯排列。圖4為本發明另一實施例中凸塊之俯視圖。請 參照圖4 ’在本實施例中，凸塊i30b之漢渠136更包括多 個第一溝渠136a與多個第二溝渠136b，而第一溝渠136a 〇 之延伸方向與第二溝渠136b之延伸方向交錯。 圖5為本發明又一實施例中凸塊之俯視圖。請參照圖 5 ’在本實施例中，凸塊130c之凹槽134可包括多個凹陷 138 ’其中凹陷138之深度以及截面積可配合導電膠（見圖 2)之導電粒子（見圖2)之大小來設計，以使凹陷138可 固定並壓破導電粒子。在本實施例中，凹陷138之深度介 於〇至20微米之間’而凹陷138之截面積介於0^30^ 方微米之間。 200921812 t 24316twf.doc/n 另外，凹陷m可呈陣列排列 =排列。圖6為本發明再一實二:::之:可 不圖規在本實施例中™之心; 在各晶圓級封裝結構的製作方法 _ , 、甶上形成凹丸，而凹槽可固定導雷躜 V電粒子，因此在將本發社 中之 础導電粒子滑動而發生壓合不破的;象=合時’ 南晶片封展體與載板之間電性連接的可靠：。如此，可提 雖然本發明已以實施例揭露如上，然其並 本發明’任何所屬技術領域中具有通常知識者=限疋 本發明之精神和範_，t可魅許之更域 脫離 二發明之保護範圍當視後附之申請專利範圍所界定 【圖式簡單說明】 圖 圖2為圖1H之實施例中晶片封裝體與載板連接示意 圖3為本發明一實施例中凸塊之俯視圖。 圖4為本發明另一實施例中凸塊之俯視圖。 圖5為本發明又一實施例中凸塊之俯視圖。 圖6為本發明再一實施例中凸塊之俯視圖。 11 200921812 24316twf.doc/n 【主要元件符號說明】 50 :第一罩幕 60 :圖案化罩幕 62 :第二開口 70 :載板 72 :接墊 80 :導電膠 82 :導電粒子 100 .晶圓 100’ ：晶圓級封裝結構 l〇〇a :晶片封裝體 110 :焊墊 120 :保護層 122 :第一開口 130、130a、130b、130c、130d :凸塊 132 :頂面 134 :凹槽 136 :溝渠 136a :第一溝渠 136b :第二溝渠 140 :球底金屬層 140’ ：金屬層 138 :凹陷 12D, as shown in FIG. 1F, a portion of the bump 13 暴露 exposed by the second opening 62 is removed by the patterned mask 6 〇 to form a concave surface on each of the top surfaces 132 of each of the bumps 13 〇 Slot 134. Thereafter, as shown, the patterned mask 60 is removed. Thereafter, referring to Fig. 1H, the metal layer 140' is patterned by using the bumps 13 as a mask to form the ball-bottom metal layer 14A. At this point, the fabrication of the wafer-level enclosure structure was completed. Figure 2 is a block diagram showing the connection of the chip package and the carrier in the embodiment of Figure 1H. Please refer to ® 1Η and Figure 2, after completing the above steps, G-level package structure]00, perform a cutting step to cut the wafer-level package into a plurality of chip package theory and package the chip The body, ° is mounted on the contact 70, and the conductive paste 80 is filled between the pads 72 of the carrier 7G and the ^ ^ to electrically connect the chip package to the carrier 70 due to the wafer level package structure of the present invention. In the manufacturing method, a recess 134 is formed on the top surface 132 of each bump 130, and the recess 1 fixes the conductive particles a in the conductive paste δ, so that the wafer of the present invention 200921812 w —.* 24316 twf When the package 100a is bonded to the carrier 70, the sealing of the conductive particles is not easily caused by the sliding of the conductive particles. In this way, the wafer sealing body can be improved! The reliability of the electrical connection with the carrier 7〇. It should be noted that the above-mentioned groove 丨34 has various embodiments. Hereinafter, a groove having a groove and a groove having a groove are exemplified. 3 is a top plan view of a bump in accordance with an embodiment of the present invention. Referring to FIG. 2 and FIG. 3, in the embodiment, the groove 134 of the bump 130a may have a plurality of trenches 136, and the depth and the cross-sectional area of the trench 136 may match the size of the conductive particles 82 of the conductive paste 8 The design is such that the trench 136 can hold and crush the conductive particles 82. In this embodiment, the depth of the trench 136 is, for example, between 〇 and 2 μm, and the cross-sectional area of the trench 136 is between 0 and 30 square microns. The trenches 136 may be arranged in parallel, as shown in FIG. Or the father can be arranged in error. 4 is a top plan view of a bump in another embodiment of the present invention. Referring to FIG. 4, in the present embodiment, the Han channel 136 of the bump i30b further includes a plurality of first trenches 136a and a plurality of second trenches 136b, and the extending direction of the first trench 136a and the extension of the second trench 136b The directions are staggered. Figure 5 is a plan view of a bump in accordance with still another embodiment of the present invention. Referring to FIG. 5', in the embodiment, the recess 134 of the bump 130c may include a plurality of recesses 138', wherein the depth and the cross-sectional area of the recess 138 can be matched with the conductive particles of the conductive adhesive (see FIG. 2) (see FIG. 2). The size is designed such that the recess 138 can fix and crush the conductive particles. In the present embodiment, the depth of the recess 138 is between 〇 and 20 μm and the cross-sectional area of the recess 138 is between 0 and 30 μm. 200921812 t 24316twf.doc/n In addition, the recesses m can be arranged in an array = array. FIG. 6 is still another second embodiment of the present invention::: it is not intended to be in the center of the TM in the present embodiment; in the fabrication method of each wafer level package structure, a concave pill is formed on the crucible, and the groove can be fixed. Leading 躜V electric particles, so the conductive particles in the base of the company are slipped and uncompressed; like = ' ' 'The reliability of the electrical connection between the south wafer sealing body and the carrier plate: Thus, although the present invention has been disclosed above by way of example, the invention of the present invention has the general knowledge of the invention, and is limited to the spirit and scope of the present invention. The scope of protection is defined by the scope of the appended patent application. [FIG. 2 is a schematic view of the connection between the chip package and the carrier in the embodiment of FIG. 1H. FIG. 3 is a plan view of the bump according to an embodiment of the present invention. 4 is a top plan view of a bump in another embodiment of the present invention. Figure 5 is a plan view of a bump in accordance with still another embodiment of the present invention. Figure 6 is a plan view of a bump in accordance with still another embodiment of the present invention. 11 200921812 24316twf.doc/n [Main component symbol description] 50: First mask 60: patterned mask 62: second opening 70: carrier 72: pad 80: conductive adhesive 82: conductive particles 100. wafer 100': wafer level package structure 10a: chip package body 110: pad 120: protective layer 122: first opening 130, 130a, 130b, 130c, 130d: bump 132: top surface 134: groove 136 Ditch 136a: first ditch 136b: second ditch 140: ball bottom metal layer 140': metal layer 138: recess 12