200921681 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種製造一記憶體單元之方法，且特 別是有關於一種製造用於一記憶體陣列之一記憶體單元之 方法。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a memory cell, and more particularly to a method of fabricating a memory cell for a memory array. [Prior Art]
快閃記憶體是非揮發性（N〇n-v〇iatile )記憶體的一種， 具有在將電源關閉之後，仍可以保存資料之優點。但快閃 記憶體相較其他類似的記憶體如唯讀記憶體（Read 〇nly memory ; ROM)’更具有可重複讀寫、讀寫速度快及功率 肩耗低等優勢，可說疋結合了揮發性及非揮發性記憶體之 優點。現在許多行動儲存裝置上如手機、Mp3播放器，大 量的使用快閃記憶體，更使快閃記憶體的需求量與容量有 跳躍式的成長。 現今之快閃記憶體多利用p型金屬氧化場效電晶體 (PMOS)來實現。-般金屬氧化場效電晶體之結構在間極 (Gate)與通道之間具有一氧化層（（}批〇_)，而快閃 記憶體則在控制閘（Controlgate;CG)與通道間多了一層 浮閘（F1〇atinggate;FG)。因為這層浮閘，快閃記憶體i 過施加電壓使電子進出此浮閘而決定高低態而儲存資料， 快速完成讀'冑'抹除。通常快閃記憶體最大的問題即在 於燒錄干擾’其來源為：⑴被選擇之位元線上，未選擇 Ϊ記憶體單元、;⑺被選擇之字元線上，未選擇之記憶體 早X，（3)未選擇之字元線及未元線上，未選擇之記憶體 200921681 :元而憶體陣列由於對記憶體區規劃未盡理 燒錄時間過長，更可能遭受損如此將使得資料 因此，如何設計一個記憶體陣列 (Segment—, *達到降低燒錄干擾 此一業界亟待解決的問題。 ’错由完善的切割 程度之目的，乃為 【發明内容】 和随!明的目的就是在提供一種記憶體陣列，記憶 呈陣_列之複數個記憶體區及複數個全域位 ^線’把憶體區包含呈陣列排列之複數個記憶體單元、複 數個選擇閘、複數個區域位元線及複數個區域字元線。選 擇閘及區域位元線對應於記憶體單元之行數設置，其中區 域位元線連接至各行記憶體單元及選擇開。區域字元線對 應於記憶體單元之列數設置，各連接至各列記憶體單元。 全域位7C線對應於記憶體區之記憶體單元行數設置，各連 接至各行記憶體區之各行記憶體單元之各選擇閘。 根據本發明之另一目的，提供一種製造—記憶體單元 之方法，記憶體單元係用於一記憶體陣列，包含下列步 驟：提供一 P型基板；形成一淺溝槽隔離（Shall〇w_tren讣 isolation)結構於該基板上；形成一 n井區於該基板上； 各形成一介電層於該淺溝槽隔離結構之兩側之溝槽；形成 一牙隧氧化層於該η井區上；沉積一浮閘多晶矽於該穿隧 氧化層上；形成一浮閘於該淺溝槽隔離結構上；沉積—絕 200921681 - 緣層於該浮閘上；沉積一控制閘多晶矽於該絕緣層上；以 、 及形成一控制閘於該浮閘上方之該絕緣層上。 根據本發明之又一目的，提供一種製造一記憶體μ _ 之方法，記憶體單元係用於一記憶體陣列，包含下列步 提供一 ρ型基板；形成一 η井區於該基板上；形成—穿隧 氧化層於該η井區上；沉積一浮閘多晶矽於該穿隧氧化層 上；沉積-物質層於該浮閘多晶石夕上；形成—淺溝槽隔離 ㈣及-浮閘，其中該浮㈣位於該淺溝槽隔離結構上； 〇 各形成一介電層於該淺溝槽隔離結構之兩側之溝槽内，俾 使該二介電層之高度與該物質層相等；以一化學^械研磨 法（Chemical mechanical p〇Hshing)磨平該二介電層之表 面；移除該物質層；姓刻該二介電層，俾使該二介電層之 高度與該物質層相等；沉積一絕緣層於該浮閘上；沉積一 控制閘多晶石夕於該絕緣層上；以及形成一控制間於該浮閑 上方之該絕緣層上。 本發明之優點在於藉由本發明之陣列分割方式，可使 (J 燒錄干擾程度降低而輕易地達到上述之目的。 在參閱圖式及隨後描述之實施方式後，該技術領域具 有通常知識者便可瞭解本發明之目的，以及本發明之技術 手段及實施態樣。 【實施方式】 請參照第1圖，其纷示依照本發明之第一實施例之一 記憶體陣歹"之一俯視圖。記憶體陣歹"包含複數個記憶 體區’係呈陣列排列。第i圖中繪示其中四個記憶體區1〇、 200921681 12、14及16。記憶體陣列1更包含複數個全域位元線及全 域字元線’其中全域位元線11a、lib、lie及全域字元線 13a、13b、13c經過記憶體區10。第2圖係記憶體區1〇進 一步之俯視圖。記憶體區1 〇包含複數個選擇閘2〇〇、複數 個通過閘202、複數個記憶體單元204、複數個區域位元線 201及複數個區域字元線203。其中記憶體單元204係呈陣 列排列，選擇閘200係對應於記憶體單元204之行數設置； 區域位元線201係對應於記憶體單元204之行數設置，各 連接至各列記憶體單元204及選擇閘200;通過閘202係對 應於記憶體單元204之列數設置；區域字元線203係對應 於記憶體單元204之列數設置，各連接至各列記憶體單元 204及通過閘202。 同時參照第1圖及第2圖，全域位元線Ua、llb、Uc 係分別連接至記憶體區10之各行記憶體單元所屬之選擇 閘，而全域字元線13a、13b、13c分別連接至各列記憶體 區各列記憶體單元所屬之通過閘《記憶體陣列1更包含複 數個區域位元線選擇線及區域字元線選擇線，於第丨圖中 之區域位元線選擇器17及區域字元線選擇線15,分別間隔 複數行/列記憶體單元設置。區域字元線選擇線15用以連 接複數列通過閘，區域位元線選擇器17用以連接複數列選 擇閘’以使各選擇閘及各通過閘可以於被選擇時導通。 記憶體陣列1更包含複數個源極線，如記憶體區1〇中 之源極線19 ’係間隔複數行記憶體單元設置。各該等源極 線連接至一電源供應及複數列記憶體單元之源極。各源極 線間隔之密度係視電源供應之電壓下降之程度而定，若電 200921681 壓隔較短之距離即下降，則源極線設置之密度上升。如第1 圖所示，源極線19連接至一電源供應18及複數列記憶體 單元之源極。須注意的是源極線並非直接連接該等記憶體 單元之源極上’而是實質上連接至源極周圍之一區域。各 源極線於電源供應及各記憶體單元間更包含一源極解碼 器’如源極線19上之源極解碼器19a。源極解碼器1%係 用以對不同之源極線提供不同之電壓。 第3圖為複數個記憶體單元2〇4之一剖面圖。虛框線 中所示為其中一記憶體單元204 ,包含一汲極3〇〇、_源極 3CH、一浮閘32、一穿隧氧化層31、一複晶矽介電層幻及 一控制閘34。汲極3〇〇及源極3〇1形成於一基板3之11井 區30上，沒極300係連接至一區域位元線，穿隨氧化層η 形成於汲極300及源極301間，浮閘32係形成於穿隧氧化 層31上；複晶矽介電層33形成於浮閘32上；控制閘34 形成於穿隧氧化層31上，係連接至一區域字元線。由第3 圖可以得知，各記憶體單元2〇4之汲極3〇〇及源極3〇丨係 可與鄰接之記憶體單元共用。記憶體單元2〇4可由—浮閘 相對源極及汲極之自我對準製程而形成。亦可更進—步由 一源極相對控制閘之自我對準製程而形成。 第一實施例中所述之記憶體陣列卜其中各記憶體單元 之燒錄、抹除及讀取係經由全域位元線及全域字元線先選 擇欲操作之記憶體區後，再進一步由區域位元線及區域字 元線選擇欲操作之記憶體單元。藉由如此的選擇方式，可 以避免不同區的記憶體單元之干擾，而大幅降低操作時 間。其中燒錄方式係由一關閉狀態熱電子注入（〇ff_state h〇t 10 200921681 electron injectlon)方式進行燒錄，此關閉狀態熱電子注入 方式係藉由一閘極輔助接面崩潰（⑽心…㈣細比⑽ breakdown)機制完成。被選擇之複數個記憶體單元之字元 線被施加一咼正電壓，未被選擇之複數個記憶體單元之字 兀線被施加-第-負電壓，源極被施加一第二負電壓。其 中第二負電壓之絕對值係大於第一負電壓，俾使被選擇及 未被擇之s己憶體單元間的隔離確實。而完成燒錄之動 作燒錄過私中，會經由至少一次的讀取過程以確認記憶 〔 冑單元之臨界電壓值是否大於或等於一特定電壓值。如臨 界電壓值未大於或等於該特定電壓值，控制問電壓或沒極 電壓將改變以再進行燒錄，直到記憶體單元之臨界電壓值 大於或等於此特定電壓值，而完成燒錄。 各e憶體單元之抹除方式則由一電子穿随方式進行抹 除。其中被選擇之複數個記憶體單元之閘極被施加拆之電 壓、位兀線被浮接、源極被施加uv之電壓及η井區被施 加11V之電壓，未被選擇之複數個記憶體單元之問極被施 〇 加6V之電壓、位元線被浮接、源極被施加ι1ν之電壓及打 井區被施加11V之電壓，以進行抹除之步驟。抹除過程中， 會經由至少一次的讀取過程以確認記憶體單元之臨界電壓 值是否小於或等於-特定電壓值，通常為_41¥。如臨界電 壓值未小於或等於該特定電壓值，控·電壓或没極電壓 將改變以再進行抹除，直到記憶體單元之臨界電壓值大於 或等於此特定電壓值，而完成抹除。 本發明之第二實施例係為一種製造一記憶體單元之方 法，該記憶體單元係用於如第一實施例所述之記憶體陣 11 200921681 列。第4A圖係為-如第-實施例所述之記憶體陣列中，立 中四個記憶體單元之方塊圖，圖中所框選之處係為一呓憶 體單元。#先以A彳向說明製造_記憶體單元之方法^ 步驟。提供-P型基板4，並形成—淺溝槽隔離結構仙於 P型基板4上，p型基板4之上半部再形成—n井區*卜於 形成η井區41後，進-步於淺溝槽隔離結構4〇之兩側之 溝槽各形成-介電層40a及40b。接著，形成—穿隨氧化層 42於n井區41上後’沉積一浮閘多晶矽43於穿隧氧化層 42上，如第4Β圖所示。接著，如第4C圖所示，形成一第 -圖案光阻層44於浮閘多晶石夕43上，再根據第一圖案光 阻層44钱刻#問多晶石夕43以形成浮閘43，於淺溝槽隔離結 構40上，形成如第4D圖所示之結構，其中㈣氧化層^ 亦跟著被蝕刻成為42，。移除第一圖案光阻層料後，沉積 一絕緣層45於浮閑43,上，再沉積—控制閉多晶石夕牝於該 絕緣層45上。接著，形成-第二圖案光阻層〇於控制問 多晶矽46上，再根據第二圖案光阻層47，沿平行a之方 向蝕刻控制閘多晶矽46以形成控制問46，於浮閘Μ，上，浮 閘上方以外之部份則被蝕刻掉，如第4E圖所示。其中絕緣 層45亦跟著被蝕刻成為45、接著由第圖之b方向觀之， 係為第㈣。移除第二圖案光阻層47後，換雜控制閑价 及浮閘43,兩側之淺溝槽隔離料4()，俾形成—没極_ 及一源極彻，成為第4A圖之結構。接著於沒極彻 f 4〇1及控制閘46,上各形成-接點，俾使各該接點各透過 —金屬線（未緣示出）與其他記憶體單元電性連接， 形成該記憶體陣列。 12 200921681 本發明之第三實施例亦為一種製造一記憶體單元之 方法，該圮憶體單元用於如第一實施例所述之記憶體陣 歹J第4G圖係為一如第一實施例所述之記憶體陣列中， 其中四個記憶體單元之方塊圖。帛4H圖為f 4G圖之c 方向之面圖’與第二實施例之不同處在於’在第二實施 例中於掺雜控制閘46,及浮閘43,兩側之淺溝槽隔離結構 40 ’俾形成一汲極4〇〇及一源極4〇1之步驟後，更形成一 ”電間隙壁48於控制閘46,及浮閘43，之兩側。再姓刻對 應於源極401 ’淺溝槽隔離結構4〇兩側之溝槽之介電層 40a及40b，俾使介電層4〇a及4〇b下之部份基板曝露， 如第41圖所示，係、為第4G圖沿D方向之剖面圖。離子佈 植- P型雜質於曝露之部份基板，俾使記憶體單元形成— 源極4〇1才目對控制閑46,之自我對準結構，最後再於沒極 糊、源極及控制閉46，上各形成一接點，俾使各該接 點各透過-金屬線（未緣示出）與其他記憶體單元電性連 接’進而形成該記憶體陣列。 ，於本發明之第四實施例中，第三實施例之掺雜控制閉 46’mi 43’兩側之淺溝槽隔離結構4() 彻及-源極彻之步驟可於源極相對控== 自我對準結構完成後再進行，並接著於沒極400、源極4〇1 及控制閘46’上各形成—接點以電性連接其他記憶體單 元。與第三實施例之不同處在於，坌__ ^㈣第二貫施例之源極401 極份接收到没極_之掺雜’而本實施例之源 極401將在源極較深處亦接收到汲極4〇〇之掺雜。 本發明之第五實施例為—種製造-記憶體單元之方 13 200921681 法，該記憶體單开田&[_ ^ 第从圖係為一如第用於音如弟一實施例所述之記憶體陣列。 個記憶體單元之方第塊一圖實施=述之記憶體㈣^ 單元之方法之久 百先以E方向說明製造一記憶體 早兀之方法之各步驟。提一 半部再形成— /、P基板5;P型基板5之上 51上後，沉穑 卜形成一穿隧氧化層52於η井區 2 V 浮閑多晶石夕53於穿隨氧化層”上，並再 沉積-物質層54於浮閘多晶㈣ ; 並: 質層54於本實施例 圖所不。物 f 弁阻屏為1化物。接著形成-第三圖案 幻物二：閘多晶矽53上’根據第三圖案光阻層55蝕 刻物質層54、浮閜炙曰故c，办 &51以^ , ㈣氧化層52及部份n井 ㈠以开/成-淺溝槽隔離結構5〇及浮閑53，，其中浮閘 53係位於淺溝槽隔離結構％上，如第冗圖所示。如此同 時餘刻多層的方法’可以使浮閘對準於源極及祕間之寬 度，而不會如第二實施例一般，浮閑寬度略大於源極及汲 =間之寬度。移除第三圖案光阻層55後，於淺溝槽隔離結 * 50之兩側之，冓槽各形成一介電㉟5如及娜，俾使二介 電層50a及5〇b之高度與物質層％相等。以一化學機械研 磨法（Chenncal mechanical p〇nshing)磨平二介電層心 及之表面後’移除物質層54，。敍刻二介電層他及 ’俾使二介電層5〇a及赐之高度與穿随氧化層^相 等。形成-多晶㈣隙^ 53，a於浮閘53兩側，俾使—絕 緣層56及-控制閘多晶碎57沉積於於浮開53，及多晶 隙壁53’a上。接著’如第5D圖所示，形成一第四圖案光 阻層58於控制間多晶石夕57上，再根據第四圖案光阻層％ 沿平行A之方向蝕刻控制閘多晶矽5 6以形成控制閘$ 7，於 14 200921681 f閘53上n方以外之部份則被㈣掉， 所示。其中絕緣層56亦跟著被钱刻成為56，。接二第口 之F方向觀之，係為第517圖。移 撿Ββ _杪除弟四圖案先阻層58後’ :制間57,及浮問53,兩侧之淺溝槽隔離結構50,俾形 成汲極5〇〇及一源極501。接著於、及極 c7, u _ 接者於汲極500、源極501及 "T 各形成一接點，俾使各該接點各透過—金屬線 (未繪示幻與其他記憶料元電輯接 成記 :體陣列。與第二實施例不同之處為，本實施例=體己 單元結構係為一浮開53，相董·!·、浪& , 準結構。 及汲極500之自我對 本發明之第六實施例亦為一種製造一記憶體單元之 方法’該記龍單元用於如第—實施例所述之記憶體陣 列第5G圖係為一如第五實施例所述之記憶體陣列中， 其中四個記憶體單元之方塊圖。第5Η圖為第圖之G 方向之剖面圖’與第五實施例之不同處在於，在第五實施 例中於掺雜控制開57’及浮閘，53，兩側之淺溝槽隔離結構 5〇 ’俾形成一汲極500及一源極501之步驟後，更形成一 介電間隙壁59於控制閘57，及浮閘53,兩側。再蝕刻對應 於源極5(H，淺溝槽隔離結構5〇兩側之溝槽之介電層他 及50b，俾使介電層50a及5〇b下之部份基板曝露，如第 51圖所示’係為第圖沿Η方向之剖面圖。離子佈植一 p 型雜質於曝露之部份基板’俾使記憶體單元形成一源極 5〇1相對控制閘57,之自我對準結構，最後再於沒極5〇〇、 源極5〇1及控制問57,上各形成一接點，俾使各該接點各 15 200921681 透過金屬線（未纷示出）與其他記憶體單元電性連接’ 進而形成該記憶體陣列。Flash memory is a type of non-volatile (N〇n-v〇iatile) memory that has the advantage of saving data after the power is turned off. However, flash memory has the advantages of repeatable reading and writing, fast reading and writing speed, and low power shoulder consumption compared with other similar memories such as read-only memory (ROM). Advantages of volatile and non-volatile memory. Nowadays, many mobile storage devices, such as mobile phones and Mp3 players, use a large amount of flash memory, which makes the demand and capacity of flash memory grow leaps and bounds. Today's flash memory is often implemented using a p-type metal oxide field effect transistor (PMOS). The structure of the general metal oxide field effect transistor has an oxide layer between the gate and the channel ((} batch _), while the flash memory is between the control gate (CG) and the channel. A layer of floating gate (F1〇atinggate; FG). Because of this layer of floating gate, flash memory i applies voltage to make electrons enter and exit the floating gate to determine the high and low state to store data, and quickly complete the read '胄' erase. Usually The biggest problem with flash memory is the burning interference. The source is: (1) the selected bit line, the memory cell is not selected, and (7) the selected word line, the unselected memory is X, ( 3) Unselected word line and un-elements, unselected memory 200921681: Yuan and memory arrays are more likely to suffer damage due to the unreasonable burning time of the memory area planning. How to design a memory array (Segment-, * achieves the problem of reducing the interference of burning in this industry. The purpose of the error is to perfect the degree of cutting, is the content of the invention] and the purpose of providing is to provide a kind of Memory array, memory a plurality of memory regions of the array_column and a plurality of global domain lines ^ the memory region includes a plurality of memory cells arranged in an array, a plurality of selection gates, a plurality of regional bit lines, and a plurality of regional word lines The selection gate and the area bit line correspond to the row number setting of the memory unit, wherein the area bit line is connected to each row of memory cells and is selected to be opened. The area word line corresponds to the number of columns of the memory unit, and each is connected to Each column of memory cells. The global bit 7C line corresponds to the number of memory cell rows in the memory region, and is connected to each of the row memory cells of each row of memory cells. According to another object of the present invention, a The method of manufacturing a memory cell, wherein the memory cell is used in a memory array, comprising the steps of: providing a P-type substrate; forming a shallow trench isolation (Shall〇w_tren讣isolation) structure on the substrate; forming a a n well region on the substrate; each forming a dielectric layer on the sides of the shallow trench isolation structure; forming a tunnel oxide layer on the n well region; depositing a floating gate polysilicon Forming a floating gate on the shallow trench isolation structure; depositing - 200921681 - edge layer on the floating gate; depositing a control gate polysilicon on the insulating layer; and forming a Controlling the gate on the insulating layer above the floating gate. According to still another object of the present invention, there is provided a method of fabricating a memory cell _ for a memory array comprising the following steps to provide a p-type a substrate; forming a n well region on the substrate; forming a tunneling oxide layer on the n well region; depositing a floating gate polysilicon on the tunneling oxide layer; and depositing a material layer on the floating gate polycrystalline stone Forming a shallow trench isolation (four) and a floating gate, wherein the floating (four) is located on the shallow trench isolation structure; each of the germanium forms a dielectric layer in the trench on both sides of the shallow trench isolation structure, The height of the two dielectric layers is equal to the material layer; the surface of the two dielectric layers is smoothed by a chemical mechanical p〇Hshing; the layer of the material is removed; Layer, the height of the two dielectric layers is opposite to the layer of the material ; Depositing an insulating layer on the floating gate; depositing a control gate on the eve of a multi-spar insulating layer; and forming on the insulating interlayer in a control of the floating above idle. The invention has the advantages that the array segmentation method of the present invention can easily achieve the above purpose by reducing the degree of interference of the programming. After referring to the drawings and the embodiments described later, the technical field has the usual knowledge. The object of the present invention, and the technical means and embodiments of the present invention can be understood. [Embodiment] Referring to Figure 1, there is shown a top view of a memory array according to a first embodiment of the present invention. The memory array contains a plurality of memory regions arranged in an array. In the figure i, four memory regions 1〇, 200921681 12, 14 and 16 are illustrated. The memory array 1 further includes a plurality of global regions. The bit line and the global word line 'where the global bit lines 11a, lib, lie and the global word lines 13a, 13b, 13c pass through the memory area 10. The second picture is a further top view of the memory area 1 . The area 1 〇 includes a plurality of selection gates 2〇〇, a plurality of pass gates 202, a plurality of memory cells 204, a plurality of regional bit lines 201, and a plurality of regional word lines 203. The memory cells 204 are arranged in an array. The selection gate 200 corresponds to the row number setting of the memory unit 204; the regional bit line 201 corresponds to the row number setting of the memory unit 204, and is connected to each column memory unit 204 and the selection gate 200; Corresponding to the number of columns of the memory cells 204; the region word lines 203 are arranged corresponding to the number of columns of the memory cells 204, and are connected to the column memory cells 204 and the pass gates 202. Referring to FIG. 1 and 2, the global bit lines Ua, 11b, Uc are respectively connected to the selection gates of the row memory cells of the memory region 10, and the global word lines 13a, 13b, 13c are respectively connected to the columns of the column memory regions. The pass gate to which the memory unit belongs: "The memory array 1 further includes a plurality of area bit line selection lines and area word line selection lines, and the area bit line selector 17 and the area word line selection line in the second figure. 15. The interval line/column memory unit is respectively arranged. The area word line selection line 15 is used to connect the plurality of columns through the gate, and the area bit line selector 17 is used to connect the plurality of column selection gates to make the selection gates and the respective gates Can be selected by gate The memory array 1 further includes a plurality of source lines, such as a source line 19' in the memory area 1', and a plurality of line memory unit settings. Each of the source lines is connected to a power supply and a plurality of sources. The source of the column memory cell. The density of each source line interval depends on the degree of voltage drop of the power supply. If the voltage of 200921681 is reduced by a short distance, the density of the source line is increased. 1 shows that the source line 19 is connected to the source of a power supply 18 and a plurality of columns of memory cells. It should be noted that the source lines are not directly connected to the sources of the memory cells' but are substantially connected to One area around the source. Each of the source lines further includes a source decoder 'such as a source decoder 19a on the source line 19 between the power supply and each of the memory cells. The source decoder 1% is used to provide different voltages to different source lines. Figure 3 is a cross-sectional view of a plurality of memory cells 2〇4. One of the memory cells 204 is shown in the dashed line, including a drain 3 〇〇, a _ source 3CH, a floating gate 32, a tunnel oxide layer 31, a polysilicon dielectric layer, and a control. Gate 34. The drain 3 〇〇 and the source 3 〇 1 are formed on a well region 30 of a substrate 3, the immersed 300 is connected to a region bit line, and the pass oxide layer η is formed between the drain 300 and the source 301. The floating gate 32 is formed on the tunneling oxide layer 31; the polysilicon dielectric layer 33 is formed on the floating gate 32; the control gate 34 is formed on the tunneling oxide layer 31 and is connected to an area word line. As can be seen from Fig. 3, the drain 3 〇〇 and the source 3 各 of each memory cell 2 〇 4 can be shared with adjacent memory cells. The memory cell 2〇4 can be formed by a self-aligned process of the floating gate with respect to the source and the drain. It can also be further advanced by a self-aligned process of a source relative to the control gate. In the memory array described in the first embodiment, the programming, erasing, and reading of each memory unit are performed by selecting a memory area to be operated via a global bit line and a global word line, and then further The area bit line and the area word line select the memory unit to be operated. With such a selection method, the interference of the memory cells in different areas can be avoided, and the operation time can be greatly reduced. The burning mode is programmed by a closed state hot electron injection (〇ff_state h〇t 10 200921681 electron injectlon), and the closed state hot electron injection mode is collapsed by a gate auxiliary junction ((10) heart... (4) The finer (10) breakdown) mechanism is completed. The word line of the selected plurality of memory cells is applied with a positive voltage, the word line of the unselected plurality of memory cells is applied with a -first negative voltage, and the source is applied with a second negative voltage. The absolute value of the second negative voltage is greater than the first negative voltage, so that the isolation between the selected and unselected suffix units is true. When the burning operation is completed, the reading process is performed at least once to confirm whether the threshold voltage value of the unit is greater than or equal to a specific voltage value. If the critical voltage value is not greater than or equal to the specific voltage value, the control voltage or the no-pole voltage will be changed to be burned again until the threshold voltage value of the memory cell is greater than or equal to the specific voltage value, and the programming is completed. The erase mode of each e-memory unit is erased by an electronic follow-up method. The gates of the selected plurality of memory cells are applied with the removed voltage, the floating lines are floated, the voltage of the source is applied with uv, and the voltage of the n well region is applied with a voltage of 11V, and the plurality of memories are not selected. The cell is applied with a voltage of 6V, the bit line is floated, the source is applied with a voltage of ι1ν, and the well area is applied with a voltage of 11V for the erase step. During the erasing process, at least one reading process is performed to confirm whether the threshold voltage value of the memory cell is less than or equal to a specific voltage value, which is usually _41¥. If the threshold voltage value is not less than or equal to the specific voltage value, the control voltage or the gate voltage will be changed to be erased again until the threshold voltage value of the memory cell is greater than or equal to the specific voltage value, and the erasing is completed. The second embodiment of the present invention is a method of manufacturing a memory cell for use in the memory array 11 200921681 as described in the first embodiment. Fig. 4A is a block diagram of four memory cells in a memory array as described in the first embodiment, and the frame is selected as a memory cell. #First, explain the method of manufacturing the _memory unit by A. Providing a -P type substrate 4, and forming a shallow trench isolation structure on the P-type substrate 4, and forming an n-well region in the upper half of the p-type substrate 4, after forming the n-well region 41, further The trenches on both sides of the shallow trench isolation structure 4 are formed with dielectric layers 40a and 40b. Next, a pass-through oxide layer 42 is formed on the n-well region 41 to deposit a floating gate polysilicon 43 on the tunnel oxide layer 42, as shown in FIG. Next, as shown in FIG. 4C, a first-pattern photoresist layer 44 is formed on the floating gate polycrystalline stone 43, and then according to the first pattern photoresist layer 44, the polycrystalline stone 43 is formed to form a floating gate. 43. On the shallow trench isolation structure 40, a structure as shown in FIG. 4D is formed, in which the (four) oxide layer is also etched to 42. After removing the first patterned photoresist layer, an insulating layer 45 is deposited on the floating layer 43, and then deposited to control the closed polycrystalline stone on the insulating layer 45. Next, a second pattern photoresist layer is formed on the control polysilicon 46, and according to the second pattern photoresist layer 47, the gate polysilicon 46 is etched in the direction parallel to a to form a control 46, on the floating gate. The part outside the floating gate is etched away, as shown in Figure 4E. The insulating layer 45 is also etched to 45, and then viewed from the direction b of the figure, which is the fourth (fourth). After the second pattern photoresist layer 47 is removed, the control price and the floating gate 43 are replaced, and the shallow trench spacers 4 () on both sides, the 俾 formation - the immersion _ and the source are thoroughly formed, and become the 4A map. structure. Then, the gates are formed in a state in which the gates are formed, and the contacts are formed, and the contacts are electrically connected to other memory cells through the metal wires (not shown) to form the memory. Body array. 12 200921681 The third embodiment of the present invention is also a method for manufacturing a memory unit, wherein the memory unit is used in the fourth embodiment of the memory array according to the first embodiment. In the memory array described in the example, a block diagram of four memory cells.帛4H is a view of the c-direction of the f 4G diagram. The difference from the second embodiment is that in the second embodiment, the doping control gate 46 and the floating gate 43 are shallow trench isolation structures on both sides. After the step of forming a drain 4〇〇 and a source 4〇1, an electric gap 48 is formed on both sides of the control gate 46 and the floating gate 43, and the surname corresponds to the source. The dielectric layers 40a and 40b of the trenches on the sides of the 401' shallow trench isolation structure are exposed to a portion of the substrate under the dielectric layers 4a and 4B, as shown in Fig. 41, A cross-sectional view of the 4G image along the D direction. Ion implantation - P-type impurity on the exposed substrate, so that the memory cell is formed - the source 4〇1 is the control of the self-aligned structure, Finally, a contact is formed on the non-paste, the source and the control closure 46, so that each of the contacts is electrically connected to other memory cells through the metal wire (not shown) to form the Memory Array. In the fourth embodiment of the present invention, the shallow trench isolation structure 4() on both sides of the doping control closing 46'mi 43' of the third embodiment is thorough and the source is completely stepped After the source relative control == self-aligned structure is completed, and then formed on the dipole 400, the source 4〇1 and the control gate 46' to electrically connect other memory cells. The difference of the third embodiment is that the source 401 of the second embodiment of the second embodiment receives the doping of the electrodeless electrode _ and the source electrode 401 of the embodiment will be deeper at the source. The doping of the drain 4 is received. The fifth embodiment of the present invention is a method for manufacturing a memory cell 13 200921681, which is a single open field & [_ ^ The first is used for the memory array described in the embodiment of the memory. The first block of the memory unit is implemented as a memory (four) ^ The method of the unit is first described in the E direction to create a memory early Each step of the method of 兀 提 提 提 提 提 提 提 / / / 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 提 ; ; ; The eve 53 is on the oxide layer and re-deposits the material layer 54 to the floating gate poly (4); and: the layer 54 is not shown in this embodiment. The object f 弁 resistance screen is 1 compound. Then forming a third pattern illusion 2: thyristor 53 on the etched material layer 54 according to the third pattern photoresist layer 55, floating c, and & 51 to ^, (4) oxide layer 52 and part n The well (1) is opened/formed-shallow trench isolation structure 5〇 and float 53, wherein the floating gate 53 is located on the shallow trench isolation structure %, as shown in the redundancy diagram. Thus, the method of multi-layering in the same time can align the floating gate with the width of the source and the secret, without the floating width being slightly larger than the width of the source and the 汲 = as in the second embodiment. After the third pattern photoresist layer 55 is removed, on the two sides of the shallow trench isolation junction * 50, the trenches each form a dielectric 355 such as 及, so that the heights of the two dielectric layers 50a and 5〇b are The material layers are equal. The material layer 54 is removed by smoothing the surface of the dielectric layer and the surface of the dielectric layer by a chemical mechanical polishing method (Chenncal mechanical p〇nshing). The two dielectric layers are etched and the two dielectric layers are 5〇a and the height is given to the oxide layer. Forming a polycrystalline (tetra) gap ^ 53, a on both sides of the floating gate 53, a barrier insulating layer 56 and a control gate polycrystalline powder 57 are deposited on the floating opening 53, and the polycrystalline spacer 53'a. Then, as shown in FIG. 5D, a fourth pattern photoresist layer 58 is formed on the inter-polycrystalline silicon wafer 57, and then the gate polysilicon layer 5 is etched in the direction parallel to A according to the fourth pattern photoresist layer % to form Control gate $7, at 14 200921681, the part of the n gate other than the gate 53 is (four) off, as shown. The insulating layer 56 is also engraved into 56. Take the second direction of the F direction, which is the 517th picture. After the 捡Ββ _ 杪 弟 图案 图案 图案 图案 先 先 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Then, at the end, and the pole c7, u _ picker forms a contact point on each of the bungee pole 500, the source pole 501 and the "T, so that each of the joints is transmitted through the metal wire (not shown with other memory elements) The electromagnet is connected to a body array. The difference from the second embodiment is that the present embodiment = the body unit structure is a floating opening 53, a phase, a wave, a quasi-structure, and a bungee The sixth embodiment of the present invention is also a method for manufacturing a memory unit. The memory unit is used in the fifth embodiment of the memory array as described in the first embodiment. In the memory array, a block diagram of four memory cells is shown. Figure 5 is a cross-sectional view of the G direction of the figure. The difference from the fifth embodiment lies in the doping control in the fifth embodiment. Opening 57' and floating gate, 53, shallow trench isolation structure on both sides 5〇'俾 forming a drain 500 and a source 501, further forming a dielectric spacer 59 on the control gate 57, and floating Gate 53, on both sides. Re-etching the dielectric layer corresponding to the source 5 (H, the trenches on both sides of the shallow trench isolation structure 5 and 50b, A portion of the substrate under the electrical layers 50a and 5〇b is exposed, as shown in Fig. 51, which is a cross-sectional view along the Η direction of the first image. The ion implants a p-type impurity on the exposed portion of the substrate to make the memory The unit forms a self-aligned structure of a source 5〇1 with respect to the control gate 57, and finally forms a contact point on the 5th pole, the source 5〇1 and the control 57, so that each of the contacts is connected. Point 15 200921681 Electrically connected to other memory cells through metal wires (not shown) to form the memory array.
57，L本發月之第七實施例中，第六實施例之掺雜控制閘 兩側之淺溝槽隔離結構50，俾形成一沒極5〇〇 社源極5〇1之步驟可於源極501相對控制閘57,之自我對 冓π成後再進行，並接著於没極5〇〇、源極及控制 問57’上各形成-接點以電性連接其他記憶體單元。與第三 ^施例之不同處在於，第六實施例之源極5G1將僅於表面 ^々接收到;及極5〇〇之掺雜’而本實施例之源極训將在 源極較深處亦接收到汲極500之掺雜。 上述以浮問相對源極及汲極之自我對準結構及源極相 對控制閘之自我對準結構均可使記憶體單元的面積更小， 進而使整體記憶體陣列之面積縮減。 由上述本發明較佳實施例可知，應用本發明之單一電 晶體（1Τ)記憶體單元而組成之記憶體陣列，可以透過選 擇閘及通㈣進行字元線及位元線方向的分割，在形成較 小分割區塊的同時降低燒錄干擾。藉由閑極輔助接面崩潰 以產生關閉狀態熱電子之方法進行燒錄及一電子穿随方式 進行抹除。在施加以適當之電壓後，亦可達到抑止干 成效，均是本發明之優點。 雖然本發明已以較佳實施例揭露如 限定本發明，任何熟習此技蓺者 仪《考，在不脫離本發明之 和範圍内’當可作各種之更叙谕神执 更動與潤飾，因此本發明之 範圍當視後附之中請專利範圍所界定者為準。 ’、° 16 200921681 【圖式簡單說明】 ^為讓本發明之上述和其他目的、特徵、優點與實施例 食b更明顯易懂，所附圖式之詳細說明如下： 第1圖是本發明之一記憶體陣列之俯視圖； 第2圖是本發明之一記憶體區之俯視圖； 第3圖是本發明之複數個記憶體單元之一剖面圖； 第4A圖·第41圖是本發明製造一記憶體單元之流程圖 以及； 第5A圖-第51圖是本發明製造一記憶體單元之流程圖57, in the seventh embodiment of the present month, the shallow trench isolation structure 50 on both sides of the doping control gate of the sixth embodiment, the step of forming a immersive 5 〇〇 source 5 〇 1 can be The source 501 is opposite to the control gate 57, and the self-alignment π is performed, and then the contacts are formed on the 5 poles, the source and the control 57' to electrically connect the other memory cells. The difference from the third embodiment is that the source 5G1 of the sixth embodiment will be received only on the surface; and the doping of the pole 5' and the source training of the embodiment will be at the source. The doping of the bungee pad 500 is also received in the depth. The self-aligned structure of the floating gate relative to the source and the drain and the self-aligned structure of the source relative gate can reduce the area of the memory cell, thereby reducing the area of the overall memory array. According to the preferred embodiment of the present invention, the memory array formed by applying the single transistor (1 Τ) memory cell of the present invention can perform segmentation of the word line and the bit line direction through the selection gate and the pass (four). The formation of smaller partitions reduces the burn-in interference. The eraser assists the junction collapse to generate a closed state hot electron for burning and an electronic follow-up method for erasing. It is also an advantage of the present invention that the effective effect can be achieved after applying a suitable voltage. Although the present invention has been described in terms of the preferred embodiments of the present invention, it is to be understood that the skilled artisan is capable of various modifications and refinements without departing from the scope of the invention. The scope of the invention is defined by the scope of the patent application. ',° 16 200921681 BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious, the detailed description of the drawings is as follows: FIG. 1 is the present invention 1 is a plan view of a memory region of the present invention; FIG. 3 is a cross-sectional view of a plurality of memory cells of the present invention; FIG. 4A and FIG. 41 are views of the present invention. Flowchart of a memory unit; and FIG. 5A to FIG. 51 are flowcharts of manufacturing a memory unit of the present invention
[主要元件符號說明】 •記憶體陣列 1〇、12、14、16 :記憶體區 la、lib、lie :全域位元線na、m、13c :全域字元線 17:區域位元線選擇器 15 :區域字元線選擇線 18 :電源供應 19a :源極解碼器 201 .區域位元線 2〇3 ·區域字元線 3 :基板 3〇〇 :汲極 31 :穿隧氧化層 33 .複晶發介電層 4 : P型基板 4〇a、40b :介電層 200 :選擇閘 202 :通過閘 204 :記憶體單元 30 ： η井區 301 :源極 32 ： 浮閘 34 ： 控制閘 40 ： 淺溝槽隔離結構 400 :汲極 17 200921681 401 :源極 41 ： 42 :穿隧氧化層 43 ： 43’ ：浮閘 44 ： 45 :絕緣層 45,： 46 :控制閘多晶矽 46,： 47 :第二圖案光阻層 48 ： 5 : ρ型基板 50 ： 50a、50b :介電層 500 ： 501 :源極 51 ： 52 :穿随氧化層 53 ： 53’ ：浮閘 53，a 54 :物質層 54,： 55 :第一圖案光阻層 56 ： 56’ ：絕緣層 57 ： 57’ ：控制閘 58 ： 59 :介電間隙壁 η井區 浮問多晶砍 第一圖案光阻層 絕緣層 控制閘 介電間隙壁 淺溝槽隔離結構 :汲極 η井區 浮閘多晶石夕 :多晶矽間隙壁 物質層 絕緣層 控制閘多晶矽 第二圖案光阻層[Main component symbol description] • Memory array 1〇, 12, 14, 16 : Memory area la, lib, lie: global bit line na, m, 13c: global word line 17: area bit line selector 15: area word line selection line 18: power supply 19a: source decoder 201. area bit line 2 〇 3 · area word line 3: substrate 3 〇〇: drain 31: tunnel oxide layer 33. Crystalline dielectric layer 4: P-type substrate 4〇a, 40b: dielectric layer 200: selection gate 202: pass gate 204: memory unit 30: η well region 301: source 32: floating gate 34: control gate 40 : Shallow trench isolation structure 400: Deuterium 17 200921681 401 : Source 41 : 42 : Tunneling oxide layer 43 : 43 ' : Floating gate 44 : 45 : Insulation layer 45 , : 46 : Control gate polysilicon 46 , : 47 : Second pattern photoresist layer 48 : 5 : p-type substrate 50 : 50a, 50b : dielectric layer 500 : 501 : source 51 : 52 : through oxide layer 53 : 53 ' : floating gate 53, a 54 : material layer 54: 55: first patterned photoresist layer 56: 56': insulating layer 57: 57': control gate 58: 59: dielectric spacer η well region floating polycrystalline A first insulating layer patterned photoresist layer control gate dielectric spacer shallow trench isolation structure: η drain plurality spar floating gate well region Xi: polysilicon spacer material layer, the second polysilicon control gate insulating layer patterned photoresist layer
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