TW200850099A - Advanced multilayered coreless support structure, and their fabrication - Google Patents

Abstract

To provide a method of fabricating an advanced multilayered coreless support structure. The method includes the stages of: (I) fabricating a membrane including conductive vias in a insulating material on a sacrificial carrier, and (II) detaching the membrane from the sacrificial carrier to form a freestanding laminated array. The membrane contains the via array in a insulating material. A method of fabricating an advanced multilayered coreless support structure also includes at least the stages of: (I) fabricating a membrane including conductive vias in a insulating material on a sacrificial carrier, and (II) detaching the membrane from the sacrificial carrier to form a freestanding laminated array; (V) thinning and planarizing; and (VII) terminating.

Description

200850099 TPPO/P2855-001 IX. Description of the Invention: [Technical Field] The present invention relates to a multilayer coreless support structure and a method of fabricating the same. [Prior Art] The electronics industry is becoming more and more complicated and miniaturized', especially in mobile devices such as mobile phones and portable computers, where space is very precious. Integrated circuits (ICs) are the core of these electronic systems. Similarly, i(:s is also becoming more complex, integrating more and more transistors' requires more and more input turns out of the contacts. They want Working at faster conversion speeds and frequencies requires more power and generates a lot of heat that needs to be dissipated. ICs are connected to power supplies, user interfaces and other components through printed circuit boards (PCBs), in order to make these MPCBs The connection between the two is easier, and the electrical connection needs to be provided. The usual method of praying is to use an electronic substrate to connect and its coffee. The electronic substrate is part of the IC package, which replaces the traditional lead frame. As an insertion mechanism between 1C and its PCB, such a substrate may include a 'two or more office layers, which are separated by a variety of insulating materials, such as Tao Jing or organic materials. There is a contact conduction array at the bottom. The conductive contacts can be spherical contacts, providing a so-called ball grid array (BGA) or pin for the electrical connection of the PCB, or a so-called pin array (10) > as an alternative Select ' _ substrate can be used to make __ point scale and be directly mounted on the 200850099 TPPO / P2855-001 PCB 'provides a so-called rectangular grid array (lga). At the top, the substrate usually passes the known wire bonding technology or Flip-chip package technology to carry one or more electrically connected ICs. Figure 1 shows an example of a prior art wire-bonded BGA package, including a substrate 100, connecting the substrate 1 to a thin pad 104 to the bottom PCB (Figure The ball-and-ball array (BGA) of the ball 102 is not shown, and the electrical wire array, that is, the wire bonding 1〇6, which is connected to the top pad 1〇8 to the IC 11〇 of the substrate 100. The IC 11 is typically protected by a resin material 112, also known as a molding material. Figure 2 shows an example of a prior art flip chip BGA package containing an inverted I wafer BGA substrate 2GG. The array (BGA) 2() 2 connects the pad 204 on the bottom side of the substrate to the bottom pcB. However, the electrically conductive bumps 2〇6 located above the top pad 208 of the substrate replace the wire bonding, using a flip chip process. The technology is connected to 21G. In this jade art, it is also included in the IC and substrate 20 A resin material 212 is applied between the surfaces of 0. In this technique, the resin material 212 is also commonly referred to as an 'unfilled' material. The resin 212 acts as a stress buffering material, reducing the lifetime of the 1C 210 and the bumps 206 over the life of the package 250. Fatigue generated during thermal laps. Sometimes the 'flip-chip package 25' also includes a metal reinforcement layer 216 attached to the substrate 200 by the dead layer 218 and a cover 220 attached to the π back surface by the thermal adhesive layer 222. The reinforcement layer 216 is used to further strengthen the substrate 2〇〇 and to help maintain the flatness of the subsequent ic integration process, while the cover 22G helps dissipate the heat generated by the ic 21〇 during operation. 6 200850099 TPPO/P2855-001 The new BGA substrate, PGA substrate, LGA substrate of the above-mentioned inspection line process and wafer process shown in Figure 1, ® 2 generally consists of two main parts: a so-called "core part" and The "combination part" of the layer construction. Figure 3 shows a detailed example of a typical organic fcbga substrate. The core portion 33 of the substrate 300 is slightly formed by a plurality of copper conductor layers separated by a glass fiber reinforced organic insulating layer. The copper conductor layer 332 in the core 330 is electrically connected by a metallized via (ρτΗ) 336. L brother, in the process of making the substrate 300, the core part is first made. Metallized through-holes are then made by mechanical drilling, copper ore and plug holes. Then, the outer scale of the core portion 33 is made. Two combined partial pastes, and then are added to both sides of the core 3〇〇. These combined portions 34 〇, 34 〇 are spaced apart by an insulating layer 344 of a copper 342 _, _ thin side glass fiber. The interior of the insulating layer includes a mineral copper microvia, which is connected to an adjacent copper conductor layer. The microvias are typically fabricated by a laser drilling process so that their diameter is typically smaller than the metallized vias 336. This saves valuable space on the base 300 for application ic. The dielectric used for the combined portion has improved mechanical and electrical properties: -ir/v Π3 / , /,, 'and the higher H' achieved by using the microvia 346 reaches the density of the IC contacts and acts as Connect the intermediate contacts of the PCB. It is noted that the core portion 33 of the substrate 300 of the FCBGA operates: the internal connection "carrier" of the m34Q', and is suitable for the power supply and ground copper conductor layers of the progress. 200850099 TPPO/P2855-001 Due to its more _!/0 position, Hyundai IG is not expected to be a good one. If the green part of the ridge is set on the side of the nucleus = point, this will be difficult to achieve. In order to make a ^tan, no _ bottom in the Ic domain process, the combination part of the lining is placed on both sides of the core part, and a symmetrical structure is formed to produce a stress-balanced, flat substrate. / However, in the case of the _m group, the division is a generation _, which will increase the T for the working age and add _. The substrate structure obtained by the method of the material is more, so the production yield is also lowered. Moreover, an increase in the thickness of the substrate results in a descent drop, which does not require a thicker package for mobile-devices and other areas requiring small size. In addition, an increase in the thickness of the substrate results in an increase in the thermal resistance of the package. These can destroy the performance of 1C. Based on these shortcomings, we have made many attempts to change the above-mentioned two Meiji structures*. - Two types of 2 small thicknesses are made of a base material without a core (four), providing a τ-type coreless substrate, technology. In this technique, the core portion of the BGA (or PGA, -GA) side of the substrate is removed by slitting, whereby the entire weave bottom contains only a combination of parts for connecting Ic to (10). The thickness of the substrate is greatly reduced, along with its thermal impedance and electrical properties. In addition, the removal of the core portion of the substrate enables the manufacturing time of the process and eliminates the need for expensive mechanical drilling of PTHs. The present patent application of the PCT Patent Application No. _2002/ 0001 937, which is incorporated herein by reference, which is incorporated herein by reference in its entirety, the entire entire entire entire entire entire entire entire entire entire disclosure Metal Interconnect, 200850099 TPPO/P2855-001 ~ The sheet was later partially removed to make a metal support and ride, and the metal support reinforcement was provided with holes for connecting ic. Although, USK 2002/0001937 to Kikuchi provides a viable green color for a core substrate, the mosquito has a fresh defect. All of the conductor layers of Wei Wei require expensive _ interconnections. _ This kind of interconnection is good due to improved density and finer spacing, but it is not suitable for making lower density and large pitch power and ground layers, while making this expensive thin film interconnection economically Not feasible. In addition, these layers generally require a specific metal thickness to reduce electrical resistance and to prevent overheating. It will be difficult to achieve this effect by making _film maker #. Furthermore, the flip chip bonding process imposes stresses that are unacceptable to the interconnect structure. The thickness of the film is generally no more than 100 microns, which forces the interconnect structure to be deformed or stretched. This situation sometimes causes damage to the thin film insulating layer, thereby causing the IC to operate. In addition, the presence of the golded portion of the 'IG__ will be a valuable space on the outer surface of the substrate, limiting its use in applications where passive components are required, such as light capacitors close to 1C. Furthermore, large-diameter metal reinforced portions can cause such techniques to be unsuitable for applications such as multi-wafer substrates, low-sized substrates, and two-dimensional matrix arrays or π-structured substrates.

U.S. Patent No. 6,872, 589 to the name of U.S. Patent No. 6,872, issued to the entire entire entire entire entire entire entire entire entire entire entire entire- section. The substrate referred to by _stanberg in patent 咫 6,872,589 is more than all the defects in the USSN 2002/00_7 patent due to the lesser cost of the 200850099 substrate in the patent defense 2〇〇2/〇〇〇1937. ~, According to the above content, many lead poems have no core base. In order to meet this demand, we must:: a low-cost, high-performance heart, a kind of expensive thin-brick structure with a sleek way, (4) replaced by other established and commonly used in the ordinary pgB manufacturing industry Cheap materials and broken. Unlike the _insulating material, this method of __ technology is applied, and it is strengthened by glass-dimensional or other reinforcing materials. By reasonably selecting these insulating materials, a self-supporting, coreless base structure that eliminates or at least reduces the need for metal reinforcements may be made. Furthermore, the use of relatively low cost, existing PCB processes It is expected to provide an economical multi-layer substrate that includes both low-density, large-pitch power and ground metal layers and high-density, small-pitch metal signal layers. This layered structure is _ _ _ is subjected to hot pressing Or during the hardening process. Therefore, there is no lack of safety in the bottom of the wire, and the flatness can be removed. When the substrate is only in the object of Jingu County 4, the substrate is removed before the assembly of 1C. Or _, as a reinforcing support substrate, during the production process, the interior of the production of unbalanced stress. These stresses may be released by the peeling of the metal carrier 'will lead to the f-curve and _ of the substrate. This deformation will lead to low assembly ic The yield may also be difficult to install on the corresponding pCB board. In order to solve this problem, the US patent of US 6, 913, 814 200850099 TPPO/P2855-001 proposed by Ho et al. The lamination process and its corresponding structure, in which a nano-density multilayer substrate is provided, which are separately fabricated and finally stacked. The method provides a common metal carrier base that is different from the prior art. On-chip 'official, multi-layer substrate selection, this technology seems to be able to take advantage of the tested material process in the PCB fabrication industry, where the towel is replaced by a solid copper microchannel, providing an economical organic coreless substrate. f, 35 and 'US 6,913, 814 towel technology has two important defects: First, for the clothing to be attached to the PCB with a low pitch and a high pitch W side, the mouth structure' The substrate must be composed of separate layers, each layer having a different density and different thicknesses of the bar, and the layer of the layer. This condition causes the imbalance, asymmetry of the curve, and the structure is like the prior art. As is well known, the use of through-hole-pad connections between layers of the substrate established by metal conduction through the insulating layer stack is a good IC performance because it leads to Hole contact loss (4) (This belt is faulty. This situation is particularly noteworthy in the temperature-temperature process used in the process of 1C mounting to the substrate. The application of the inventor of this Mamming is pending, H_itz et al. 2〇〇5年1〇月,1,曰's IL171378 named “New Integrated Circuit Support Structure and Its Producer 22nd Sub-Base” The manufacturing method includes the following steps: “) Θ, (8) on the substrate Adding a gamma-resistant barrier layer to the layer; (c) adding a sub-layer; (4) fabricating a more stacked conductive layer and an insulating layer of the first half-layer, the pass-through layer is connected through a through-hole through the insulating layer; (4) in the first half Adding 11th 200850099 A to the laminate I wish / TPPO/P2855-001 layer W added a protective cover layer in the second Jinxian film layer; (8) d Zhuodi substrate layer; (h) removing photoresist Layer; (Remove the initial anti-etching = two more layers of the second half of the laminated layer and the insulating layer, the conductive layer through the shirt, (4) #物-+ ship-symmetric, k, stacked conductive layer and insulating layer U) is added to the second half of the stack to remove the second metal substrate layer.

(d) In the processing of sub-378 proposed by tz et al., which essentially consists of half of the structure required for the formation on the sacrificial substrate, the end is terminated by a thick layer: the second layer: the layer becomes the second sacrificial substrate The first-half layer is symmetrical with respect to the first sacrificial substrate, and the first layer is symmetrical. In principle, the younger-semi-laminate and the second-half stack should be mirror images of each other, with the opposite side force, and the tendency of the four sides. But 'because these pile structures are made outward from the center, the first half stack is made from the center, and the second half stack on the first half stack is also made out of the heart.' It is difficult to ensure The process conditions of the two halves of the stack - the difference between _ often leads to the occurrence of the underlying money - some unbalanced stress, which leads to the bending of the substrate ' _ bending _ base Wei in line with advanced IG carving, such as stacked package (PGP), package package (PIP), stack 4 Ic dragon, installed with several ^ flip or other wire bonding process (4) strict plane requirements. For these reasons, Hurwitz et al. proposed 378, although it has moved forward with the original technology, a large 12 200850099 TPPO/P2855-001 two 'but the shop is not mixed with a large number of active layers of multi-layer, Na structure, the finished product of the above structure The rate drops. Therefore, in spite of the above advancement and the iu Cong proposed by Hurwitz et al., considering the strict requirements of (4) for the flatness, the health f has to propose a better and more complicated process and the corresponding wafer support structure. The structure should be able to have the advantage of being economical and high in yield even if applied in many layers of structures. The present invention takes this need into consideration and provides new process technologies and new structures. SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-layered interconnect support structure fabrication technique that is very versatile. Another object of the present invention is to provide a manufacturing technique with high yield. Another object of the present invention is to make an array of vias between conductive layers without the use of a time-consuming, expensive process that can only be used to make circular cross-section vias. It is a particular object of the present invention to provide a fabrication process for a multi-layer interconnect support structure having good planarity and flatness. This Maoyue has fine enamel in order to provide a high-reliability multilayer interconnect support structure. Benming provides a thinner 14-core layered substrate for single or multiple K than the prior art, with a plurality of conductive power layers and a ground metal layer at 2 high density, fine pitch a signal layer, which is interconnected by a copper k-hole interconnected by an insulating layer. The copper via can have any cross-sectional shape and is not round. 200850099 / » 诂r- TPPO/P2855-001 shape; the substrate can be low Loss transmission of electronic money, heat p and resistance to small. Another particular object of the present invention is to provide a self-supporting, flat, enamel layered substrate that can accommodate ICs that are assembled and assembled using a chip. Such substrates can also be provided in a unitary or multi-unit manner prior to the job. These multiple units can be arranged by means of a matrix array or a strip array. In addition, the purpose of this is to provide a substrate fabrication process and the substrate of (4), which comprises a large number of layers using a power source and a ground metal layer, and has a low density, with a suitable age. The thickness is transferred to the Wei resistance, thus preventing overheating. In addition, the purpose of this is to provide a substrate manufacturing process and a substrate made therefrom. The bottom of the county contains a layer or layers on both sides of the medium structure. The layers are in the __, phase _ Prepared under the preparation conditions, withstand the residual stress of the balance, with a good flat button. In a first aspect, the object of the present invention is to provide a method for fabricating a substructure of a job-reading method, which comprises an array of via holes in which an insulating material is fired, and the method of fabrication comprises stages: I-on a sacrificial carrier Making a film containing conductive vias enclosed in an insulating material; Π-the film described on the sacrificial carrier, the vertical layered array stage I includes substeps·· 14 200850099 TPPO/P2855-001 (i a full-plate plating barrier metal layer on the sacrificial carrier; (ii) adding a copper seed layer to the resistive metal layer; (iii) adding a photoresist layer on the copper seed layer, exposing and developing a photoresist pattern; (iv) a copper via hole in the photoresist pattern; (v) stripping the photoresist layer, leaving an upright copper via; (vi) stacking an insulating material over the copper via, The freestanding film thus formed contains an array of copper vias in the insulating matrix. In another embodiment, the stage 丨 includes sub-steps: (〇 adding a photoresist layer directly on the sacrificial carrier, exposing, developing, forming a photoresist pattern; (11) plating the line in the formed photoresist pattern (iii) wire-plated copper vias on the line-plated barrier metal; (iv) strip the photoresist layer to expose the copper vias; (v) stack the insulating material outside the exposed copper vias. The method includes the steps of: (V1) removing the sacrificial carrier layer' thereby forming an electronic substrate including a copper structure including a barrier metal layer in the insulating matrix. In the first aspect, the present invention is to provide a method prepared by the above method. A self-contained via film comprising an array of insulative materials. The invention provides a method for fabricating an electronic substrate, the method comprising at least 15 200850099 TPPO/P2855-001: I- fabricated on a sacrificial carrier a film comprising conductive vias surrounded by an insulating material; II- from the sacrificial carrier layer - said film forming a free-standing layered array; V-thinning, leveling; VI-assembly; VII-terminal stage. The conductive vias may be fabricated by copper plating, which is selected from the group consisting of electrowinning and chemical forging. Stage I comprises sub-steps: (i) plating a barrier metal layer on a sacrificial carrier; (ii) attaching Adding a copper seed layer to the metal layer; (iii) adding a photoresist layer on the copper seed layer, exposing and developing to form a photoresist pattern; (iv) plating a copper via hole in the photoresist pattern; (v) Stripping the photoresist layer leaving the erected copper vias; (vi) stacking the insulating material over the copper vias; Stage II includes sub-steps: (vii) removing the sacrificial carrier layer; (viii) removing the barrier metal layer, thereby The resulting electronic substrate contains a copper structure in an insulating matrix. 16 200850099 TPPO/P2855-001 Typically, in this embodiment, the barrier metal layer comprises at least one of the following features: (a) the barrier metal layer is selected from the group consisting of Metal·钽, tungsten, chromium, titanium, titanium-tungsten combination, titanium button combination, nickel, gold, nickel layer, gold layer, gold layer, nickel layer, tin, lead, lead layer, tin layer, tin-lead alloy, tin A silver alloy, the barrier metal layer is prepared by a physical vapor deposition process.

(b) The barrier metal layer is selected from the group consisting of nickel, gold, gold layer after recording layer, nickel layer after gold layer, tin, lead, post-stack tin layer, tin-alloy, tin-silver alloy, and barrier metal layer It is prepared by a method selected from electroless plating and electroplating. (c) The thickness of the barrier metal layer is from 1 μm to 5 μm. As an optional turn, the method Wei Wei ΠΙ · · Add metal Wei layer and additional through hole layer 'formed an internal substructure, the shaft substructure including the center plane surrounded by the through hole layer, Cheng, in the _ The electronic substrate established on the substructure includes an odd number of metal functional layers. Typically, the stage includes sub-steps: (4) adding a photoresist layer, exposing, developing, forming a functional pattern; (b) adding a copper layer to the functional pattern; (c) stripping the photoresist; (d) adding a second light The layer is exposed and developed to form a through-hole pattern; (e) green failure in the via pattern, copper plating, forming a copper via; (Ο stripping the second photoresist layer; 17 200850099 ( g) Etching off the steel seed layer; TM^Ρ2855-〇〇1 (h) Laminating the insulating material. In addition, the internal substructure of the via layer 'in:: several metal functional layers in the center surrounded by layers. The electronic substrate established on a stand-alone basis includes the step IV of the outer layer, the outer layer, the ship layer and the through-hole layer, including the layered insulating material added by the (i), flattening step (8), exposing y^( e) the outer surface of the copper through hole added; the eighth (J) is attached to the outer surface of the copper through hole and the surrounding insulating material, such as titanium, road, nickel chrome; Adding a copper seed layer to the adhesion metal layer; (1) adding a second functional layer of the photoresist on the copper seed layer, performing exposure, development, and shape (2) Adding a metal functional layer to the second functional pattern; (n) stripping the second functional layer of the photoresist; • (〇) adding a third via layer of light, exposure, development, Forming a third via pattern (Ρ) to plate copper in the third via pattern to form a third copper via layer; (q) stripping the third layer of photoresist ·, 18 200850099 TPPO/P2855-001 (Γ) money Cutting off the copper seed layer and the attached metal layer; (S) laminating the insulating material layer. As an alternative, the method of thinning and flattening the insulating material added in the step (h) in the step (1) is selected from the group consisting of: mechanically, chemically Mechanical polishing, dry multi-step process using two or more of the above techniques. Stage I contains sub-steps: (·) directly add photoresist material on the sacrificial carrier, expose, develop, form a photoresist pattern; 11) line plating barrier metal in the formed photoresist pattern; (iii) copper via holes on the line plating barrier metal; (iv) stripping the photoresist to expose the copper via; (v) exposed copper The insulating material is stacked on the via hole. Stage II includes sub-step (vi) to remove the sacrificial carrier; thus, the obtained electricity The submount contains a copper structure having a barrier metal layer in the insulating matrix. A typical resistive metal layer has at least one of the following features: (a) The barrier metal layer is selected from the group consisting of nickel, gold, gold layer after the layer, gold layer After the nickel layer, tin, lead, tin layer lead layer, tin-lead alloy, tin-silver alloy, the barrier metal layer is selected by electroless plating, electroplating or a combination of the two; (b) the thickness of the barrier metal layer is 0. 1 micron to 5 micron. 19 200850099 A Weeping • 丄 丄 7 1 TPPO/P2855-001 Μ and Γ The wrong method contains an additional stage 添加: adding a first metal work internal substructure consisting of through holes 2 The _ medium 4 is a Wei layer film, whereby the electronic substrate established on the _ moiety structure contains a plurality of metal functional layers. Typically, stage 111: adding a first metal functional layer and a second via layer to form an inner (: substructure, the _ substructure includes a central metal work moon layer film surrounded by a via layer, the stage In comprises the following steps: (VII) adding an adhesion metal layer, such as titanium, chromium, nickel chrome, on the surface exposed by the step (V1). The exposed outer surface comprises copper surrounded by an insulating material covered by a barrier metal. (viii) adding a copper seed layer to the adhesion metal layer; (IX) adding a first functional photoresist layer on the copper seed layer, performing exposure and development to form a functional pattern; (X) in the functional pattern Adding a copper layer; (xi) stripping the first functional photoresist layer; (XII) adding a second via photoresist layer, exposing and developing to form a second via pattern; (X111) in the second via pattern Copper plating to form a second copper via layer; (xiv) stripping the second via photoresist layer; (xv) etching away the copper seed layer; (xvi) removing the attached metal layer; 20 200850099 TPPO/P2855-001 (XVI) An insulating material is stacked on the second via layer that exits. The manufacturing method of the present invention further includes a step Iv: adding a second functional layer and a third via layer, forming an internal substructure including two functional layers surrounding the central via layer, the electronic substrate established on the basis of /, 4, and Metal functional layer. Stage IV adds additional functional layer and third via layer, which may include the following steps: (11) Thinning the layered insulating material added in the flattening step (xvii), exposing step (xiii) towel addition _ the outer surface of the through-hole layer; (such as adding a metal layer on the outer surface of the violent surface and the insulating material, such as titanium, chromium, nickel chrome; (XX) adding a copper seed layer on the attached metal layer; A photoresist layer is further added to the copper seed layer to perform exposure and development to form a functional pattern. / (χχπ) Adding copper to the step (xxi) to form a second functional layer; (XX111) stripping step (xxi) t added photoresist layer; (xxiv) adding another photoresist layer, exposing, developing, forming the first [shape; ~ hole (XXV) in the third through hole pattern of copper, forming a third copper Via layer; (XXVI) stripping the other photoresist layer; (xxvii) money engraved copper Sublayer and attached metal layer; (xxviii) Layered with insulating material. 21 200850099 Blood TPPO/P2855.00! "" An insulating material that is used excessively is a fiber-reinforced resin composite. ° 匕 as a deferrable The insulating material comprises a resin selected from the group consisting of a thermoplastic tree, a solid sealing resin, and a resin having thermoplasticity and thermosetting properties. In the case of a towel, the insulating material comprises an inorganic particle filler, the insulating material being at least It has the following characteristics: (4) the inorganic hard-filled filler contains particles of ceramic or glass; (b) the particle size is on the order of micrometer; (c) the filler weight percentage is 15% to 3〇%. The insulating material is a fiber matrix composite material comprising fibers selected from the group consisting of organic fibers and glass fibers. The fibers may be chopped fibers or continuous fibers arranged in a twill or woven manner. + As a fourth or preferred embodiment, the insulating material is a prepreg comprising a fiber mat pre-impregnated with a partially cured polymeric resin. Typically, the step of stripping the layered cylindrical via structure from the sacrificial carrier layer to form a separate layered array includes the step of engraving the sacrificial carrier. And leveling the insulating material step to expose the outer surface of the outer through hole, which can be realized by the following techniques: rhyme, chemical mechanical polishing (10), dry fine, and a combination of two or more of these technologies. Multi-step process. 22 200850099 Typically, this method consists of an additional phase VI, t τ—establishing the growth functional layer and the via layer. ~' On both sides of the film As an alternative, the additional stage VI comprises the following steps. (4) Adding a _ metal layer on both sides of the flat inner substructure is selected from titanium, chromium or nickel chromium.嫔 Attachor Gold (b) Add a copper seed layer on the adhesion layer; (C) Add a photoresist layer to expose the exposed first-outer photoresist pattern; Open/Dangdi-External Functional Layer (4) - Light __ in the line plating - external functional layer; (4) stripping the first - external functional layer of the first - external photoresist pattern 曰, _ (1) adding a photoresist layer, exposure, development, forming a first external lithography谬Graph; the first layer of the spoon; (g) in the second external light __ in the line surface - the outer copper through hole (h) strips the second outer photoresist pattern; (i) etches off the copper seed layer and adheres The metal layer; (J) is stacked on the copper functional layer and the via layer exposed on the surface; (1) the insulating material is reduced and planarized until the outer surface of the via layer is exposed. Alternatively, step (4) to step (1) above are repeated _ to establish the desired additional outer layer. The finalization of the stage m may include the following steps: 23 200850099 ,··奂上九田Η ΤΡΡΟ/Ρ2855-001 (1) Adding to the outer-thick chromium and nickel-chromium of the pile-like structure; · °卩g Attaching a metal surface layer, such as titanium, (ii) adding an external copper seed layer to the externally attached metal surface layer; (iii) adding, exposing, and displaying the layer to provide a graphic structure; ((9) adding scales to the graphic structure towel Disc and copper wire; (V) strip the photoresist layer; "live copper and copper seed layer, expose (VI) add masking photoresist layer, occlusion > copper pad to provide the final metal pattern. (Vii) The exposed copper pad is made of metal in the following materials: nickel, gold, layer, and the termination layer may be selected from the group consisting of alloys thereof; lead, silver, palladium, nickel gold, tin silver

Cviii) stripping off the masking photoresist layer; (IX) removing the exposed copper seed layer, and attaching the metal layer to the turbulent path; (X) adding a solder mask layer to expose the layer. /, 九亚,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Layer; Bufangqing metal surface layer added external steel seed sound. ui) in the outer can layer field - correct (five) exposure, development of external photoresist layer 'formed graphic structure; 24 200850099 (v) in the above _ structure add force c Steel pads and wires; TPPO/P2855-001 copper pads (vi) remove the outer photoresist layer, remove the obscured copper r ···, $ and the exposed metal sounds · (viii) add solder 掭Luanchuan has a layer of soil, ^; , 4 light, developed to cover the copper wire, exposing (ix) in the silk (four) scales b learning red 7 alloy and anti-health polymeric materials. t silver, satin, nickel gold, tin silver, production = r aspects, this is the day to provide a kind of structure with an even number of ship layers by the above method. In terms of production, the present invention has been provided with a structure having a plurality of functional layers. In another aspect, the object of the present invention is to provide a substantially symmetrical structure made by the above method. [Embodiment] The present invention relates to a novel manufacturing process for fabricating an electronic substrate and a novel electronic substrate obtained by the above process. Some of the fabrication steps, such as photoresist addition, exposure, development, and subsequent removal steps are not discussed in detail here, as the views and processing flows in these steps are common knowledge, and if discussed in detail herein, This _ very cumbersome. Exactly speaking, the technology in the field 25 200850099 TPPO/P2855-001 Personnel Sb is able to make appropriate choices for the production process and materials according to parameters such as specifications, substrate complexity and components. In addition, the actual construction of the base material 'has been described'. In fact, the present invention provides a clothing method suitable for the "support structure" of the rural area. The following discussion relates to a novel and versatile method for fabricating a multilayer substrate. 'The township base towel, various conductive layers ride through the through holes of the insulating layer to form a three-dimensional stacked structure. Figure 4 is a basic flow chart of the key steps of making the substrate method of the present invention, this method Including ··· P all segments Ia—using a full-plate electroplating technique to fabricate a film containing conductive vias surrounded by an insulating material on a sacrificial carrier, or a stage ib-line electric ore branch fabricated on a sacrificial carrier containing insulation Membrane of conductive vias surrounded by materials. These two techniques and their corresponding advantages are discussed in detail in the following sections. ' Stage Π, from the sacrificial carrier layer, on top of it, adding other layers to the solid疋Remove the residual stress before it is in the multi-layer structure. In this way, the flatness of the money is obtained as the blasting method. For multiple layer structures, the surface-side layer can be The optional stage is the same as that described in stage IV. In stage V, the structure is reduced by the order of "1, and the stalk is cut into a cut, forming a flat internal substructure. Adding a variety of its structure, this process can obtain a symmetrical structure, which is shown in Fig. 5a and 5h as the schematic 5b of two such structures (1) followed by the leveling stage 7 ^ as follows. In (4) (4), the 'stage metal layer, the = film = 'add even number and 3 - 〇-3 structure, that is, there are two and three symmetry on the through hole layer in the insulating 26 200850099 TPPO/P2855-001 film. The metal functional layer. Thus, as in the example of the even-numbered symmetric structure shown in Figure 5a, the layered structure comprises two pairs of metal functional layers 38, copper pads T8, connected by copper vias 4, 34, Figure 5a The four-layer structure includes two pairs of external metal functional layers 38 and copper pads T8, which are respectively disposed on both sides of the Langzi structure located in the insulating material_scale hole, and is therefore referred to as a 2-G-2 binding structure. The towel also shows the attached metal layer 6 and copper seeds.

The layer 2' seeding structure is terminated with a terminal metal layer 98 and a solder mask 99. The fabrication process and selection process are discussed in detail below. In the example shown in the six-layer structure of FIG. 5b, the layered structure includes three pairs of metal functional layers 28 disposed on both sides of the copper via holes in the insulating film structure, such as copper pads μ, W in FIG. 5a. Both the 2+2 structure and the structure 3 in Fig. % are included in the insulating film 5, and the through holes 4 are placed in a symmetrical laminated layer. The substrate is provided with three metal functional layers on each side of the layered array, the continent, the == stacked___ _ _ _ application, that is, the same day, the following is described. 2 and the symmetrical structure shown in Fig. 5b includes paste _, brazed, 4, 34, 44, and insulating material 5, and insulating material 5 is preferably: polymer, as described below. (4) f疋 fiber reinforced a basic structure can make some changes, such as the figure 'and the through hole layer, lose, _, butterfly her 27 200850099 TPPO / P2855-001 structure as shown in Figure 15, the dog can be constructed as shown in Figure ^ The 2_b 2 and 3_1-3 structures represented by 6 and J7, respectively. In the occasion where you need even (four) but not high requirements for the threat to the young, at the stage! After π, 'F is a segment of V' can be added to the stage ίν: adding a second additional metal functional layer and a central layer, as shown in Fig. 21, the symmetric structure is shown, and the through-hole strength in the insulating film shown by the structure is more High, but it is not really symmetrical. The core of the present invention is the fabrication of a free-standing film comprising an array of vias bonded together by an insulating material. As shown in Figure 6, a specific embodiment of such a free-standing film is shown, and another variation is shown in Figure 8. This vertical film is the structural basis for all of the following structures, and the fabrication steps are also the basic steps of the following process. As shown in FIG. 12, and particularly as shown in FIG. 14, the overall process includes a copper structure in the sacrificial carrier 88, 18 and the vias 4, 14, 24, and the insulating material 5 is wound around the hole. Preferably, the insulating material is a layer of red fiber reinforced composite insulating material. After peeling off from the sacrificial carrier layer, the metal layer 28, 38, and the copper pad τ8 are added on both sides of the film. The film is transformed into an internal sub-zero 媸 % 产 产 产 产 产 产 产 产 产 产 产 产 产 产 产 产 产 产 产 产The solder mask is formed into a support structure for wafer support. To be, Saki is on its squama, if the process needs 6 and Yangge, it can also contain the line resisting layer. The resistance of the thin metal layer of the high-purity conductive layer is almost unaffected by the adhesion metal layer. The X positive body V structure 28 200850099, the upper TPPO/P2855-001 due to this layered symmetry with via _ Or the preparation process of the substantially symmetrical free-standing multilayer substrate, the outer layer is simultaneously mounted on both sides, so that the residual stress generated by the shrinkage of the polymer resin of the insulating material during the curing process tends to agree with each other, thereby achieving High flatness and improved yield, so that the substrate in the present invention can be used as a medium for Ic and printing, and provides good internal junctions for both, which are heterogeneous layers. 4. In the internal substructure of the complex · 5, then the terminal metal layer (two plus t functional layer 28 (such as the production of its needle knitting n 圏 11 not). This deformation can be surnamed native, 溥It has a complicated structure to record the metal work to add external external forks on both sides. ^~Layer 38, brazing (four) to form a more in-slope, which requires an odd number of metal layers. Situation & dream: = use even-numbered layers The process is just vacant - a metal ·: transmitting signals in the XY plane. 曰 No... and 'to avoid waste, and in order to modify the production process as much as possible, the internal structure of the her body is there = factory to f The functional layer is sandwiched by the through holes to form a sandwich structure, and the outer layer of the central metal can also be deposited with an outer layer. By this method, the functional layer 8 can have a substantially symmetrical structure of the layer 8 and the odd number of metal layers. Can be the heart of the metal in the invention, the eucalyptus she is compiled as a miscellaneous field should be 29 200850099 TPPO/P2855-001 force and by the _ music ' _ is in those cases with a sister _ structure, due to the initial layering The array film is peeled off from the sacrificial carrier layer by stretching, straightening and shrinking-reducing stress, and 镰 as an internal substructure, in which the various layers of the film are _completely structured. The outer layer is added at the same time on both sides, and this is in the __ lie force, these stresses against each other 'Sha' does not cause the substructure to bend and deform, thereby ensuring the flatness. As shown in Figure 6 tf 'the invention The core structure is comprised of an insulating material 5 The via array 4 is on the copper seed layer 2. The free-standing film la and its deformation Ib as shown in Fig. 8 are as follows, which is the basis for the establishment of various substrates in the present invention.圃/ is a schematic diagram of the production process of the free-standing membrane of Fig. 6. In order to facilitate the preparation of the spear and the intermediate structure as shown in Fig. 7(1) to Fig. 7(5)(1), as shown in the figure, block ϋΓΓ, 7 (V1U), step 7 (丨): Full-board electricity on the sacrificial carrier G to two ":: metal is steel. The thickness of the sacrificial carrier 0 is generally 75 micrometers (10): the material is generally copper or steel alloy, such as brass or bronze. :: layer; can: use the following materials: group, tungsten, chrome - layer,, after = nickel layer, gold layer, gold layer, nickel layer, tin, wrong, staggered, post-tin method to prepare gold 'the layer through the physics Vapor deposition (PVD) of Lu Houquan #人i ^ 7 (1) in the resistive metal layer using recording, gold, tantalum layer after recording layer, tin, wrong, Ming layer, tin layer, tin alloy, The town can be prepared by electroless plating or pro- or both of them. 3050050099 TPPO/P2855-001 micron to 5 microinjection. The typical thickness of the barrier metal layer is generally m. ",,

An adhesive metal layer can be added to the metal layer i of the seal, which can be used to coagulate the steel on other metals. Correction, if you choose the appropriate resistive metal ^ ' carefully, you do not need the attached metal layer. Step 7 (ii), adding a copper seed layer 2 on the barrier metal layer i, the thickness of the copper seed layer is 〇. 2 micro _ 5 micrometers, which can be subjected to physical vapor deposition, for example, after sputtering Or a combination of the two. In step 7 (out), a photoresist layer is added on the copper seed layer 2, and exposure and development are carried out to form a photon. This step is carried out by using an existing electronic substrate or a common method in the preparation process of the device. Step 7 (iv), S__W is added with a copper via 4, which is located on the copper seed layer 2. The copper through hole 4 is generally prepared by means of an electron microscope, in particular, it is called a circuit-electrical process. In step 7 (v), the photoresist layer 3 is stripped leaving the upright copper vias 4. Step 7 (VI)' superposes the insulating material 5 on the outer layer of the copper through hole 4. A thermoplastic material, __ (4), or (4) heat; ^ a gel composition, such as cis-succinimide triazine, epoxy resin, polyimide, and a mixture of these materials. The insulating material 5 as the main material of the polyimide is preferably capable of adding an inorganic impurity filler, which is usually a shout or glass granule, and the particle size is on the order of micrometers. Specifically, the particle A is as small as G. 5 micro _ 5 micrometers; In such a polymeric matrix material, the particulate filler has a weight percentage of 15% to 3% by weight. In a preferred embodiment, the insulating material 5 is a fiber matrix composite material, and the package 2008 200850099 TPPO/P2855-001 contains organic fibers such as polyimide fibers (fiber B) or glass fibers. These fibers may be short fibers or continuous fibers, arranged in a diagonal interlacing manner or in a woven pattern. The pre-impregnated body is arranged by a diagonal interlacing method in which a partially hardened polymeric resin is pre-impregnated or as a cloth weave. In most preferred embodiments, the polymer matrix uses at least two woven fibers to pre-crush the material. The matrix composite of the pre-impregnated material contains a ceramic filler. Epoxy materials and polyamide matrix woven prepreg materials were supplied by Rancho c__, Ca, Arlon & These prepreg materials are sub-structured by sub-structures. The continuous fibers that penetrate the insulating layer provide additional strength and stiffness, thereby making the overall structure thinner and more uniform. Step 7 (vil), through the rainbow art to remove the sacrificial carrier 0 at 7 (the scratch-resistant metal layer J made in 〇 as the residual stop layer. The sacrificial carrier - generally copper or copper alloy, through f according to the barrier metal layer丨 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 选择 ' 选择 选择 选择 选择 选择 选择 选择 , , , The side process is completed at a higher temperature. Step 7 (viii), removing the metal barrier, such as the U metal ruthenium layer (4), can be mixed by the mixture of (10) and red 'typically formulated as CF4 and red ratio i ·· i To 3:; Other barrier metals can be turned over by the ribs known to him. 4. The double shape of the free-standing membrane 1 shown in Fig. (Ib - as shown in Figure 4). 1& The free-standing film Ib 32 200850099 TPPO/P2855-001 comprises a copper through hole 4' surrounded by an insulating material 5', which is slightly modified. The copper through holes 4 are provided on the thin metal layer 1 of the barrier layer. Finally, the resistive metal layer is placed in the substrate of the present invention. "The optional structure Ib shown in Figure 8 can be prepared by the preparatory work flow in the flow chart shown in Figure 9. The intermediate steps are shown in Figures 9(1) to 9(vi). Referring to the steps and structures shown in Figures 9 and 9 (〇 to 9(vi), as shown in Figure 9(1), [coating, exposing and developing light on the sacrificial carrier 0 Engraved pattern 3. As shown in Figure 9 (H), = _ metal layer 添加 is added to the photoresist pattern. As shown in Figure 9 (out), online: 峨 metal ' __ hole 4, typically, The use of electric ore is the same as that described in Figure 7 above, and only necessary is applied. As shown in Fig. 9 (5), the photoresist pattern 3 is peeled off, and then the exposed copper is shown in the exposed copper. 9(v). Finally, as shown in Fig.), the sacrificial carrier 去除 is removed. In these steps, , and f are made ~ Μ for the % edge material 4, the barrier metal i is corrected ▲ fine _ and shown in Figure 7. Ia _ like, only the necessary art, to I:::: Wang Ban, (as shown in Figure η or circuit plating (Figure 9) in the invention of the kind of reading! ^ is an odd or even number of metal functions Layer, this, the sample day = butterfly __ tree is different. From the Mao month (10) phase 疋 - a general and corresponding structure. ^ 不同 不同 不同 不同 不同 不同 不同 不同 不同 不同 不同 不同 不同 不同 不同 不同 不同 不同 不同Metal-added functional layer 33 200850099 28 Get Ίυ" and hold, 丄城ΤΡΡΟ / Ρ 2855-00ί plus metal work place. "Funding - Stage V as shown in Figure 4. If you add the energy side, continue to add both sides at the same time If the hole 34 and the other phase are not shown in Fig. 5a, it is possible to obtain "2_χHelmet# to make the internal sub____ more_, both of which are on the side of the lb. These are some different internal ^-film 1a or each test The structure is described below, as shown in Fig. 10, the steps of adding the external functional layer and the via layer at the same time are: 2 'Smoke G(1)' is added on both sides of the flat internal substructure x (4) 曰6 The adhesion metal layer 6 contributes to copper adhesion, especially when it is grayed on the insulating material 5. The adhesion metal layer 6 is usually made of the following materials: chin, ruthenium or nickel chrome. In step 10 (ϋ), a copper seed layer is added after the metal layer 6 is attached. Step 10 (lii), followed by the addition of a photoresist pattern 7, exposure and development. Step 1 〇 π), the copper functional layer 28 is lined up in the above-mentioned photoresist pattern. Step ι (7), the photoresist layer 7 is peeled off. In step 10 (Vi), the second photoresist layer 33 is added and exposed and developed. In step 10 (vii), copper vias 34 are electroplated in the photoresist layer. Step 仞 (viii), the second photoresist layer 33 is peeled off. Step (ix), the copper seed layer and the attached metal layer are outlined. It is worth noting that the thickness of the seed layer is usually much smaller than that of the upper layer plating. It is difficult to clearly describe this actual contrast relationship in the cross-sectional diagram of the ® 1〇(1)(xi). Step 1 〇 (χ), a layer of insulating material 5 is added on both sides of the metal functional layer 28 and the via layer 34, and the entire stack continues to be thicker. 2008 200899 TPPO/P2855-001 Thick. Step Η) (X1) The insulating material layer 5 is thinned and flattened until the outer edge of the through hole 34 is exposed. By adding other external functional layers on both sides of the growth structure, as shown in Figure 5b, a more complex structure can be formed, whereby steps 10(1) to 1 can be repeated as needed for the final structure. 〇 (6), making more through-hole layers and conductive functional layers. ^ Substrate termination of the sub-P substructure and outer structure. Figure 11 shows the finalization process, and Figure 11 (丨)丨 峨 α u to 11 ω shows the steps of the finalization process. =, and Figure U(1) to u(1), the final stage grabs the '匕$ following steps··Step 1 ·), adds force on the layer, attaches the metal layer::::Stack: _ Y's external layer continues to add external copper Photolithography _ T7,11 (111) was added to the seed copper seed layer, and the outermost W Τ 7 'opposite _ layer Τ 7 was performed to obtain a photoresist pattern structure. Step ^ (four) and the wire. Step 2) Add a copper tan / is 11 (ν) in the graphic structure, and strip off the light_layer 17. Step 1Uvi), ¥Add the photoresist layer 97, perform the n r ... shirt, and smash the copper plate T8. Step η ((6)' in the city of the copper pad μ line Liu = metal layer 98 can be nickel, gold, (10) _ mega-terminal metal alloy. Step u (· Υ, "Meng, tin, wrong, silver, Or the upper layer 6. Step η η (1Χ), etch away the copper seed layer 2 and the externally attached metal pass (1), add the itch mask 99, expose and develop, and select 35 200850099 TPPO/P2855-001 to expose the underside The copper pad T8 and the terminal metal layer % are thus obtained on the basis of the film la by performing steps ι〇(1)(4)(6) twice, and then performing step 11(i) to U°-' can be obtained as shown in Fig. 5(b) 2-2-2 structure shown. In the finalization step, you can choose not to use the material and the fabrication process. One possible termination step involves adding a conductor layer to the outer surface (above and below) of the stack. This termination step includes The following sub-steps: (4) thinning the base insulation on both sides, can be exposed by mechanical grinding, or chemical mechanical (C), or a combination of several methods to expose the outer surface of the copper through hole, (8) Adding an external 瞒 to the outer surface of the stacked structure (6) on the externally attached metal layer followed by 'adding an outer layer; (4) adding lithography on the outermost layer of the layer; () the photoresist layer into the light, developing, to obtain the light _ structure; (1) Adding copper pads and wires to the lithography kick-off; (4) removing the light layer, leaving the copper layer, the sub-35 chip and the Wei; (h) the _ sub-layer of the butterfly dew and the exposed   layer, (〇 add a solder mask, exposure, development of the exposed pad. (1) _ chemical _ way, in the silk (four) turntable; ^ final ^ fij layer, the terminal screen can be left from the left. 曰疋 nickel, Meng, or Nickel layer after gold layer, or gold layer after nickel layer, 钖 'wrong, silver '姊 alloy of these metals and anti-county compound materials. 1 ... 'and 'the structure of 5a and 5b has been optimized The electronic design of the 'substrate' in the brothers needs to reduce the thickness of the stacked array layers (the internal substructures of Figures 5a and 5b) as much as possible. Because these internal substructures 36 200850099 TPPO/P2855-001 natural brittleness 'this would jeopardize The yield of the step process discussed in detail above. There may be some changes in the process described above. This solves the above problems, resulting in some differences in structure. The example shown in FIG. 12 is a cross-sectional schematic view of a "2-0-2" type symmetrical, unsupported structure including a barrier metal layer 1, by referring to FIG. The deformation shown is the same as the one shown in Fig. 11. The deformed structure in Fig. 12 is similar to the structure of Fig. 1, but the deformed structure includes the barrier metal layer 1. The structure is shown in Fig. 4. The macro stages Ib, n, v, viwn|m are shown. As shown in Figures 13 and 13(1) to 13 (xxvii), the processing flow for forming a symmetrical, coreless support structure as shown in Fig. 12 is first shown. Step 13 U) V1 coats the structure of the film 1a, these steps and Figure 9 (〇 to 9 (in the process of making the film 8 - sample, Jianshe ^; J9 (V1), for step 13 (v., Γ The required changes. Step 13 (Chuan) The structure formed in step 13 (V1) is thinned and advanced. Steps and @4 mid-level shots pass through the internal sub-3 (:, the middle structure is as shown in the figure ^ U〇 - that is, the order in Figure 4 to J 1〇 'w' 'By the structure shown in Fig. (10), these intermediate structures correspond to the middle shown in the figure XXV111), through the other structure 13 (mail) = called then (1) fairy (1), (xxviO get the deformation of the structure 37 200850099 TPPO /P2855-001 "2-0-2" structure. Figure 12 is similar to Figure 5a, but it is prepared by a line plating process to form a barrier metal layer, forming a separate via film (as shown in Figure 9 (vi)), The barrier metal layer is retained and integrated with the final structure. Since the barrier metal layer is conductive, in many applications, the introduction of the barrier metal layer is not problematic, and its introduction is for reducing the remaining The stress is very useful. Ffi 14 is a schematic diagram of the cross section of the "3-〇-3", symmetrical, non-support structure, the fabrication process of the structure is shown in Figure 13, and the process in Figure 13 includes the flow 9 , Flow 10, repeat steps 13 (viii) through 13 (χνΗ), followed by Flow 1 Figure 14a It is shown as a preparation flow chart for the structure shown in Fig. 14. The structure is made by the steps of (4) and U for the film shown in Fig. 6. The pin is shown as a 2+2 type structure, and the internal substructure includes Center metal work: ',, two-touch layer 4, 14, the fabric manufacturing process of the structure is shown in Figure 15a to the layer 1 to add copper seed genus. Add the first _ photoresist pattern ^, 111 on the sub-layer 2) In the step (iv), the through hole pattern is formed by the ninth, " shirt. Reading or chemical method in the _ glue _3 _, shape 38 200850099 > TPPO/P2855-001 copper through hole 4. Step (v), stripping the first photoresist pattern 3, leaving the upright copper via 4. Step (vi), stacking the insulating material 5 on the copper via. Step (vii), removing the 2 sacrificial carrier Step (viii), removing the barrier metals. The structure obtained by the above steps is the same as the structure Ia shown in FIG. 6, and the flow is consistent with the method of FIG. 7, except that necessary modifications are made thereto. Before the stage v shown, the fine insulating material exposes the copper work, and the surface exposed by the removal of the resist metal layer 1 is added. The hole layer 14 indicated by gold establishes a substructure structure χ (as shown in Fig. 10(1) to 10(6): the tea is shown in Fig. 15(a), and the preparation process is as follows: the step of engraving the layer 7, the outer edge of the enamel, the function of adding light to the light (1) forms a functional pattern. Step (x), in the functional pattern, ... (6) 'peel the second photoresist layer. Step (xii), open the second layer of adhesive layer 13 'covers the gap of the copper functional layer 8, for exposure, development, internal force The second pass on the Saki 8 _. Step (xiii), in the pass / outer steel to form the second copper through hole layer 14 〇 step (xi) 剞 back to the glue layer 13, miscellaneous _ power ride 8 « two sides = Photolithographic copper seed layer 2. The cow...·14° step (xv) is etched on the via layer 14. :: Two _5 stacked to the functional layer 8 and the second copper continued preparation process = (4) lang, flat, for the first touch 1 touch, in _ (four) there are countable surface layer __ partial structure. Figure 16 shows a 2 small 2 39 200850099 structure based on the internal substructure shown in Figure 15 which is added by two rows of via layers 34 44 1 by pressing ΤΡΡ〇/Ρ2855.〇〇1 Step 'on both sides of the internal substructure as shown in Fig. 17,; 隹-π- shows the necessary energy layer to form a 3+3 structure, which is the sub-step of Figure 16 The outer metal functional layer 38 and the via layer 44 are further added to the side of the inner sub-name structure. The odd-numbered symmetric internal branch of the electro-acceptivity through-hole of the green shame line is "", 18 read through-holes (such as step 1δ (, Chuan Shang line 9 (1) to 9 (vw (V1) not)' steps Corresponding to the step & J 乍 necessary modifications. By the following way, only build on the mTh :- side, step (V11) 'add the attached metal =: sacrificial carrier 0. Step f · η to the copper cattle that are off... 1) 5 Add copper seed sound 2 on the attached metal layer 6. Step "(5), add a second photoresist layer: layer 2 step (X), add copper to work ^ open" into a functional graph. Forming the functional layer 8. Step (5), stripping the spine-first layer 7. Step (X11), adding = shadow, forming a second via hole _. Exposing the first sub-display copper, forming the first handle 111, in the second via In the figure, the line electricity = brother - copper through hole layer 14. Step (X1V), stripping step (5), Saki copper seed layer 2 and _ wide stack of insulating material 5 to the internal support structure, two =:, stack step:: layer. Based on the odd-numbered layer shown in circle 18 containing the anti-metal layer _ _ 200850099 material t line b, ten whole, exposed the outer edge of the through hole 4, 14, (such as the stage V, , ) 'Into the step to increase the external functional layer 28 and the via layer private, Figure 16 can be modified as necessary. Figure 20 is shown in Figure _ shows the inclusion of the metal layer 1, the odd layer of the internal performance of the knot System basis, ^ two shoulders _, remove the insulating material 5, flat, fiber through holes 4,, 14 read (as shown in phase V), repeat steps 1 〇, step-by-step increase external external functional layer 28'38 And the via layer _, the necessary modification of the picture is that the 5a and 5b are not 2-0-2 and 3-0-3 even layer structure, the film ia and Ib in Figure 6 and Figure 8 may be very fragile 'In some specific application areas, due to design considerations, it is necessary to minimize the structure of the sub-organization, the sound, the former, the mouth, the child and the court are in the stage of Figure 4 and <stomach> In this way, although the symmetrical structure is obtained by adding the functional layer b of the insulating film la shown in FIG. 6 and the insulating film φ, the sky, and the square nun shown in FIG. The characteristics, but because of the need to materialize, endurance and size in the use of carvings, these processes need to be revised, sacrificing absolute _ For easy fabrication and high yield. The thickness of the via 4, and the selected insulating material 5 cannot guarantee that the layer Ia or the layered structure Ib after the insulating material 5 is ground to expose the copper via 4 (4) With sufficient integrity, it is necessary to have a thicker structure on the side of the membrane (four), which is used to remove excess insulating material 5 such as copper through hole 4 or copper through hole 41 200850099 ^ TPPO/P2855-001 hole 4, before The under-polished insulating layer covers the copper via 4 or the steel via to form a reinforcing layer. Therefore, when the structure requires an even number of metal functional layers, and for electrical considerations, a low-thickness film is required and productivity is increased, the stage π enters the stage (1) (as shown in Fig. 15) to form a first-internal metal functional layer. 8 and the second via layer (4) stage iv 'adds a second metal functional layer 18 and a third via layer thereon, thereby forming a semi-symmetric inner layer containing two metal functional layers 8, 18 After the thinning and flattening of the step (4), more external metal functional layers 28, 38 and external via layers %, 44 can be constructed by the process in FIG. Then, the finalization process shown in Figure u is performed. Shown in Fig. 21 is a substantially symmetrical inner "-2-" substructure constructed on the basis of 臈Ia shown in Fig. 6. A substantially symmetrical internal "-2-" substructure can be combined with a 4-layer and a 6-layer metal work layer to form a 1-2-1 and "2-2-2" structures, respectively, which are substantially identical to Figure 5a. The "2_0-2" and "3_〇_3" structures in Fig. 5b are identical in construction, except that the internal metal functional layers 8, 18 added one at a time are different. As shown in Fig. 21a and Figs. 21b(1) to 21b(xxviii), for the fabrication flow of the structure shown in Fig. 21, steps 21(1) to 21(viii), a film la as shown in Fig. 6 is produced (in Fig. 4). Stage I and stage π), then combine this structure into a semi-symmetric internal structure in Figure 21 by stage ΠΙ (as shown in Figure 4 t). These steps 42 200850099 TPPO/P2855-001 are here (ix) To step (xvi): the first metal functional layer 8 and the first via layer 14 j are added to stack the edge material layer 5. Step ((10)): thinning and flattening the end of the first through-hole layer u. Then enter the stage P: on the basis of adding the second metal functional layer 丨8 and the third through-hole layer 24, corresponding to step 21 to step (xxvii), Saki is (four) 21 km), the whole commission is thinned and leveled (corresponding to Fig. 4 Stage v). ^Building fine: (stage 1, stage 11, ie step (1) to step (vi ii)) After obtaining the film la in Fig. 6, step r ·, 乂 (IX), adding a second photoresist layer 7, exposure and development, shape success _. In step (1), the copper function is made in the function_8. Step (5)' peels off the second photoresist layer 7. Step (xii), adding a third photonic layer "3", covering the gap of the copper functional layer 8, exposing and developing, forming a through-hole pattern on the functional layer. Step Chu—UU) The copper through-hole layer 14 is formed by electroplating steel in the pattern of the through-hole pattern. In step (xiv), the third photoresist layer 13, the dew layer 8 and the via layer 14 are stripped. Step (xv), the copper seed layer 2 is removed. Step (= Stacking the insulating material on the surface of the exposed copper functional layer 8 and the copper via layer 屛〇 step (xvii), thinning and leveling the insulating material to expose the last layer 5 of the copper via layer. III. And 'the above step (xix), deposit another layer of metal layer 6 (step (xvii deposit another layer of the layer 2, step (xx), add the fourth layer of glue ^ after the exposure) Developing, forming a second functional pattern. Step (xxi), making a second copper functional layer 18 in the process of intrusion. Step (xxi i ), stripping the fourth photolithography waist ^ ^ 43 200850099 TPPO / P2855-001 Step (5) ii And adding a fifth photoresist layer 23 covering the gap in the second functional layer i8, exposing and developing, forming a third via pattern on the second copper functional layer 18. Step Uxiv) 'in the third via hole The copper through hole sound is formed in the pattern of the pattern _ line. Step (xxv): peeling off the fifth photoresist layer 23 to expose the second copper functional layer π and the via layer 24. Step (xxvi) 'Thin the through hole Adhesion metal layer 6 and copper seed layer 2 between layers %. Step (xxvii), at the exposed second copper functional layer The surface of the via layer 24 is stacked with an insulating material layer 5, which is a stage. The thicker substructure having two Wei layers is thinned and leveled in the step scarf: generally, grinding can be used: by deposition Assembly of the outer layer transition stage. 芩 图 Figure 22 ' can also be assembled on the basis of the line money film shown in Figure 8: the semi-symmetric internal substructure of the structure shown in Figure 21. The production of the internal substructure The flow is the same as that of Fig. 21 & the only starting point is the substructure in Fig. 8 rather than the substructure in Fig. 6. Fig. 22b (1) to Fig. 22b (xxviii) are generated corresponding to the steps in Fig. 22a. Intermediate structure. Corresponding to the stage! 'Figure 22b (1) to Figure (7) shows the fabrication of the film. Corresponding to the stage „, Figure 22b (vi) shows the sacrifice of the body layer, resulting in Figure _ vertical Membrane lb. In Fig. 22b (vii) touch 22b (xvi) the single layer substructure shown in Fig. 18. These steps correspond to stage III in the entire flow shown in Fig. 4. In stage IV, the single layer structure The assembly process continues: the bifunctional layer structure shown in Fig. 22 is formed, that is, the step (χνϋ) to (like hi) As shown, the second functional layer 8 and the second via layer i4 are added to the freestanding film ib to obtain 44 200850099 f , . 0 TPPO/P2855-001 Jiandi two work: and the third through hole layer 24. In V, step (xviil), the bifunctional layer is thinned, and the flattened + middle ' can also be added in two layers to form (4) and the details of the (4), 2-structured lion shown in Fig. 24 Referring to Fig. 4 (4) to Fig. 21, the graph and the semi-symmetric structure shown in Fig. 24 are constructed on the basis of the non-corporate structure of Fig. 21. ® 23 and Figure 24 are cross-sectional schematic views of the structure and Figure (4)

The ΓΙ structure and the 3 winter 3 structure are similar, and they only make the necessary changes. The benevolence is not really symmetrical, because its substructure is in the process of «the process is an asymmetrical form. However, since the outer functional layers are simultaneously laminated, they have similar thicknesses and process conditions, and the resulting base material is less susceptible to buckling. - Similarly, on the basis of the (4) and the substructure, the corresponding semi-symmetric structures of the figure & and the figure % are constructed, which are semi-symmetric 1-2-b 2 similar to the structure shown in Fig. 23 and Fig. 24. -2-2 support structure, but it contains the line electric ore barrier metal layer 1 in the first stage, 'the miscellaneous retaining metal remains in the last structure, by comparing the structure shown in Fig. 12 and Fig. 14, it is obvious The difference between the two production processes. As noted above, the 'different multilayer substrates comprise optional conductive layers 8, 18, 28, continents, copper pad 8 and the like which are highly versatile and serve as conductive paths separated by a peripheral material 5. It is anticipated that these conductive layers include resistors, in-layer capacitors, inductors, and the like. In general, a high resistance material is selected as the insulating material 5, which should have a suitable thickness and dielectric constant to match the capacitance and inductance values required by the substrate designer. 45 200850099 TPPO/P2855-001 Therefore, those skilled in the art can speculate that the date and time of this issue are limited to the ones here, and that she can make various reductions and deformations according to this X month, but the matter changes. And modifications are intended to be covered by the scope of the appended claims. ... in the claims, the vocabulary "includes," and its variants "includes," "includes," and similar bribes are extracted from components or methods, and ants generally do not exclude other components and methods. 46 200850099 r _ , TPPO/P2855-001 [Simple Description of the Drawings] In order to better understand the present invention, how to implement it will be explained. The following will describe the drawings in the manner of the examples. In detail, the present invention is provided by a method which is considered to be the most practical and easy to understand. In this point, there is no A more specific structural description that is necessary for a basic understanding of the present invention. Those skilled in the art can understand and implement the several lion styles of the present invention in conjunction with the drawings and the accompanying drawings. And the cross-section of the stack is only a schematic diagram and does not describe the end product of the show, and does not specifically describe the conduction characteristics of each layer. j In the drawing: Figure 1 is the horizontal of the BGA package structure of the wire-bonding IC in the current Cross-sectional schematic 2 is a cross-sectional view of a prior art inverted BGA sealing structure. FIG. 2 is a cross-sectional view of the 峨 面 继 继 继 继 继 继 4 4 4 4 4 4 4 4 制作 制作 制作 制作The basic flow chart of the manufacturing process macro stage; line) and optional Fig. 5a is the cross section of the first paste 2-0-2 corresponding to the present invention for her core support structure. 200850099 TPPO/P2855-001 not intended, 5b is a schematic view of a functional layer corresponding to each side of the second through hole of the present invention having two distributions in the insulating film; a cross section of the '3' symmetric coreless support structure; A cross-sectional view of a novel type of through-hole as an embodiment of various supporting structures; soil 4々, '巴, 彖, and medium independent FIG. 7 is a production step diagram for making a heave hun shown in FIG. 6; 7 (i) is a schematic view of the intermediate production step prepared by the method of Fig. 7; the cross section of Fig. 7(ii) is a schematic diagram of the middle surface shown in Fig. 7; The cross-sectional view 7 (ili) of the intermediate structure is a schematic cross-sectional view of the intermediate step shown in Fig. 7; The transverse plane: __, the cross-sectional view of the intermediate structure obtained in the fabrication step 7 (V) is a cross-sectional schematic view of the intermediate structure obtained by the intermediate fabrication step shown in Fig. 7; Fig. 7 (vi) is from Fig. 7 Schematic diagram of the intermediate production step shown in the figure; 〖The cross section of the rib figure of the obtained towel structure is shown in the middle of the cross-section 48 200850099 Circle 7 (Wii) is the middle section shown in Figure 7 not * Intention, TPPO/P2855-001 Manufacturing steps The cross-sectional view of the obtained intermediate structure is a cross-sectional view of the variant of the free-standing crucible shown in Fig. 6; : r ::::::::: cross-sectional schematic view, · cross-section of the intermediate structure produced by the cut-off 9Gi) is a schematic diagram of the step of making the middle according to the drawing shown in Fig. 9; a schematic diagram of the cross section of the middle joint produced; Fig. 9 (lv) is not intended to make the step according to the middle shown in Fig. 9; the face = (,) is as shown in Fig. 9. Figure 9 (v〇 is a schematic diagram of the intermediate fabrication step shown in Figure 9; cross-sectional through hole of the intermediate structure made by the cross-sectional structure of the intermediate structure of the transversely fabricated structure = The domain structure of his _ substructure is added to both sides of the hole layer and the functional layer to form a basic symmetrical structure Art flow diagram; Figure i (i) is a schematic diagram of the intermediate structure fabricated using the steps shown in Figure 10; Figure 1 〇 (ii) is a schematic diagram of the intermediate structure fabricated using the steps shown in Figure 1; Figure 10 ( Ill) is a schematic diagram of the intermediate structure made using the steps shown in Fig. 1G. 49 200850099 TPPO/P2855-001; Fig. 10(iv) is a schematic view of the intermediate structure produced by the steps shown in Fig. 10; Fig. 10(vi) is a schematic view showing an intermediate structure produced by the steps shown in Fig. 10; Fig. 10 (vii) is a step of using the steps shown in Fig. 10. Schematic diagram of the intermediate structure, Fig. 10 (viii) is a schematic view of the intermediate structure fabricated by the steps shown in Fig. 10, and Fig. 10 (ix) is a schematic view of the intermediate structure fabricated by the procedure shown in Fig. 10; Fig. 10 (x) Fig. 10(xi) is a schematic view showing an intermediate structure fabricated by the steps shown in Fig. 10; Fig. 11 is a view showing the preparation of the structure shown in Fig. 10 (xi) Flowchart; Figure 11 (i) is the intermediate knot made using the steps shown in Figure 11. Figure 11 (ii) is a schematic view of the intermediate structure fabricated using the steps shown in Figure 11; Figure 11 (iii) is a schematic view of the intermediate structure fabricated using the steps shown in Figure 11; Figure 11 (iv) is the use of Figure 11 Schematic diagram of the intermediate structure produced by the steps shown; Figure 11 (v) is a schematic view of the intermediate structure fabricated using the steps shown in Figure 11; Figure 11 (vi) is a schematic view of the intermediate structure fabricated using the steps shown in Figure 11; Figure 11 (vii) is a schematic view of the intermediate structure produced by the procedure shown in Fig. 11; Fig. 11 (viii) is a schematic view of the intermediate structure fabricated by the procedure shown in Fig. 11; Fig. 11 (ix) is a process produced by the procedure shown in Fig. Schematic diagram of the intermediate structure; 50 200850099 TPPO/P2855-001 Figure 11 (X) is a schematic diagram of the intermediate structure made by the steps shown in Figure 11; Figure 12 is a diagram of the internal operation by applying the steps shown in Figure 10 to Figure 8 A cross-sectional view of a "2-0-2" symmetric coreless support structure of a barrier metal layer formed by the illustrated deformed film; FIG. 13 is a flow chart of the preparation of the "2-0-2" structure shown in FIG. Figure 13 (i) shows the intermediate knot made in the corresponding step shown in Figure 13. Figure 13 (ii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Figure 13; Figure 13 (iii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Figure 13; Figure 13 (iv) is Figure 13 A schematic view of the intermediate structure produced by the corresponding steps; Fig. 13 (v) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 13; Fig. 13 (vi) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 13; (vii) is a schematic view of the intermediate structure made for the corresponding steps shown in Fig. 13; Fig. 13 (viii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 13; Fig. 13 (ix) is a corresponding step of the process shown in Fig. 13. Figure 13 (X) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 13; Figure 13 (xi) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 13; Figure 13 (xii) is a diagram 13 is a schematic view of the intermediate structure produced by the corresponding steps; FIG. 13 (xiii) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 13; FIG. 13 (xiv) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. Figure 13 (xv) is the corresponding step shown in Figure 13. Schematic diagram of the intermediate structure fabricated in FIG. 13; FIG. 13 (xvi) is a schematic diagram of the intermediate structure produced by the corresponding steps shown in FIG. 13; 51 200850099 TPPO/P2855-001 FIG. 13 (xvii) is an intermediate structure made by the corresponding steps shown in FIG. Figure 13 (xviU) is a schematic diagram of the intermediate structure made by the corresponding steps shown in Figure 13, Figure 13 (xix) is a schematic diagram of the intermediate structure made by the corresponding steps shown in Figure 13; Figure 13 (XX) is Figure 13 A schematic view of the intermediate structure produced by the corresponding steps; Fig. 13 (xxi) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 13; Fig. 13 (xxii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 13; (xxiii) a sound and diagram of the intermediate structure produced for the corresponding steps shown in Fig. 13; ^ Fig. 13 (xxiv) is a schematic diagram of the intermediate structure produced by the corresponding steps shown in Fig. 13. Fig. 13 (χχν) is shown in Fig. 13. Schematic diagram of the intermediate structure produced by the corresponding steps (Fig. UUxvi) is a schematic diagram of the intermediate structure produced by the corresponding steps shown in Fig. 13. Fig. 3 (xxvii) is a sound diagram of the intermediate structure produced by the corresponding steps shown in Fig. 13; . . . Figure 14 shows the inside with one The "3-G-3" symmetric coreless structure of the barrier metal layer formed by applying the steps shown in the figure to the deformed crucible of Fig. 8: a schematic sectional view; n Fig. 14a is a flow chart for preparing the structure shown in Fig. 14; 15 is a schematic diagram of an odd-numbered chip structure formed on a through hole in the insulating film shown in FIG. 6; 3 #图图 is to convert the film ia shown in FIG. 6 into an odd inner layer structure as shown in FIG. 52 200850099 TPPO Flow chart of preparation of /P2855-001; Fig. 15 (Fig. 15 is a schematic view showing the intermediate structure produced by the corresponding steps shown in Fig. 15a; Fig. 15(ii) is a schematic view showing the intermediate structure produced by the corresponding steps shown in Fig. 15a; Fig. 15 (iii) Fig. 15(iv) is a schematic view of the intermediate structure made by the corresponding step shown in Fig. 15a; Fig. 15(v) is the intermediate structure made by the corresponding step shown in Fig. 15a. Figure 15 (vi) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 15a; Figure 15 (vii) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 15a; Figure 15 (viii) is Figure 15a Schematic diagram showing the intermediate structure produced by the corresponding steps; 15(ix) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 15a; Fig. 15 (X) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 15a; Fig. 15 (xi) is the corresponding step shown in Fig. 15a Schematic diagram of the intermediate structure; Fig. 15 (xii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 15a; Fig. 15 (xiii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 15a; Fig. 15 (xiv) is Figure 15a is a schematic view of the intermediate structure produced by the corresponding steps; Figure 15 (xv) is a schematic view of the intermediate structure produced by the corresponding steps shown in Figure 15a; Figure 15 (xvi) is a schematic view of the intermediate structure produced by the corresponding steps shown in Figure 15a Figure 15 (xvii) is a schematic diagram of the intermediate structure made by the corresponding steps shown in Figure 15a, 53 200850099 TPPO/P2855-001 Figure 16 is a schematic diagram of the 2-1-2 structure constructed on the internal substructure shown in Figure 15; Figure 17 is a schematic view showing the structure of the 3-1-3 structure constructed on the internal sub-structure shown in Figure 15; Figure 18 is a schematic view showing the structure of the odd-numbered layer-symmetric internal support sub-structure formed on the through-hole in the insulating film shown in Figure 8; 18a is to convert the film lb shown in FIG. 6 into FIG. FIG. 18(i) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 18a; FIG. 18(ii) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 18a; (iii) Schematic diagram of the intermediate structure made for the corresponding steps shown in Fig. 18a; Fig. 18(iv) is a schematic view of the intermediate structure produced by the corresponding steps shown in Fig. 18a; Fig. 18(v) is made for the corresponding steps shown in Fig. 18a Figure 18(vi) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 18a; Figure 18(vii) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 18a; Figure 18 (viii) is a diagram 18a is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 18(b) is a schematic view of the intermediate structure produced by the corresponding steps shown in FIG. 18a; FIG. 18(X) is a schematic view of the intermediate structure fabricated by the corresponding steps shown in FIG. 18a; Figure 18 (xi) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 18a; Figure 18 (xii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Figure 18a; 54 200850099

Figure 18 (xiii) ^ TPPO/P2855-001 Schematic diagram of the intermediate structure made by the corresponding steps shown in the schematic diagram of the intermediate structure made in the corresponding step shown in Fig. 18a; schematic diagram of the intermediate structure produced by the corresponding step shown in the figure Figure 18 (xV1) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 18a; Figure 18 (χνι〇 is an illustration of the intermediate structure made by the corresponding steps shown in Figure 18a)

Figure 19 is a schematic view of the 2+2 structure of the internal substructure shown in Figure 18; (4) Schematic diagram of the shaft sub-junction _3+3 of the scale diagram of Figure 18; Figure 21 is a diagram of the insulating film formed in Figure 6 Two functions of each side of the through hole: a schematic view of the semi-pair structure "_2_"; Fig. 21a is a system for forming the film shown in Fig. 6 into the semi-symmetric internal structure shown in Fig. 21.

FIG. 21b(i) is a schematic diagram of the intermediate structure produced by the corresponding steps shown in FIG. 21a; ° b(ii) is a schematic diagram of the intermediate structure produced by the corresponding steps shown in FIG. 21a; FIG. 21b (iii) is Figure 21b is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 21a, and Figure 2b(v) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 21a; 21b(vi) is a schematic diagram of the intermediate structure made by the corresponding steps shown in FIG. 2ia; FIG. 21b (vii) is a schematic diagram of the intermediate structure made by the corresponding steps shown in FIG. 2A. 200850099 TPPO/P2855-001 diagram, FIG. 21b (viii) Fig. 21b(ix) is a schematic view of the intermediate structure made by the corresponding step shown in Fig. 21a; Fig. 21b(x) is the intermediate structure made by the corresponding step shown in Fig. 21a. Figure 21b (xi) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 21a; Figure 21b (xii) is a schematic view of the intermediate structure made by the corresponding steps shown in Figure 21a; Figure 21b (xiii) is Figure 21a The intermediate knot made by the corresponding step Figure 21b (xiv) is a schematic diagram of the intermediate structure made by the corresponding steps shown in Figure 21a; Figure 21b (xv) is a schematic diagram of the intermediate structure made by the corresponding steps shown in Figure 21a; Figure 21b (xvi) is Figure 21a A schematic diagram showing the intermediate structure produced by the corresponding step; FIG. 21b (xvii) is a schematic view of the intermediate structure produced by the corresponding step shown in FIG. 21a; FIG. 21b (xviii) is a schematic view of the intermediate structure produced by the corresponding step shown in FIG. 21a; 21b (xix) is a schematic diagram of the intermediate structure produced by the corresponding steps shown in Fig. 21a; 56 TPPO/P2855-001 200850099 Fig. 21b (χχ) is a schematic diagram of the intermediate structure made by the corresponding steps shown in Fig. 21a; Fig. 21b (xxi) is Figure 21b is a schematic view of the intermediate structure produced by the corresponding steps; Figure 21b (xxii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Figure 21a, and Figure 21b (xxiii) is a schematic view of the intermediate structure produced by the corresponding steps shown in Figure 21a. Figure 21b (xxiv) is a schematic diagram of the intermediate structure made by the corresponding steps shown in Figure 21a; Figure 21b (xxv) is a schematic diagram 21b (xxvi) of the intermediate structure made for the corresponding step shown in Figure 21a, corresponding to Figure 21a Schematic diagram of the intermediate structure of the fabrication, FIG. 21b (xxvii) is a schematic diagram of the intermediate structure produced by the corresponding steps shown in FIG. 21a, and FIG. 22 is intended to show that the intermediate structure of 21b (xxviii) is the corresponding step shown in FIG. 21a. Corresponding to the semi-symmetric internal structure of the semi-symmetric internal structure "-2-," shown in Fig. 21, which is constructed by the circuit plating film shown in Fig. 8. The drawing 22a is the film shown in Fig. 8. Figure 25b shows the semi-symmetric internal A flow chart, structure 57 200850099 TPPO/P2855-001 Figure 22b (i) is the schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (ii) is the corresponding Figure 22a Figure 22b (iii) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (iv) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (v) is the use of Figure 22a Figure 22b (vi) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (vii) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (viii) is adopted 22a is a schematic diagram of the intermediate structure produced by the corresponding steps; Fig. 22b (ix) is a schematic diagram of the intermediate structure fabricated by the corresponding steps of Fig. 22a; Fig. 22b (X) is a schematic diagram of the intermediate structure fabricated by the corresponding steps of Fig. 22a; Fig. 22b (xi) is adopted Figure 22b is a schematic diagram of the intermediate structure produced by the corresponding steps; Figure 22b (xii) is a schematic diagram of the intermediate structure fabricated by the corresponding steps of Figure 22a; Figure 22b (xiii) is a schematic diagram of the intermediate structure fabricated by the corresponding steps of Figure 22a; Figure 22b (xiv) is A schematic diagram of the intermediate structure produced by the corresponding steps of Fig. 22a; Fig. 22b (xv) is an intermediate structure sound map prepared by the corresponding steps of Fig. 22a; Fig. 22b (xvi) is an intermediate structure showing the corresponding steps of Fig. 22a; 22b(xvii) is an intermediate structure sound map made by the corresponding steps of Fig. 22a; Fig. 22b (xviii) is an intermediate structure sound map 22b (xix) made by the corresponding steps of Fig. 22a for the intermediate structure produced by the corresponding steps of Fig. 22a Fig. 22b(xx) is an intermediate structure diagram prepared by the corresponding steps of Fig. 22a. 58 200850099 TPPO/P2855-001 Fig. 22b (xxi) is an intermediate structure shown by the corresponding steps of Fig. 22a Figure 22b (xxii) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxiii) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a, and Figure 22b (xxiv) is the middle made by the corresponding steps of Figure 22a. Figure 22b (xxv) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxvi) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxvii) is made by the corresponding steps of Figure 22a The middle structure sound map, Fig. 22b (xxviii) is a schematic diagram of the intermediate structure made by the corresponding steps of Fig. 22a, Fig. 22b (xxix) is the schematic diagram of the intermediate structure made by the corresponding steps of Fig. 22a; Fig. 22b (xxx) is corresponding to Fig. 22a Figure 22b (xxxi) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxxii) is the intermediate structure sound map made by the corresponding steps of Figure 22a, Figure 22b (xxxiii) is adopted Figure 22a shows the intermediate structure of the corresponding steps, Figure 22b (xxxiv) shows the intermediate structure shown in Figure 22a, and Figure 22b (xxxv) Figure 22a shows the intermediate structure of the corresponding steps. 59 200850099 TPPO/P2855-001 Figure 22b (xxxvi) is a schematic diagram of the intermediate structure made by the corresponding steps of Figure 22a; Figure 22b (xxxvii) is the intermediate structure made by the corresponding steps of Figure 22a Figure 22b (xxxviii) is a schematic view of the intermediate structure produced by the corresponding steps of Figure 22a;

Figure 23 is a schematic cross-sectional view of the semi-symmetric support structure of Figure 5a _ "卜2_丨", which is slightly modified by the structure of Figure 5a, by adding an outer layer to the structure shown in Figure 21; 24 is a schematic cross-sectional view of a "2-2-3" semi-symmetric branch structure similar to the figure & a sub-symmetric symmetry similar to the figure &; : Figure 25 is a "2-2-1 semi-symmetric branch similar to "2-0-2" shown in Figure 12.

The cross-section of the structure is not intended to be 'slightly changed' to the structure in Fig. 12, but the display system, the _ metal layer of the first-stage circuit surface is differently located in the structure, which also reflects the asymmetry of the structure. Sexuality and symmetry. The location of the ke, which also reflects the structure of the non-woven shawl, the phase ___ 目, from the 200850099 TPPO / P2855-001 top left to the bottom right oblique line represents copper, the opposite The hatching from the top right side to the bottom left side indicates the barrier metal, the spotted shadow indicates the attached metal, the dot indicates no insulating material, the dense straight shadow indicates the welding mask, the black solid line indicates the terminal material, and the short extension line is formed. The shaded portion indicated by the vertical line represents the same layer of the same number of layers in the same different combinations and structures. / Should be transferred, in the frequency of shooting, the end of the age, the saki metal and the blocking gold introduction: make = τ all use different materials. However, none of these three materials use copper. How to choose the right metal material will be detailed in the following content [Description of component number] 61

Claims (1)

200850099 TPPO/P2855-OOJ is characterized by the tenth, the scope of the patent application. 1. A method for manufacturing a novel multi-layer coreless support structure, the production method comprises the following stages: I-making a material package containing her edge on the sacrificial carrier _ a film that conducts vias; a π-攸 sacrificial surface, a fine vertical layered array; the film contains an array of vias in the insulating material. 2. The method for fabricating a novel multi-layer coreless support structure according to claim W, characterized in that the stage 丨 comprises a sub-step. (1) plating a barrier metal layer on the sacrificial carrier layer; (ii) adding a seed layer to the barrier metal layer, adding, removing a photoresist layer on the seed layer, exposing and developing, forming (iv) wiring copper via holes in the photoresist pattern. (v) stripping the photoresist layer leaving an upright copper via; _ (V1) stacking her edge material on the via, the resulting freestanding film containing a copper via array in the insulating matrix . Such as the scope of patent application! The method for fabricating a novel multi-layer coreless support structure described in the present invention is characterized in that the subsection I includes sub-steps: (I) directly adding a photoresist layer on the sacrificial carrier, exposing and developing the engraved pattern; Especially (II) line plating barrier metal layer in the formed photoresist pattern; 62 200850099 TPPO/P2855-001 (III) Electroplating copper via holes on the line plating barrier metal; (IV) stripping the photoresist layer, The copper vias are exposed; (V) an insulating material is stacked outside the exposed copper vias, and the freestanding film thus formed includes an array of copper vias in the insulating matrix. 4. For the characteristic surface of the method for manufacturing a new multi-layer coreless structure according to the application of the above-mentioned item, the above-mentioned feature contains the remaining insulating material and the through-hole array. 5. A method for fabricating a novel multilayer coreless support structure, characterized in that the method comprises at least a stage: I-forming a conductive via film comprising an insulating material on a sacrificial carrier; 'Π-from the sacrificial carrier The film is peeled off to form a free-standing layered array; V-thinning, leveling; VI-assembly; VII-terminal stage. 6. The method for producing a novel core-free core-cut structure according to claim 5, wherein the conductive via hole is made of copper or a chemical-based copper. . 7. The method for fabricating and manufacturing a novel multi-layer coreless structure as described in claim 5, wherein the phase I comprises sub-steps: (i) full plate plating on the sacrificial carrier Metal layer; 63 200850099 TPPQ/P2855-001 exposure, development, shape (ii) adding a copper seed layer on the barrier metal layer (iii) adding a photoresist layer on the copper seed layer to form a photoresist pattern; (iv) line electro-mineral copper vias in the photoresist pattern; (v) stripping the photoresist layer leaving the erected copper vias; (vi) stacking the insulating material over the copper vias; stage II includes sub- Step: (vii) removing the sacrificial carrier; (viii) removing the barrier metal layer, and the electronic substrate thus formed includes the copper structure in the insulating matrix. 8. The novel multilayer coreless continuous body as described in claim 7 The method for controlling the structure is characterized in that the barrier metal layer has at least one of the following features: (a) the barrier metal layer is selected from the group consisting of the following metals: group, tungsten, complex, chin, and jinghe group. Nickel, gold, nickel layer gold layer, gold layer nickel , tin, lead, lead layer ^ tin layer, tin-lead alloy, tin-silver alloy, the barrier metal layer is prepared by physical vapor deposition < art preparation; ... 匕 工 (b) barrier metal layer is selected from the following metals: nickel , gold, nickel layer gold sound, post-tantalum nickel layer, tin, lead, lead layer tin layer, tin-lead alloy, tin-silver alloy, the common layer of the barrier is prepared by electroplating or electroless plating; c) The thickness of the barrier metal layer is from 1 μm to 5 μm. 9. The method of the novel multi-layer coreless support structure according to claim 7 of the invention, wherein the method further comprises a stage. m, adding a full ΙΓΓ and an additional via layer to form an internal substructure, the inner sub 匕曰 functional layer film is surrounded by the via layer, thereby the middle five metal functional layer. 4 (four) sub-base has an odd number The method for manufacturing the novel multi-layer coreless support structure according to claim 9 is characterized in that the stage includes the sub-steps: the light can be added to the pre-field _, _ light, (10) 彡, shape success (b) line electroplating copper work in functional graphics (c) stripping the photoresist layer; (4) adding a second lan gum layer, exposing and developing to form a via pattern; (e) performing electroplating in the via pattern to obtain a copper via hole; (g) The surname is engraved with a copper seed layer; (h) A layer of insulating material is laminated on the exposed copper via and the copper functional layer. 1Pa as a towel, patent, the new multi-layer coreless support described in item 9. The method of fabricating a structure is characterized in that it further includes a stage IV, adding an additional internal functional layer and a subsequent internal via layer to form an internal substructure comprising a layer of the via layer The electronic substrate thus assembled has an even number of metal functional layers. 12. A new multi-layer coreless support structure as described in claim 11 of the invention. 2008 20080 99 TPPO/P2855-001 plus an additional internal functional layer and a subsequent internal fabrication method 'characterized by the stage of the via layer IV includes sub-steps ·· _=)::=Material _ called surrounding insulation material added (j) on the outer surface exposed by the copper through hole and its surrounding metal layer; 00 added copper seed on the attached metal layer a layer; performing exposure and development to form a first functional layer of (1) adding a photoresist layer on the copper seed layer; (m) a copper electroplating functional layer in the second functional pattern; (n) a first functional layer of germanium Stripping the photoresist; (0) adding a photoresist layer, exposing and developing 'forming a third via pattern; (Ρ) forming a third copper via layer in the third via pattern; (q) stripping a third photoresist layer; (r) engraving the copper seed layer and the attached metal layer; (s) stacking the insulating material layer. 13. A method of fabricating a novel multi-layer coreless support structure as described in the scope of the patent application, wherein the attachment metal is selected from the group consisting of titanium, chromium and brocade. • 14. A method for fabricating a novel multilayer coreless structure as described in claim 5, characterized in that the fine segment I comprises sub-steps: (〇 directly adding a photoresist layer on the sacrificial support, Exposure, development, banding light 66 200850099 TPPO/P2855-001 engraved pattern; (ii) line electro-mineral barrier metal in the formed photoresist pattern; (iii) line electro-mineral copper on the barrier metal of line electric ore (iv) stripping the photoresist layer to expose the copper vias; (v) stacking the insulating material on the exposed copper vias; stage II includes substeps (vi) removing the sacrificial carrier; The electronic substrate comprises a copper structure in the insulating matrix, and the copper structure comprises a barrier metal layer. 15. A method for fabricating a multi-core coreless support structure according to the patent, which is characterized in that the barrier metal The layer has one of the following characteristics: (4) The barrier metal layer is selected from the following metals: nickel, gold, nickel back gold layer, gold layer back nickel layer, tin, staggered, staggered back tin layer, tin alloy, tin silver alloy , resisting the θ layer through chemical mines, electricity Or a combination of the two; (b) the thickness of the barrier metal layer is 〇.. micron to 5 micrometers. 16. The manufacturer of the novel multi-layer coreless support structure of the 14th patent is characterized in that it also includes Stage ΠΙ, adding a first metal butterfly and a second through-turning structure, the inner substructure comprising a layer surrounded by a via layer, the core metal functional layer film 'the electronic substrate thus assembled has an odd number of metals The work of the support structure, the new multi-layer coreless 67 described in claim 16 of the patent application, 200850099 TPPO / P2855-001 manufacturing method, characterized in that the addition of the first to form a layer comprising a layer of through holes The two-pass hole layer III includes the steps of: i is a step of the internal substructure of the layer, V111) adding a sub-layer on the sacrificial metal layer; graphics; (5) adding a first-function photoresist layer, performing exposure and development, and obtaining Function • (X) line electro-mineralized copper functional layer in the functional pattern; (XI) stripping the first functional photoresist layer; developing, obtaining (XII) adding the second photoresist via layer for exposure and pass Hole graphic. Fr? · /3⁄4 , XH1) in the second it hole pattern, the circuit is plated with copper to obtain a second copper via hole (xiv) to strip the second photoresist via layer; (xv) money to remove the copper seed layer; Xvi) removing the attached metal layer; (XVU) stacking the insulating material on the exposed second via layer. (4) A method for fabricating a novel multi-layer coreless structure according to the first aspect of the invention, wherein the adhesion metal is selected from the group consisting of titanium, road and brocade. 68 200850099 TPPO/P2855-001 19. The method for fabricating a novel multi-layer coreless support structure according to claim 16, wherein the method further comprises a stage iv, adding a first layer and a third pass The pore layer is formed to form an internal substructure comprising two functional layers of ugly pore layers, whereby the assembled electronic substrate has an even number of metal functional layers. 20. The method for fabricating a novel multi-layer coreless structure according to claim 19 of the patent application, wherein the step of adding the reinforcing layer and the additional through hole segment IV comprises the steps of: 9 6 (xviii) thinning and leveling Step (xvii) a layer of layered insulating material of the towel to expose the outer surface of the via layer in step (xiii); (xix) adding a metal layer to the outer surface exposed by the via hole and the insulating material; (XX) adding a copper seed layer on the adhesion metal layer; developing (xxi) adding another photoresist layer on the copper seed layer to perform exposure to form a functional pattern; and forming a circuit in the functional pattern formed in h into the copper (xxii) Forming a second copper functional layer in step (xxi); (χΧ11〇 stripping the photoresist layer added from the functional layer on the step (xxi); (xxiv) adding another photoresist layer, exposing, developing, Forming a third ^9 (four) in the third through hole pattern towel line electric ore into the copper to form a third copper through hole reed. (Li) stripping step (xxiv) added photoresist layer; 9 69 200850099 TPPO/P2855- 001 (xxvii) surname engraved copper seed layer and attached metal layer; (xxviii) A method for fabricating a novel multi-layer coreless support structure according to claim 5, wherein the insulating material is a fiber reinforced resin composite material. Port 22, as claimed in the patent application The method for fabricating a novel multilayer coreless support structure according to Item 5, characterized in that the insulating material layer comprises a resin selected from the following materials: thermoplastic resin, thermosetting polymer resin, thermoplastic resin and thermosetting polymer resin. 23. The method for producing a novel multi-layer coreless support structure according to claim 22 of the patent application is characterized in that the material further comprises an inorganic filler, the insulating material having at least one of the following characteristics. : (a) the inorganic particulate filler comprises ceramic or glass particles; (b) the particle size is on the order of microns; (c) the filler weight percentage is 15% to 3% by weight. The novel multi-layer coreless-free standard gentleman's clothing manufacturing method is characterized in that the insulating material is a fiber matrix composite material. The further step comprises a glass fiber selected from the group consisting of a facet and a twill or a woven arrangement as a new cut fiber or a continuous fiber. • 25 A new multi-layer coreless test as claimed in claim 23 of the patent application. The method of fabricating the structure is that the insulating material layer is a prepreg comprising a fiber view pre-impregnated with a partially cured 200850099 TPPO/P2855-001 polymer resin. The method for fabricating a novel multi-layer coreless support structure according to the item is characterized in that the layer is removed from the sacrificial body and the cylindrical positive hole structure is formed to form a stage of the independent layered array, which includes removal by a residual process. The step of sacrificing the carrier. *27. The method of fabricating a novel multi-layer coreless structure as described in claim 5, wherein the step of thinning and flattening the layer of insulating material to expose the outer surface of the underlying via comprises One of the following technologies: mechanical fine, chemical mechanical polishing, dry, and multi-stage processes implemented by two or more of these processes. The method for making a novel multi-layer coreless support structure according to item 5 of the patent application of the invention is characterized in that the method further comprises an additional stage: adding a functional layer and a via layer on both sides of the film. The method of fabricating a novel multi-layer coreless support structure according to claim 5, wherein the additional stage comprises the steps of: (a) adding an adhesion metal layer; (b) Adding a steel seed layer to the adhesion metal layer; (c) adding a first external photoresist layer on the copper seed layer, exposing and developing to form a first external photoresist pattern for the first and second functional layers; (4) The first external copper functional layer is line-plated in the first-outer photoresist pattern; (e) the first external photoresist layer is peeled off; 200850099 TPPO/P2855-001)^, an external photoresist layer is exposed, and exposure is performed. , the external Tonggong is a master shirt, forming a second photoresist pattern for the second hole layer; (g) performing a circuit layer in the second external photoresist pattern; the canister is an external copper through hole (h) stripping a second external photoresist layer; (1) etching away the copper seed layer and the attached metal layer; (:) stacking the insulating material layer on the out-out copper functional layer and the via layer; thinning and flattening the insulating material layer, Until the exposure is revealed, as described in item 29 of the patent application, new and re-existing. The manufacturing method, the pot 4#: ^^^ θ uncentered support structure is that the attached metal is selected from titanium, road and nickel chrome. The new multi-layer method described in the patent application of the π Patent Scope No. 29, the stipulation of the singularity of the sacred sacred sacred structure, is supported by repeating the step (4) to the step of adding the outer layer. ^,, and more: The new dressing method as described in claim 5, characterized in that the final stage VII comprises a step support structure (〇, the outer layer of the outer structure is added with external adhesion) a metal layer; (u) an external copper seed layer is added on the externally attached Jinlin; (111) an external photoresist layer is added, the shape is formed; * light, development, and a photoresist pattern is formed (r external photoresist line) Qiangang wire and Tan plate, · (V) strip off the external photoresist layer, · 200850099 (Vi) add terminal 弁钊ΤΡΡ〇 / Ρ 2855-00 ί copper pad; " _ layer, for exposure and development, there are options Exposed to remove the terminal photoresist layer from the metal layer layer and alloy; table, to, tin, silver, silver, and V111 of the above metal; develop, cover the copper wire, expose (lx) Remove the exposed copper seed layer and the exposed attached metal layer; (X) Add the solder thief layer to expose and exit the terminal metal layer. Make 5 pieces of the purely cut structure of the Qisaki financial layer, '1 lie in the electronic support structure Terminal Phase VII contains the steps: (i) Adding to the outer layer of the stackable structure Adding an externally attached metal layer; (ii) adding an external copper seed layer to the outer metal layer; forming an external photoresist layer, exposing and developing to form a photoresist pattern (5) The copper conductor and the pad (V) are stripped of the external photoresist layer; (VI) the exposed copper seed layer and the attached metal layer are etched away; the wire, the exposed (VII) is added with a solder mask layer, and exposed, Developed to cover the steel-out copper pad; the layer can be electrolessly plated from (V111) on the exposed copper pad, terminal 73 200850099 TPP〇/P2855>001 The following metals are selected: nickel, gold, tin, wrong , silver, handle, Qin Jin, tin _ silver, alloy and anti-corrosive materials. 34, such as the patent, Yan 5th (four) new multi-layer coreless support structure production method 'pure levy, root (four) The fine structure contains an even layer functional layer. 35. A novel multilayer as described in claim 5 The structure of the coreless support structure contains an odd layer work fabrication method characterized by a junction layer produced according to the method. 36. The new multi-layer helmet #1, as described in claim 5 of the patent application scope, the method of its ship, 74 200850099 XI, schema: 1