TW200849562A - Diffusion barrier in 3D memory and method for implementing - Google Patents

Abstract

One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.

Description

200849562 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a diffusion barrier in a three-dimensional memory, and a method for implementing the diffusion barrier. [Prior Art] The semiconductor industry has long been eager to increase the storage capacity of memory devices. This leads to 3D or 3D memory. However, such memory can be modified to achieve higher densities. SUMMARY OF THE INVENTION The following summary is presented to provide a basic understanding of one or more features disclosed herein. This summary is not an extensive overview. It is not intended to identify key or important elements, nor is it used to describe the scope disclosed. Rather, its primary purpose is to present one or more features in the simplistic form of the invention. In a three-dimensional or 3D memory cell, one or more diffusion barriers (difficulty) are used in a multi-scale or multi-scale. The _-scatter barrier allows the body to comprise a very low-resistance material such as copper, It is not easy to spread out into the surrounding area, especially in the elevated p

The use of a lower resistance ί allows the component to be downsized because it reduces the increase in resistance that occurs when the size of the body is reduced. Thus, the density and storage capacity of the resulting memory array can be made more often than given __. In order to achieve the foregoing and related purposes, to describe. However, when it comes to these __ 起 Μ 敝 敝 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The description is made with the same reference numerals, and wherein the various structures are not necessarily to scale, In the autumn, it is obvious that people with lower levels of these specific details === - one or more characteristics. In other examples, the representations described in L, are known to aid understanding.冓 and devices are illustrated in block diagram form, in FIGS. 1-3 W, an exemplary method for forming a 3D memory cell or a plurality of diffusion barriers are formed around the conductors of the cell, to: 7 An exemplary semiconductor substrate (4) on which the method is implemented is, as in the case of a further storage valley 1, wherein these low resistivity materials alleviate at least - = = Γ - degree adverse conditions. Although the following description and description of the method 100 ί on === the order of description of these actions or events cannot be solved in the sense of β, for example, the shots occur in a non-sequence, and other actions or events of =:= Bu occur simultaneously. In addition, the second = the light action for the 3 now its towel description - or the township is not or the implementation of the Qing is in the face - one or more actions can be completed - one or more separate actions and / Or stage. ΐΐΖ2, the first groove is moved in the first dielectric class, wherein «-% of the medium 204 is formed on the substrate fine, and may include, for example, a nitride-reduced and/or oxide-based material ( Figure 4). It can be understood that the substrate used therein and/or half of any type of semiconductor (for example, 矽·S〇I), such as semiconductor wafers and/or one or more dies on the germanium, And any other type of semiconductor and/or a layer of insect crystals on i, or other related thereto. It can also be understood that since the memory unit is to be in contact with the substrate 200, the substrate 2 below the unit can be used for other purposes, such as layout, such as line decoding II, column decoder, 1/〇 multiplexer. And / or read / write circuits. This increases area efficiency for expensive production lines. At step v104, a first diffusion barrier material layer 2?6 is formed over the first dielectric to line the first trench 2?2 (Fig. 5). Then, in step 1〇6, the second diffusion barrier material layer 2 (10) is formed on the first diffusion barrier material layer, so that the first trench is also replaced by 2 (Fig. 6). The first and second diffused brown material layers 2〇6, 2〇8 may include any one or several kinds of lower materials, such as pure (Ta), nitrogen her (hand), tree w), nitrogen tilt (tune, Nitriding 200849562, TlSlN), ruthenium (Ru), indium (M.), chromium (Cr), money _, 铢 (four), nitrogen ϋ Shi Xihua crane (WSlN), Hehua tin (TlW), button life (four) And the group-钌 physical == second diffusion barrier material layer can be formed by a deposition process, such as lateral JV and 7 or chemical vapor deposition (CVD), such that they are along the body of the trench 202 The thickness of the sentence. In addition, although the two-layered barrier-blocking material has been described (four). Fine, two-green transition material is advantageous, and a diffusion barrier material layer 2〇6 can provide a better adhesion diffusion barrier layer 2G8 for the dielectric material 2G8 can exhibit better diffusion resistance Barrier characteristics. Moreover, when one of the barrier material layers has a higher resistivity, then the strip is two; (affecting its lattice structure) so that it becomes more resistive, then the layer can diffuse the barrier material The thickness of layer 2G8 is about 1/10. In this manner, the overall conductivity reduction of the resulting component is substantially alleviated. The first ϊ ί ==, filling the trench 202 (4) with a very low resistivity first conductor 210, such as copper. This may include forming a pure 202^, which is well adhered to the diffusion barrier material layer used to fill the trench 202. It is reported in the chemical bath i's! For example, physical vapor deposition (PVD) ° - The conductor liLr copper fills the trench 202. In one example, the width is expanded. After the first trench 202 is filled with the first conductor plus, the second 8 and the first diffusion barrier material layer, in step no, the second mechanical polishing (CMP) is performed to remove excess material 21〇 2, 8, 2, 6, 7, therefore, the material t 206 filling the first trench 202 is substantially flush with the top surface of the dielectric 204. At step 112, the first conductor 210 is slightly recessed (Fig. 8). For example, if the height of the first removed r I is about 5 〇 nm, then about 5 11111 or about 10% of the first conductor 210 may be implemented in two or more techniques to recess the first conductor 21 . For example, anti-two, re-type and/or chemical mechanical polishing (CMp). In the reverse plating, a (reverse) biasing disk, some book light 200849562 === is added to the first-conductor trace to remove some of the upper layers of the first conductor. The over-emulsified sulfur can be used to wet the first conductor 21〇. The CMp process can also be allowed to perform a segment-length _ so that the first conductor 21G is overgrinded or recessed. When the first conductor 210 is exposed to the atmosphere, some oxidation side may occur. Therefore, the first conductor 21?' is cleaned, for example, by argon sputtering and/or hydrogen reaction. On the first conductor 210 of the i# 2 body and the recess, a third diffusion barrier layer 2 is formed. Next, in step m, over the third diffusion barrier material layer 212, = a fourth diffusion barrier material layer 214 (Fig. 1G). The third and fine diffusion material layer 2 214 may comprise any one or more of the following materials: for example, pass, w, view, salt,

TiSiN, Ru, M〇, Cr, Rh, Re, TaSiN, WSiN, TiW, Ta_w*Ta_Ru. And in the same manner as the first and second diffusion barrier material layers, in step 12, the third and fourth diffusion barrier material layers 212, 214 are planarized (eg, by CMP) to be associated with the first The top surface of the dielectric 204 is flush (Fig. 1). It can be appreciated that the third and fourth diffusion barriers 212, 214 effectively cover the first conductor 210. Although the third and fourth diffusion barriers have been described, it can be understood that a single diffusion barrier can be formed over the first conductor 21A. However, for the first and second expansions, the barrier 2G6, having two neobar barriers 212, 214 is advantageous because, for example, the diffusion barrier 212 can exhibit better diffusion barrier properties, while the barrier 214 Provides better adhesion to the materials that are subsequently applied. As with the first and second diffusion barrier material layers 2〇6, 2〇8, the respective thicknesses of the third and fourth diffusion barriers 212, 214 can be adjusted as needed to reduce the resistivity. It can be understood that the first diffusion barrier 2G6 and the fourth diffusion barrier 214 can include the same material (or a composite of materials), and the second diffusion barrier 208 and the third diffusion barrier 212 The same material (or composite of materials) can be included. In this method, the first conductor 21 is effectively surrounded by the same material (or composite of materials) 208, 212, the material 2〇8, 212 being composed of another material (or composition of materials) 206, Surrounded by 214. At step 122, a first heavily doped semiconductor material layer 220, such as a polysilicon, is formed over the first dielectric 204 and the first, second, and fourth diffusion barriers 206, 208, 214 (Fig. u). The polysilicon 220 may be doped during formation (on-site) and/or implanted after being formed to have a first conductivity type (e.g., n-type or p-type). The undoped or lightly doped polysilicon layer 222 is connected to 200849562 = can be ==, and is formed in step 124 in Fig. 124). This technique includes, for example, _ or the doping of the layer 22G over (4) 1 and/or forming to have a conductivity of !; == 24 to form (in situ) impurities. For the sake of brevity, in the text of the text - ζ ^ 2 ^; Ρ type or n · after f main layer 226 (and illustrated in most of the drawings). , Μ, 224 total secret is a single - 222 process 'such as chemical gas her product (CVD), thin layer 220, can cause 2 conductor 2 ig through such a high temperature π phase μ S 丨 "expanding into the surrounding area, such as the first A dielectric 204. This is r!; r material with U resistivity may have a stronger tendency to outdif. (4) Make I very, the material of the resistor ί is desired at the first conductor 210, at least because they are Size reduction 'by allowing more memory cells to be produced on a given area, improves (d) ΒΠ, which in turn increases storage capacity. More specifically, when the size of the first conductor 210 is allowed by a material that is not low resistivity The resistivity of the first conductor 210 is still maintained as a second (four) shape. When the cross-sectional area of the towel is reduced, the electrical side of the conductor generally increases. The same as the red or the kind of reagent, such as tantalum or niobium alloy, It is not necessary to add thin layers 22〇, 222, and/or [24: to reduce the temperature at which crystallization occurs. However, in the absence of diffusion barriers (10), Μ, Μ, these reagents need to be added to the thin layer 22〇 , 222 and/or 224 to mitigate out-diffusion (eg, by reducing The processing temperature required for crystallization). However, any suitable additive can be added to the thin layers 220, 222 and/or 224. At step 128, a dielectric anti-fuse material layer 230 is then formed over the thin layer 226. (第, ;; 囷) ° 黾 黾 丨 丨 丨 反 反 反 反 反 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨Rapid Thermal Process (RTP), Chemistry 9 200849562, Phase Sinking MCVD), liquid deposition, homeostatic oxidation, dry thermal oxidation, lysing oxidation, wet chemical emulsification, and/or electrochemical oxidation. Thinner than the semiconductor layer]. For example, the thin layer 226 may be about 100 times thicker than the thin layer 230. In step 130, a fifth diffusion material layer 232 is formed over the dielectric f anti-silver material layer ( Figure 13) The fifth diffusion barrier material layer 232 may comprise any one or more of the following materials: for example Ta, TaN, W, WN, TlN, TiSiN, Ru, M〇, Cr, Rh, Re TaSiN, and , Ta-W and Ta-Ru, and may be formed by, for example, a deposition and/or growth process. At step 132, - hard The cover material layer 234 can be formed on the first layer of the jade diffusion barrier material. The hard mask material layer 234 is relatively thick (for example, between about _A and Joche a and is included) Considering or several kinds of materials such as Ta, TaN, W, WN, TiN, TiSiN, Ru, Mo, Cr, Rh, Re, Shi N, w Xie, Cao, Ta w* Ta Ru, and For example, reading and / money long and lion ^ as can be touched, so that the layer of hard material (9) ^ thick rhyme, is to make it close to the processing of _ as a _ and / or CMP resistance ^. However, since the hard mask material layer 234 is relatively thick, it is advantageous for the layer to include one or more lower repair materials to mitigate the total electrical alcohol of the layer. For example, the hard mask material layer 234 can include W, Cao, and/or Ta. In addition, the hard mask material layer 234 can include a plurality of layers (as in other layers of the present invention). For example, the hard mask material layer 234 can include a lower resistivity of Ta on the top surface of the TaN when it is grown on the top surface of the TaN. At step 134, the hard mask material layer 234, the fifth diffusion barrier material layer 232, the dielectric = silk material layer 230, the second heavily doped semiconductor material layer 224, selective undoped or nudged / The semiconductor material layer 222 and the first heavily doped semiconductor material = columnar structure 236 are above the first conductor 210 (Fig. 15). Therefore, the hard mask layer 234, the fifth diffusion barrier 232, the dielectric f antifuse layer 23 (), and the semiconductor 226 having multiple impurities are included. It will be understood that 'as with other patterning described herein, this can be performed by a micro-shadow technique, where the lithography refers to the transfer of one or two between various media. In the lithography, a photosensitive photoresist coating layer is formed on the layer to be transferred to dt or a plurality of layers. The photoresist coating layer is then patterned' by exposing it to radiation or light of the type or polyhedral shape, wherein (optionally) passes through the intermediate layer comprising the pattern; The light causes the exposed or unexposed portions of the photoresist coating layer to be better or worse than the type of photoresist used. The developer is then used to remove areas of better solubility remaining in the patterned photoresist. The patterned photoresist can be joined as a mask to a lower layer that can be selectively processed (e.g., etched). When the columnar structure 236 is formed, some deviation may occur (eg, due to mask displacement, etc.), it being understood that the diffusion barriers 206, 208, 212, and/or 214 also serve as a residual barrier. 'to minimize the short circuit between the first conductor 210 and the columnar structure 236, especially the semiconductor 226 of the columnar structure 236. That is, the etchant used to pattern the thin layers 234, 232, 23A, 224, 222, and 22A is selective to the diffusion barriers 206, 208, 212, and 214 so that it removes the thin layer 234, 232, 230, 224, 222, and 220 are faster than etching the diffusion barriers 206, 208, 212, and 214. Likewise, the columnar structure should be moved to the left or right so that the diffusion barriers 206, 208, 212, and/or 214 are exposed to the etchant, with little or no diffusion resistance before the etching process is completed. Bars 206, 208, 212, and 214 are removed. Thus, the first conductor 210 will still remain contained within the diffusion barriers 206, 208, 212, and 214 even if the columnar structure is offset from the first conductor 21A. Figure 16 is a perspective view of the columnar structure 236 covering the first conductor 210 and surrounding the diffusion barriers 206, 208, 212 and 214. It can be seen that the columnar structure 236 has a substantially square cross section '* The first conductor 210 extends in the first direction. It can be understood that, in the same manner, simultaneously with the first conductor 210 and substantially parallel to the first conductor, an array of storage cells, a plurality of conductors and surrounding diffusion barriers can be formed, and then the thin layers 234, 232 can be made. 23, 224, 222, and 220 are patterned such that each of the conductors has a plurality of columnar structures spaced apart therefrom. As seen from arrow 238 in item 16, the 17th to 26th is a cross-sectional view of the miscellaneous unit. Fig. 17 only illustrates the structure of Fig. 15 from the projection direction (e.g., rotation about %., thin layers 220, 222, and 224 are shown as a single layer 226). At step 136, a dielectric fill is performed to substantially electrically insulate the columnar structure from the surrounding elements (e.g., other columnar structures - not shown). The dielectric f-fill may comprise any suitable (four) dielectric (four) material such as, for example, dioxo prior, _(8)(7) and/or nitrogen based materials. At 138, the dielectric fill 24 is planarized (e.g., via cMp) such that the basin is substantially flush with the top surface of the columnar structure 236 (Fig. 18). It will be appreciated that during the other planarization steps, the hard mask 234 acts as a barrier to (10) to relieve the columnar structure from (or other damage). At step 14, a dielectric 242 is formed over the filler material 24 and the columnar structure 236 (Fig. 19). The second dielectric 242 can similarly comprise any suitable % dielectric material such as, for example, an oxide and/or nitrogen based material. At step 142, a second trench 244 is formed (e.g., engraved) within the second dielectric (Fig. 20). The hard mask 234 is again used to protect the columnar structure 236 by being a patterned side barrier performed at step 142. At = 144, a sixth diffusion barrier material layer is formed over the second dielectric f 242 to accommodate a trench 244 (Fig. 21). At step 146, a barrier material layer 248 is formed over the sixth diffusion barrier material layer 246, thus also lining the second trench (Fig. 22). With the white paper, the diffusion barrier-like, the sixth and seventh diffusion barrier material layers 246, % or several of the following materials: for example, Ta, Lan, w,, ΤιΝ, delete, ^ 2 , Department, Know, Ding, Geng, Cao, (4) and Ta_Ru. Similarly, the time can be two IC steps such as physical vapor deposition _) and/or chemical 曰 and VII diffusion barrier material layers 246, 248, 2 (I, substantially uniform thickness. The sidewalls and the bottom surface of the 242 have barrier materials ίί 1 tube illustrates two diffusion barrier material layers, but it can be realized as a single diffusion barrier material and two barrier barrier (four) layers are advantageous because, for example, the sixth diffusion barrier material The characteristics of the layers 246, 248 are expanded, and, for example, when the diffusion resistance is substantially thinner, for example, the rate 'then the layer can be prepared to change the separation a, ▲ Wei Cheng (four) shot six ships turn The material layer 246, for example, has a higher resistance, so that the layer can be formed to 1/1 G of the thickness of the resulting element. In this formula, 'substantially reduces ^250--=, followed by, for example, an electro-mine process. The various layers of steel filled with the second groove ^pure steel are relatively thin (for example, about 5 〇 nm) high conductivity = residual knives. This barrier material adheres well, and can be ς lining red grooves 244 The diffusion can be carried out in a chemical bath, such as physical vapor deposition (PVD) to form a customized electricity Filling up from the bottom surface 12 200849562: In the example, the second conductor has a width of about 45 nm. As the second trench 244 is covered by the second conductor 250, the seventh diffusion barrier material layer 248 and the sixth diffusion barrier material After layer 246 is filled, chemical mechanical polishing (CMP) is performed at step 150 to remove excess of these materials 25, 248, 246 and expose first dielectric 242 (Fig. 23). As a result, the material filling second trench 244 250, 248, 246 are generally flush with the top surface of the dielectric 242. Next 'at step 152, the second conductor 250 is slightly recessed (Fig. 24). For example, if the first V body 250 has a twist of about 5 〇. Nm, then about 5 nm or about 1% of the second conductor 250 can be removed. One or more techniques can be implemented to recess the second conductor 250. For example, anti-electricity, wet etching, and/or chemical mechanical polishing can be used. (CMp). For reverse plating, a (reverse) bias is applied to the second conductor 25A together with some photochemical to remove some of the upper ions of the second conductor 25Q. Wet etching can be performed using sulfur peroxide. The second conductor 25 〇 can also allow the process to proceed The segment is slightly longer to cause the second conductor 25 to be ground or recessed. When the second conductor 250 is exposed to the atmosphere, some oxidation occurs. Therefore, the first conductor is washed at step 154 > 25〇, for example, by argon sputtering and/or helium gas reaction cleaning. In step 156, the dielectric 242 and the recessed second conductor 25A are formed to form an eighth diffusion barrier material layer (second S-picture). Next, in step (5), on the eighth diffusion barrier material layer, a ninth diffusion barrier material layer 254 is formed (Fig. 26). Like the other diffusion barriers mentioned herein, the eighth and ninth The diffusion barrier layer 2S2, 254 may comprise any one or more of the following materials: for example, TiW, Ta-W, and Ta-Ru. In the step, the eighth and ninth diffusion barrier materials g 252, 2M are planarized (e.g., by CMP) to be aligned with the top surface of the second dielectric. The 疋, 苐 and ninth diffusion barriers 252, 254 of Zeng Huanli effectively cover the second body 250. Similarly, although the eighth and ninth diffusion barriers, 254, have been described, it can be appreciated that a single-diffusion barrier can be formed over the second conductor 25G. However, having two: 52, 2 is advantageous because, for example, the diffusion barrier 252 can exhibit better diffusion, while the diffusion barrier 254 provides better adhesion to the subsequently applied material.疋=$ body. It is also possible to adjust the individual of the eighth and ninth diffusion barriers 252, 254 as needed to reduce the resistivity. It can be understood that the sixth diffusion barrier 246 and the ninth diffusion barrier ... 13 200849562 may comprise the same material (or a composite of materials), and the seventh diffusion barrier 248 and the eighth diffusion barrier P early 252 may comprise the same material (or a composite of materials). In this method, the second conductor 250 is effectively surrounded by the same material (or composite of materials) 248, 252, which is surrounded by another material (or composite of materials) 246, 254. . Figure 27 is a perspective view of the 3D storage unit 260 including the columnar structure 236 over the first conductor 21 and surrounding diffusion barriers 206, 208, 212 and 214, and the second conductor 250 and in the columnar shape Diffusion barriers 246, 248, 252, and 254 around structure 236. In the exemplary embodiment, the first and second conductors 210, 250 are substantially perpendicular to each other. However, the conductors can be oriented at any suitable angle relative to the other conductor. As mentioned a little above, in order to form an array of storage cells, a plurality of columnar structures spaced apart from each other may be formed over a plurality of conductors formed simultaneously with the first conductor 21 and parallel to the first conductor 210. Next, in the same manner, a plurality of conductors are formed on the columnar structure simultaneously with the second conductor 250 and substantially parallel to the second conductor 250. The layered configuration of the columnar structures and conductors can be continuously repeated to form a stacked or 3D memory array. Although not illustrated in Figure 27, it will be understood that the various storage units are electrically insulated from each other by a dielectric material such as filler material 240 and first and second dielectrics 204, 242 (Figs. 18, 15 and 26). Likewise, although vertical or stacked 3d memory improves area efficiency, it will be appreciated that this goal may even go a step further because the structure is formed over the first dielectric 204 (Fig. 15), and It is not directly on the semiconductor substrate 2 (8). In this manner, the δ 3 3D έ έ 体 is electrically insulated from the substrate 200, allowing other features/elements to be formed in the substrate, such as a read/write circuit. The 3D storage unit 260 operates, at least in some portion, because the columnar structure 236 has a first conductivity prior to applying a stylized voltage to the unit, and has a second conductivity after the stylized voltage is applied to the unit. More specifically, because antifuse 230 typically includes a dielectric material, it is in a first conductive state prior to applying a programmed voltage to the cell, and is in a second conductive state after the stylized voltage is applied to the cell. That is, when a sufficient voltage (e.g., a stylized voltage) is applied to the unit through the first and/or second conductors 21, 250, the antifuse 23 is broken so that the current can be more easily passed therethrough. Therefore, the conductivity of the unit 260 is significantly increased after the antifuse 230 is broken. Unit 260 may thus be considered to store the 200849562 storage bins or 1 'on the anti-fuse break (stylized) by the pair of - and / or second conductors 210 before the antifuse breaks (unprogrammed) , 250 applies a voltage and ^ = or 〇. For example, the column unit 236 can be used to complete the survey of the coffee unit, wherein the applied voltage is known to be reactionary. Break === (d) It is puzzling that, although discussing the characteristics of the methods described in this article (for example, those organizations are not in the 4th 27th figure), the method is stated in the first μ. Objects '===& (and structures) can be considered to be independent of each other, can exist alone, and do not need to be considered for any specific aspect described in the figure. In addition, the thin layer described in this article can Formed in a suitable manner, such as spin coating, sputtering, growth and/or deposition techniques, etc. Similarly, those skilled in the art can make variations and/or changes in accordance with the reading and/or understanding of the specification and drawings. The disclosure of the present invention includes all such modifications and variations and is intended to limit the invention in any way. In addition, although only a few of the several embodiments have been disclosed - specific features or aspects have been disclosed. Or aspects may be combined with one or more other features and/or aspects of other embodiments as desired. In addition, the terms "including", "having", "having (four)", "banding" are used herein. Yes and / The rhyme of its variants, such terms are used to refer to the meaning of the meaning, such as "including." Similarly, "exemplary" health refers to - a real complement, which refers to the best real. It is a matter of simplification and ease of understanding that the features, layers and/or elements described herein are described as having a particular size and/or orientation relative to each other, the actual size and/or orientation of which may be substantially The above is different from the illustrated size and / or direction. 15 200849562 [Simple description of the diagram] The first 1-3 diagram includes a flow chart illustrating an example method for implementing diffusion in a 3D memory unit; A cross-sectional view of a semiconductor substrate, for example, illustrates a first body and a columnar structure of a 3D memory cell formed thereon, wherein one or more diffusion barriers are formed around the first body; A perspective view of the first conductor and the columnar structure of the 3D read unit, wherein one or more diffusion barriers are formed around the first conductor; the I7-% diagram is a cross-sectional view of an exemplary semiconductor substrate, illustrating Forming a second conductor on the columnar junction f of the memory cell One or more diffusion turns are formed around the second conductor; the L Z7 pattern includes a first view, a second conductor, and a perspective view of the memory cell of the columnar structure between them. One or more diffusion barriers are formed around the first and second conductors. [Main Element Symbol Description] 100 Methods 102 to 160 Step 200 Semiconductor Substrate 202 First Trench 204 First Dielectric 206 First Diffusion Barrier Material Layer 208 Second diffusion barrier material layer 210 First conductor 212 Third diffusion barrier material layer 214 Fourth diffusion barrier material layer 220 Younger semiconductor material layer 222 Polycrystalline layer 224 Younger layer of semiconductor material 226 single layer 230 dielectric antifuse material layer 16 200849562 232 234 236 238 240 242 244 246 248 250 252 254 260 fifth diffusion barrier material layer hard mask material layer columnar structure arrow dielectric filler second dielectric second trench Slot sixth diffusion barrier material layer seventh diffusion barrier material layer second conductor eighth diffusion barrier material layer ninth diffusion barrier material layer 3D storage unit 1 7

Claims (1)

200849562 X. Patent application scope: 1. A memory unit comprising: = first, in a trench of a first dielectric; a first conductor 'in a trench of a second dielectric; and a column And constituting the first and second conductors, the columnar structure having a first conductivity before applying a stylized voltage to the 5L, and adding the stylized voltage to the unit And then having a second conductivity, at least one of the first and second conductors being recessed in the first and second dielectrics respectively, the at least one recess being filled by the first diffusion barrier, such that the columnar structure The first £. diffusion barrier joint. 2. According to the scope of patent application! The memory unit of the present invention, wherein the main structure comprises: a semiconductor over the first conductor; and a fuse 'on the semiconductor, the anti-fuse is applied to the stabilizing voltage The cell is first in a first conductivity state and is in a second conductivity state after the stylized voltage is applied to the cell. 3. The memory unit according to claim 2, wherein the tissue structure comprises: a hard mask over the anti-fuse. 4. The memory unit of claim 3, wherein the conductors comprise copper. 5. The memory unit of claim 4, wherein at least one of the trenches is lined with the first diffusion barrier such that at least one of the first and second conductors is The first diffusion barrier is surrounded. 6. The memory unit of claim 5, wherein the columnar structure comprises: a second diffusion barrier between the antifuse and the hard mask. 7. The memory unit according to claim 6, comprising: a third diffusion barrier on the first diffusion barrier in the at least one recess. 8. The memory unit according to item 7 of the scope of the patent application, wherein at least one of the grooves of the towel is prefabricated with the second expansion, so that at least one of the first and second conductors It is surrounded by the first diffusion barrier surrounded by the second diffusion barrier. 9. According to the patent, the memory unit described in the patent f 帛 8 item, wherein the columnar structure does not include the wrong or 18 200849562 bismuth alloy. Ιο· - a memory unit, comprising: a first conductor; a second conductor; and a shape, a first and a second conductor, the modified structure does not include a wrong or wrong alloy, a miscellaneous, Adding a stylized voltage to the unit has a first conductivity, and a second conductivity after the stylized voltage is applied to the unit. 11. The memory unit according to claim 10, comprising at least the following One of the first conductors is in a trench of the first dielectric; and the second conductor is in a trench of the second dielectric. 12. ^ According to claim 11 The memory unit, wherein the first and second conductors are recessed in the first and second dielectrics, and the at least one recess is caused by the second fWfH^ such that the impurity has no first diffusion-bonding. 12 series of fiber units, drilled: a Feng conductor, above the first conductor; and the child ^, 糸 on the county 'body, the anti-solving wire is added to the unit in the stylized voltage The ilt conductivity state adds a stylized voltage to the ^ conductivity state. 4) The 13 items of the narration of the fresh-spotted structure include: a hard mask over the anti-fuse. The memory unit of item 14, wherein the conductors comprise copper. The memory unit of claim 15, wherein at least one of the grooves is: expanded: = r_, 17. The memory unit according to claim 16 of the patent scope, wherein the second diffusion barrier is Between the anti-fuse and the hard mask, the memory unit according to claim 17 of the patent application scope includes: a second diffusion barrier, wherein the at least one recess comprises The material described in item 18 of the patent application is expanded as early as possible. The sin of the singularity of the sufficiency of the sufficiency of the sufficiency of at least one of the 19, 200849562 of the grooves is lined with the third diffusion barrier, At least one of the first and second conductors is surrounded by the first diffusion barrier surrounded by the third diffusion barrier. The memory unit comprises: a first copper conductor; a columnar structure over the first conductor; and a second copper conductor over the columnar structure, wherein The columnar structure includes: a semiconductor over the first conductor; An antifuse, over the semiconductor; and a hard mask over the rectified wire, the antifuse being in a _ state prior to applying a stylized voltage to the cell, adding a stylized voltage After the unit is in the second guide: the shape 21. According to the scope of claim 20, the memory unit includes the following to, 丨, and =. a first conductor, in the trench of the first dielectric; and one of: "one conductor" in the trench of the second dielectric. 22. < The memory unit, the first in the basin = at least one of the gamma traps in the first and second dielectrics; the recessed conductor is filled with a diffusion barrier such that the pillar structure and the first diffusion barrier. (3) The memory unit according to claim 22, wherein one of the trenches is lined with the first diffusion barrier such that the first and second conductors are first Surrounded by diffusion barriers.] The main eve of the 24th memory according to the scope of patent application 帛μ item memory single second diffusion, between the reversal and the hard mask her structure includes: The memory unit of claim 24, comprising: - a second diffusion barrier, the first expansion in the at least one trap. 26. according to the application described in claim 25, With the third diffusion transfer lining, the storage-and the second and the second--are covered by the third diffusion barrier The first diffusion chamber of the circumference, 27 of the four. According to the scope of claim 26, the zero circumference mfe is earlier % 'where the semiconductor does not include the wrong or 20 200849562 tantalum alloy. 28 · a method of forming a memory unit, The method includes: filling a trench in a first dielectric with a conductor and a conductor; recessing the first conductor in the first dielectric; filling the recess with a first diffusion barrier; forming a columnar structure at the a diffusion barrier; and forming a conductor-conductor over the columnar structure, the pillar structure having a first conductivity prior to applying a stylized voltage to the cell, and applying a stylized voltage to the cell The method of claim 28, wherein the forming the columnar structure comprises: forming a layer of semiconductor material over the first diffusion barrier and the first dielectric; forming a layer of anti-k wire material over the layer of semiconductor material; and patterning the layer of antifuse material and the layer of semiconductor material, the antifuse being first before adding a stylized voltage to the cell The conductive state is in a second conductive state after the staging voltage is applied to the unit. The method according to claim 29, wherein the forming the columnar structure comprises: forming a hard mask material a layer on the layer of the anti-fuse material; and patterning the layer of the hard mask material, the layer of the anti-fuse material, and the layer of the semiconductor material. 31. The method of claim 30, wherein The semiconductor includes steel. 32. The method of claim 31, comprising: translating the trench with the first diffusion such that the first conductor is surrounded by the first diffusion. The method of claim 32, wherein the forming the columnar structure comprises: 幵> forming a layer of a diffusion barrier material over the layer of the anti-solvus material, forming a layer of hard mask material Above the second diffusion barrier material layer; and patterning the hard mask material, the second diffusion-transfer material layer, and the secret layer.彳干干(四)材 34. The method of claim 33, comprising forming a third diffusion barrier over the first diffusion barrier in the recess. 21 200849562 35. The method of claim 34, comprising: lining the trench with the third diffusion barrier such that the first conductor is surrounded by the third diffusion barrier Surrounded by a diffusion barrier. The method of claim 35, wherein the columnar structure does not include a tantalum or niobium alloy. 37. A method of forming a memory cell, comprising: filling a trench in a first dielectric with a first conductor; forming a pillar structure over the first conductor; and forming a second conductor Above the columnar structure, the columnar structure does not include a tantalum or niobium alloy having a first conductivity prior to applying a stylized voltage to the unit, and having a second after applying a stylized voltage to the unit Electrical conductivity. The method of claim 37, comprising: recessing the first conductor in the first dielectric; and filling the recess with a first diffusion barrier such that the pillar structure and the first Diffusion barrier bonding. 39. The method of claim 38, wherein forming the columnar structure comprises: forming a layer of semiconductor material over the first diffusion barrier and the first dielectric layer; forming an antifuse material layer Overlying the layer of semiconductor material; and patterning the layer of antifuse material and the layer of semiconductor material, the antifuse being in a first conductivity state prior to applying a stylized voltage to the cell, adding a stylized voltage After the unit is in a second conductivity state. 40. The method of claim 39, wherein forming the columnar structure comprises: forming a layer of hard mask material over the layer of antifuse material; and layering the hard mask material, anti-melting The layer of silk material and the layer of semiconductor material are patterned. 41. The method of claim 40, wherein the conductors comprise copper. 42. The method of claim 41, comprising: lining the trench with the first diffusion barrier such that the first conductor is surrounded by the first diffusion barrier. 43. The method of claim 42, wherein forming the columnar structure comprises: 22 200849562 forming a second diffusion barrier material layer over the antifuse material layer; forming a hard mask material layer Overlying the second diffusion barrier material layer; and patterning the hard mask layer, the smear layer, the antifuse material layer, and the semiconductor material layer. 44. The method of claim 43, wherein: forming a third diffusion barrier over the first diffusion barrier in the recess. 45. The method of claim 44, comprising: using the third diffusion-transforming trench such that the germanium conductor is surrounded by a scale-diffusion barrier, the first diffusion barrier being Surrounded by a third diffusion barrier. 46. A method of forming a memory cell, comprising: filling a trench in a first dielectric with a first copper conductor; forming a layer of semiconductor material over the first conductor and the first dielectric; forming an antifuse material a layer over the layer of semiconductor material; forming a hard mask layer over the layer of reverse-solving material; patterning the hard mask layer, the layer of antifuse material, and the layer of semiconductor material to form a pillar And forming a second copper conductor over the columnar structure, the antifuse being in a first conductivity state prior to applying the stylized electricity house to the unit, after the staging voltage is applied to the unit The second conductivity state. I 47. The method of claim 46, comprising: recessing the first conductor in the dielectric, and filling the recess with a first diffusion barrier such that the columnar structure and the first Diffusion barrier bonding. 48. The method of claim 47, comprising: using the first diffusion-filling trench such that the first conductor is surrounded by the first diffusion barrier. 49. The method of claim 48, comprising: forming a second diffusion barrier material layer over the antifuse material layer, forming a hard mask material layer in the second diffusion Above the barrier material layer; and patterning the β-hard mask material layer, the second diffusion barrier material layer, the anti-solvus material layer, and the semiconductor material 23 200849562 layer to form the columnar structure. 50. The method of claim 49, comprising: forming a third diffusion barrier over the first diffusion barrier in the recess. 51. The method of claim 50, comprising: lining the trench with the third diffusion barrier such that the first conductor is surrounded by the first diffusion barrier, the first diffusion barrier Surrounded by the third diffusion barrier. 52. The method of claim 51, wherein the semiconductor does not include tantalum or niobium gold.