〇9twf.doc/n 200849048 J ^ XU-Γ 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種預測晶圓良率的方法， 是有關於-種藉由簡單計算得出良率@、’且特別 率的方法。 手相失之預剛晶圓良 【先前技術】 隨著超大型積體電路技躺持續發展，積 度也日漸提昇’而於製程中所產生之極微=的 n o 現在就成為影響積體電路品質之_缺陷。巧陷 製程中所產生之缺陷分為可修補的缺陷與不能’ ，兩種，其中可修補的缺陷為不影響良率之缺P；的， ::::缺陷指的是會降低製程良率之缺：,： 法電性流通而紐晶圓失效(dle =疋热 ，命缺陷_，。因一 命缺陷與非致命缺陷，並藉由致命二 定，正是對致中輪進行監控以維持產線的穩 田則積體電路製程的重要課題之一。 的$率來在半導體製程中通常是使用商業化套裝 不來ίίτ損失的預測，其是利用各種 再經，的;;來未 過多軟體中’由於影響致命機率的參數 等 鍵靶圍（Critical area, Ac)、缺陷尺寸（D) 、 相同的線寬製程下，只要不同產品就要重新 200849048 VMU4 22509twf.doc/n Ο ο 計算Ac，不僅費時且佔記憶體，更麻煩的是D值的取得， D值是各機台傳出之缺陷訊號，而非真正的缺陷尺寸， 因此我們發現由於量測機台的不同特性，而造成0〇值無 法表示真正的缺陷尺寸，又這些程式過於繁瑣紐 :十需要花費大量的時間去設定以及修正參數， …/ f產品在試產（pil°tmn)時期即時反映的要求或 投片量少產品多樣化的代王產品，前述之參數皆由機台 ，出之訊號’各機台的靈敏度及精確度不同，者所有的 ==算！:會，訊(noise)心而良率 相者日主’一般商業化套裳的良率預測軟體價格 相田叩貝，同8守也增加了生產成本。 【發明内容】 並進卿通、之建立，迅速地預測良率 法，的，本發明提出一種預測晶圓良率的方 接著曰圓&陷率貧料，提供每周固定檢測之資料， 日日0產出（Wafer om)時分析每一膜層之 周;^之ΐ析各膜層時需考慮各膜層製造當時“ 率損失。卩、陷百刀比乘以-中位數，即為晶圓良 的中位數來=ϋ同減中各晶圓的缺陷數量所得到 以單—日表此批次晶_缺陷數量，避免了在分別 曰"、缺陷數量來進行計算時單一晶圓的檢測誤 j〇9twf.doc/n 200849048 差造成計算結果的偏差。此外， ^ 使用的參數較少，且以晶圓二在進行計算時所 良率損失。另外，本發明不方式計算出晶圓 體，因此可以有效地降低m責_化套襄軟 為讓本發明之上述特徵和優點能 Ο ο ==並配合所附圖式，作詳細說明如下。 [貫施方式】 的Λ發明Λ預測晶圓良率的方法是用以計算一批晶圓 體製程中，晶圓上的每_層心二工 衣乍凡成的，且製作完成所需的時間也並不相同，因此 在利用本發明來計算晶率損失時，必須採用當層膜 層製作完成時的數據資料來進行計算。 首先，在建立此型前，先以人工缺陷分類 Uamial defect Classificat聰，MDC)檢測出相同的缺陷 並確疋其位置。紐，經由電性檢測制缺陷的位置， 並確認此顧是否使日日θ粒失效。接著，將人玉檢測結果 與電性檢測結果輯，使晶粒失效的缺陷定義為致命缺 陷。表1為對相同缺陷進行人工檢測與電性檢測的結果。 由表1可以得知，編號丨的缺陷之位置的人工檢測結果 與電性檢測結果相符合，同時可使晶粒失效的缺陷，因 此將編號1的缺陷定義為致命缺陷。編號2的缺陷之位 置的人工仏測結果與電性檢測結果雖然相符合，但並不 6 200849048 r ^^」09twf*doc/ii 會使SH粒失效，因此並非為致命缺陷。編號3的缺陷之 位置經過人工檢測與電性檢測之後，二者的結果並不相 付，雖然電性檢測出晶粒失效，但並非此缺陷所造成， 因此並非為致命缺陷。編號4的缺陷之位置經過人工檢 測與電性制之後，二者的絲並不補，且晶粒也未 失效，因此並非為致命缺陷。之後，將致命缺陷的數量 除以全部缺陷的數量即可得到此種缺陷的致命機率 (killer probability)。 缺陷編號 人工檢測钦置與電性 檢測位置是否符合 晶粒是否失效 1 〇 —1 〇 2 〇 X 3 X 〇 4 ----------—-- X --~~-----L __ 、另外，當我們在分析基線（baseline)時，欲以一數值 代表-個群組時’常賴有平均值與中位數。例如，當週某 一膜層掃出的缺陷數有：1〇、1〇、15、2〇、25、25及3〇平均 值為（HmGU)m3，中位數為上述七個數值依 序由小至大位於巾間者=20，當正常狀訂細可發現平 均值幾乎等於中位數。但當有問題發生時1Q、12、n 129及200，平均值·· 44· 7中位數：21可見平均值容易 又心專，而中位數比較穩定，但也可以反應出基線的變化。 200849048 〜义 v/~r “509twf.doc/n 本發明利用由同一批次中各晶圓缺陷數量所得到的中位 數^代表此批次晶圓的缺陷數量，可避免檢測誤差造成 计异結果的偏差。中位數乘上致命缺陷率即可預測該晶 圓之失效晶粒數目。 明參閱弟1圖，為本發明每週晶圓缺陷資料運算示 意圖，圖中顯示每週的取樣缺陷百分比，經換算成失效經粒 數目母週固疋以人工缺陷分類（manual defect classmcation，MDC )，並計算各類型的缺陷數目除以缺 f) o 陷總數等得出各類型缺陷所佔缺陷之百分比，各類型缺 陷百刀比乘上致命缺陷率，就可以預測本週各類型缺陷 失效晶粒的百分比，因此也就可以算出本周之良率預測 值:，為這些數據資料是現成的，無須為了預測良率而 進，實驗。但膜層完成之_有可能落在兩次固定檢測 之間，需考慮每一膜層製造當時距離前一周檢測與後一 周檢測之時間配以權重算出。 /' 舉例來說，具有三膜層之晶圓在晶圓產出（wafer〇m) 進行最後分析時必須將第一膜層、第二膜層及第三膜層 2命缺陷進行累計’以計算該晶圓之致命缺陷，“ «该晶圓之良率’例如第—膜層是在距離最後分析之 如天前做的，20除以7之後是2餘6，gp距離前三週缺 分析的時間為少i天，距離前二週缺陷分析之時間多6 天’因此^須將前三週之料請缺陷之致命缺陷數乘以 —加上剛二週之各類型缺陷之致命缺陷數乘以6广，第 二膜層是在距離最後分析之10天前做的，1〇除以7之後 是1餘4，即距離前二週缺陷分析的時間為少3天，距離 200849048 ----——509twf.doc/n 刚一週缺卩曰分析之時間多4天，因此必須 類型缺陷之致命缺陷數乘以3/7加上前—、週=二 陷之致命缺陷數乘以4/7，以此類推t各，缺 =致命缺陷相加即可麵—批即將出-= 产、兄圓在製造每—膜層時，各晶圓之缺陷 :况:=二我們可以取當批晶圓每_膜層之缺陷中位 數’、.先相-膜層之缺陷時即可乘上此—中位數 η ο ^晶圓該膜層之缺陷數，以此累計各該膜層之缺陷數γρ 為該批晶圓之良率損失。 ρ 、，請參閱第2目，系本發明預測晶圓良率之流程圖， 百先由於取樣一批晶圓計算出致命缺陷率（诎匕〇9twf.doc/n 200849048 J ^ XU-Γ 九, invention description: [Technical field of invention] The present invention relates to a method for predicting wafer yield, which is related to - a simple calculation Rate @, 'and special rate method. The pre-finished wafers are lost [previous technology] As the super-large integrated circuit technology continues to develop, the accumulation is increasing day by day, and the mini-no in the process is now affecting the quality of the integrated circuit. _defect. The defects generated in the process are divided into repairable defects and failures. Two kinds of defects can be repaired without affecting the yield P. The :::: defects refer to the process yield reduction. The lack of::: The legal flow and the failure of the new wafer (dle = heat, life defect _,. Because of a fatal defect and non-fatal defects, and by fatal determination, it is the monitoring of the middle wheel Maintaining the production line of the stable field is one of the important topics in the integrated circuit process. The rate of $ in the semiconductor process is usually the use of commercial kits not to predict the loss of ίίτ, which is the use of various re-transitions; In the software, due to the influence of the parameters such as the critical area (Critical area, Ac), the defect size (D), and the same line width process, as long as different products are to be re-200849048 VMU4 22509twf.doc/n ο ο Calculate Ac Not only is it time-consuming and occupies the memory, but the more troublesome is the acquisition of the D value. The D value is the defect signal transmitted by each machine, not the actual defect size. Therefore, we find that due to the different characteristics of the measuring machine, 0〇 cannot represent the true deficiency The size of the trap, and these programs are too cumbersome: Ten need to spend a lot of time to set and correct the parameters, ... / f products in the trial production (pil °tmn) period immediately reflected the requirements or the amount of product is less diversified product generation Products, the above parameters are all from the machine, the signal 'the sensitivity and accuracy of each machine are different, all == count!: will, news (noise) heart and yield phase of the day's general commercialization The yield of the skirt is predicted by the price of the soft phase, and the same as the 8th guard, which increases the production cost. [Invention] The establishment of the Qingtong, and the rapid prediction of the yield method, the present invention proposes a prediction of wafer yield. The square is then rounded & the trapping rate is poor, and the weekly fixed test data is provided. The day of each film layer is analyzed at the time of Wafer om; the film layer needs to be considered when decomposing each film layer. At the time of manufacture, "rate loss. 卩, trapped 100-knife ratio multiplied by - median, that is, the median of the wafer is good = the same as the number of defects in each wafer, the single-day table is obtained. The number of crystal _ defects, avoiding the calculation of the number of defects and the number of defects The detection error of a single wafer j〇9twf.doc/n 200849048 The difference causes the deviation of the calculation result. In addition, ^ the parameters used are small, and the yield loss is calculated when the wafer 2 is calculated. In addition, the present invention does not. The wafer body is calculated, so that the m-responsibility can be effectively reduced. The above-mentioned features and advantages of the present invention can be described in detail with reference to the drawings, and the following is described in detail. ΛInvented ΛThe method of predicting wafer yield is to calculate the process of a batch of wafers, and the time required for the completion of the fabrication is not the same. Therefore, when the present invention is used to calculate the crystal loss, it is necessary to calculate the data when the layer is completed. First, before establishing this type, Uamial defect Classificat, MDC) was used to detect the same defect and confirm its location. New Zealand, through the electrical detection of the location of the defect, and confirm whether this Gu invalidation of the day θ particles. Next, the results of the human jade detection and the electrical detection result are combined to define the defect of the grain failure as a fatal defect. Table 1 shows the results of manual and electrical detection of the same defects. It can be seen from Table 1 that the manual detection result of the position of the defect of the number 丨 coincides with the electrical detection result, and at the same time, the defect of the grain failure can be made, and thus the defect of No. 1 is defined as a fatal defect. The artificial guessing result of the defect number of No. 2 is consistent with the electrical test result, but it is not 6 200849048 r ^^"09twf*doc/ii will invalidate the SH grain, so it is not a fatal defect. After the position of the defect of No. 3 is manually and electrically detected, the results of the two are not paid. Although the die is electrically detected, it is not caused by this defect, so it is not a fatal defect. After the position of the defect of No. 4 is manually detected and electrically, the wires of the two are not compensated, and the die does not fail, so it is not a fatal defect. After that, the number of fatal defects is divided by the number of all defects to get the killer probability of such defects. The defect number is manually detected whether the position of the placement and the electrical detection is in conformity with whether the die is invalid. 1 〇—1 〇2 〇X 3 X 〇4 ----------—-- X --~~--- --L __ , In addition, when we are analyzing the baseline, we want to represent a group with a value, which often depends on the mean and median. For example, the number of defects swept out by a film in the week is: 1〇, 1〇, 15, 2〇, 25, 25, and 3〇, the average value is (HmGU)m3, and the median is the above seven numerical values. From small to large, it is equal to 20 in the towel. When the normal shape is set, the average value is almost equal to the median. But when there is a problem, 1Q, 12, n 129 and 200, the average value is 44. 7 median: 21 visible average is easy and self-study, while the median is stable, but can also reflect changes in the baseline. . 200849048~义v/~r “509twf.doc/n The present invention utilizes the median ^ obtained from the number of defects in the same batch to represent the number of defects in this batch of wafers, which avoids the detection error and causes the calculation to be different. The deviation of the result. The median multiplied by the fatal defect rate can predict the number of failed grains of the wafer. See Figure 1 for a schematic diagram of the weekly wafer defect data calculation, showing the weekly sampling defects. The percentage is converted into the number of failures by the number of defects, and the number of defects is calculated by dividing the number of defects of each type by the number of defects, the total number of defects, etc. Percentage, the number of defects per type multiplied by the fatal defect rate, can predict the percentage of failure crystals of each type of defect this week, so you can calculate the predicted yield of this week: for these data is readily available, no need to Predict the yield and experiment, but the completion of the film may fall between the two fixed tests, and it is necessary to consider the time when the film is manufactured at the time of the previous week and the next week. Calculated by weighting. /' For example, a wafer with a three-layer layer must have a first film layer, a second film layer, and a third film layer at the wafer yield (wafer〇m) for final analysis. Life defects are accumulated 'to calculate the fatal defect of the wafer, ''The yield of the wafer', for example, the first layer is made before the final analysis, and 20 is divided by 7 is 2, 6, Gp is less than i days from the first three weeks of analysis, and 6 days longer than the first two weeks of defect analysis. Therefore, the number of fatal defects in the first three weeks of the defect must be multiplied by - plus just two weeks. The number of fatal defects of each type of defect is multiplied by 6 wide, and the second film is made 10 days before the final analysis. After 1〇 divided by 7 is 1 more than 4, that is, less time from the first two weeks of defect analysis. 3 days, distance from 200849048 -----509twf.doc/n Just one week after the analysis of the lack of analysis, so the number of fatal defects of type defects must be multiplied by 3/7 plus before - week = two traps The number of fatal defects is multiplied by 4/7, and so on. The lack of fatal defects can be added to the surface - the batch is coming out -= production, brother in the manufacture of each film In the case of layers, the defects of each wafer: Condition: = 2 we can take the median of the defects of each batch of wafers, the first phase - the defect of the film layer can be multiplied by this - the median η ο ^ The number of defects in the film layer, thereby accumulating the defect number γρ of each film layer as the yield loss of the batch of wafers. ρ , , please refer to the second item, which is a flow chart for predicting the wafer yield of the present invention, and the first calculation of the fatal defect rate by sampling a batch of wafers (诎匕
Pr〇babiilty，Kp) 101，再由每周固定檢測得出當週晶圓缺 陷資料102，分析各膜層之失效缺陷晶粒百分比，各膜層 之失效缺陷晶粒百分比乘上一中位數即為該膜層之良率 損失103,累計各膜層之良率損失即為該批晶圓之良率損 失104。 綜上所述，本發明先利用人工缺陷分類及電 性測試結紐行比較疊對，赠立致命㈣率，再利用 每週固定時間分析各類型缺陷所得出的晶圓缺陷資料， 利用這些晶圓缺陷資料經過簡單的時間權重的換算即可 得出各膜膜層之缺陷資料，進而得知該晶圓之良率。 此外’本發明在進行計算時所使用的參數較少，且 是以晶圓上實際的缺陷數量來進行計算，因此可以避免 因外界產生干擾而產生的誤差以及可以適用在不同的機 台，而以花費較少時間且準確的方式計算出晶圓良率損 9 200849048 yjiKj-t ^^09twf.doc/n 失，不需使用昂貴的商業化套裝軟體，因此達到了降低 生產成本的目的。 雖然本發明已以實施例揭露如上，然其並非用以限 定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作些許之更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所 界定者為準。 ’ 【圖式簡單說明】 第1圖為本發明每週晶圓缺陷資料運算示意圖，圖中顯 J 示每週的取樣缺陷百分比，經換算成失效經粒數目。 第2圖為依照本發明實施例所繪示的計算晶圓良率損 失的方法之流程圖。 【主要元件符號說明】 101〜104 ··步驟 Ο 10Pr〇babiilty, Kp) 101, and then weekly fixed test to obtain the wafer defect data 102, analyze the percentage of failure defect crystal grains of each film layer, and multiply the failure defect grain percentage of each film layer by a median That is, the yield loss 103 of the film layer, and the yield loss of each film layer is accumulated as the yield loss 104 of the batch of wafers. In summary, the present invention first uses artificial defect classification and electrical test junctions to compare stacks, grants fatal (four) rates, and then uses weekly fixed time to analyze wafer defect data obtained from various types of defects, and utilizes these crystals. The round defect data is converted into defect data of each film layer by a simple time weight conversion, and the yield of the wafer is known. In addition, the invention uses fewer parameters in the calculation and calculates the actual number of defects on the wafer, so that errors caused by external disturbances can be avoided and can be applied to different machines. Calculate the wafer yield loss in a less time-consuming and accurate way. It does not require the use of expensive commercial kit software, thus reducing the production cost. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. [Simple description of the diagram] Figure 1 is a schematic diagram of the weekly wafer defect data calculation of the present invention, showing the percentage of sampling defects per week, which is converted into the number of failed particles. FIG. 2 is a flow chart of a method for calculating wafer yield loss according to an embodiment of the invention. [Explanation of main component symbols] 101~104 ··Steps Ο 10