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TW200848558A - Gallium nitride substrate and gallium nitride film deposition method - Google Patents

Gallium nitride substrate and gallium nitride film deposition method Download PDF

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Publication number
TW200848558A
TW200848558A TW097114534A TW97114534A TW200848558A TW 200848558 A TW200848558 A TW 200848558A TW 097114534 A TW097114534 A TW 097114534A TW 97114534 A TW97114534 A TW 97114534A TW 200848558 A TW200848558 A TW 200848558A
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gallium nitride
layer
substrate
nitride layer
gan layer
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TW097114534A
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Seiji Nakahata
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Sumitomo Electric Industries
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02389—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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  • Crystallography & Structural Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Materials Engineering (AREA)
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  • Junction Field-Effect Transistors (AREA)
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Abstract

Affords high-carrier-concentration, low-cracking-incidence gallium nitride substrates and methods of forming gallium nitride films. A gallium nitride film 52 in which the carrier concentration is 1 x 10<SP>17</SP> cm<SP>-3</SP> or more is created. Initially, a gallium nitride layer 51 including an n-type dopant is formed onto a substrate 50. Then, the gallium nitride layer 51 formed on the substrate 50 is heated to form a gallium nitride film 52.

Description

200848558 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種氮化鎵基板及氮化鎵層之形成方法。 【先前技術】 包含氧或矽等η型摻雜物之η型氮化鎵基板已為眾所周知 (參照曰本專利特開2000-44400號公報）。該氮化鎵基板之 載子濃度為 lxlO16 cm·3〜lxl02G cm-3。 【發明内容】200848558 IX. Description of the Invention: [Technical Field] The present invention relates to a method for forming a gallium nitride substrate and a gallium nitride layer. [Prior Art] An n-type gallium nitride substrate containing an n-type dopant such as oxygen or ruthenium is known (refer to Japanese Laid-Open Patent Publication No. 2000-44400). The gallium nitride substrate has a carrier concentration of lxlO16 cm·3 to lxl02G cm-3. [Summary of the Invention]

[發明所欲解決之問題] 然而，如上述氮化鎵基板般，若為了提高載子濃度而提 高η型摻雜物濃度，則存在氮化鎵結晶變脆之傾向。因此 會導致氮化鎵基板之製造步驟或者使用氮化鎵基板之磊晶 成長步驟、元件形成步驟中之裂痕發生率變高。若氮化鎵 基板上產生裂痕，則會成為不合格品。因此，氮化録基板 及使用氮化鎵基板之蟲晶、元件之製造良率尚存在提高餘 本發明❹於上述情況而開發者，其目的在於提供一種 載子濃度較高、裂痕發生率較低之氮化鎵基板及氮 之形成方法。 曰 [解決問題之技術手段] 為了解決上述課題，本發明之氮化嫁層之 子濃度為1 X 1 Ω17 -3 /成方法係载 括上之氮化鎵層之形成方法，且包 、土板上形纟包含η型推雜物之氮 及將上述基板上所形成之上述氮化録層加熱 130592.doc 200848558 本發明之氮化鎵層之形成方法中，可藉由對包含n型摻 雜物之氮化鎵層進行加熱，而形成裂痕發生率低之氮化嫁 層。其原因尚未明# ’但可考慮如下方面。n型摻雜物於 含有鎵（Ga)及氮（N)之晶格間以較高機率存在，使結晶產 生應變。若對氮化鎵層進行加熱，則存在於晶格間之η型 摻雜物會移動至Ga位點或Ν位點。其結果，氮化鎵層之裂 痕發生率降低。又，氮化鎵層之載子濃度變高，達到 1 x 1017 cm-3 以上。 r \[Problems to be Solved by the Invention] However, as in the case of the above gallium nitride substrate, if the concentration of the n-type dopant is increased in order to increase the concentration of the carrier, the gallium nitride crystal tends to become brittle. Therefore, the manufacturing steps of the gallium nitride substrate or the epitaxial growth step using the gallium nitride substrate and the crack occurrence rate in the element forming step become high. If a crack occurs on the gallium nitride substrate, it will become a defective product. Therefore, there has been an increase in the yield of the nitride substrate and the device using the gallium nitride substrate, and the developer has developed the above-mentioned situation. The object of the invention is to provide a carrier having a high concentration and a crack occurrence rate. Low gallium nitride substrate and method of forming nitrogen.曰 [Technical means for solving the problem] In order to solve the above problems, the sub-concentration of the nitrided layer of the present invention is 1 X 1 Ω 17 -3 / forming method is a method for forming a gallium nitride layer, and a package, a soil plate The upper shape includes the nitrogen of the n-type dopant and the heating of the nitride layer formed on the substrate 130592.doc 200848558 The method for forming the gallium nitride layer of the present invention can be performed by including n-type doping The gallium nitride layer of the material is heated to form a nitrided layer having a low crack occurrence rate. The reason for this is not yet clear. However, the following aspects can be considered. The n-type dopant exists at a high probability between the crystal lattice containing gallium (Ga) and nitrogen (N), causing strain of the crystal. When the gallium nitride layer is heated, the n-type dopant existing between the crystal lattices moves to the Ga site or the germanium site. As a result, the incidence of cracks in the gallium nitride layer is lowered. Further, the carrier concentration of the gallium nitride layer is increased to 1 x 1017 cm-3 or more. r \

土又，較好較，以80(rc以上溫度加熱上述氣化錄層5分 釦以上。此時，可使裂痕之發生率更低。 广較好的是’以和分鐘以下之降溫速度加熱上述 亂化鎵層。此時，可使裂痕之發生率更低。 又較好的疋，上述氮化鎵層之表面自上述氮化録層之 ⑽〇1)面傾斜0·03。以上。此時，可使裂痕發生率更低。其 原因尚不明確，作可老麿4 τ考慮如下方面。於氮化鎵層之表面形 成有微細階差。η型摻雜物自該階差之角填充進去，因此 易於進入Ga位點或叫立點。1 率降低。 …果鼠化銥層之裂痕發生 又’較好的是’上述氮化鎵層之位錯密度為… 以下。於該情形時，可#裂 確，&quot;考产… 發生率更低。其原因尚不明 &quot;二一= 通常，n型摻雜物易於集中於位 …二此：n型摻雜物集中於特定場所，則裂痕發 以下：則於氮化:二氮化鎵層之位錯密度為lxl〇、_2 ^ η型摻雜物分散於整個層中。因 130592.doc 200848558 此’裂痕發生率降低。 曲本發明之氮化鎵層之形成方法，包括於基板上形成載子 濃度為1 X 1 017 c m -3以上且包含n型摻雜物之氮化鎵層之步 驟，上述氮化鎵層之表面自上述氮化鎵層之（0001)面傾斜 0.03°以上。 本發明之氮化鎵層之形成方法中，可形成裂痕發生率較 低之氮化鎵層。其原因尚不明確，但可考慮如下方面。於 氮化鎵層之表面形成有微細階差。η型摻雜物自該階差之 角填充進去，因此易於進入Ga位點或Ν位點。其結果為， 使氮化鎵層之裂痕發生率降低。又，氮化鎵層之載子濃度 變高，達到lxio17 cnT3以上。 又，較好的是，上述氮化鎵層之位錯密度為1&gt;&lt;1〇7 em_2 以下。於該情形時，可使裂痕發生率更低。其原因尚不明 確，但可考慮如下方面。通常，—摻雜物易於集中於位 錯附近之空間，若η型摻雜物集中於特定場所，則裂痕發 生率會變高。此處，氮化鎵層之位錯密度為ΐχΐ〇7 cm·2以 下，則於氮化鎵層中，η型摻雜物分散於整個層中。因 此，使裂痕發生率降低。 本發明之氮化鎵基板中’該氮化鎵基板之載子濃度為 1Χ1017 cm-3以上，且包含_摻雜物，並具有自該氮化嫁 基板之（0001)面傾斜0.03。以上之表面。 本發明之氮化鎵基板之載子濃度較高為1χ1〇1?⑽^以 上。又，本發明之氮化鎵基板之裂痕發生率較低。其原因 尚不明確’但可認為藉由傾斜GG3。以上，而使_階段性 130592.doc 200848558 成長，使Si易於進入Ga位點’ 〇易於進入N位點，因此使 得結晶之應變變少。 又，較好的是，該氮化鎵基板之位錯密度為lxlO7 cm-2 以下。於該情形時，可使裂痕發生率更低。其原因尚不明 確，但可考慮如下方面。通常，η型摻雜物易於集中於位 錯附近之空間，若η型摻雜物集中於特定場所，則裂痕發 生率變高。此處，氮化鎵層之位錯密度為lxl07 cm·2以 下，則於氮化鎵層中η型摻雜物分散於整個層中。因此， 使裂痕發生率降低。 [發明之效果] 根據本發明，提供一種載子濃度較高且裂痕發生率較低 之氮化鎵基板及氮化鎵層之形成方法。 【實施方式】 以下，一面參照隨附圖式一面對本發明之實施形態進行 詳細說明。再者，於圖式之說明中，對相同或同等之要素 使用相同符號，並省略重複說明。 圖1係模式性表示用以於基板上形成包含 η型摻雜物之氮 化鎵層之氫化物VPE(VapGr Phase Epitaxy，氣相蟲晶）裝置 之圖。圖1所示之氫化物VPE裝置10包括：成長爐12,其 收納用以使氮化鎵層5 1成長之基板5〇 保持基板5 0。 及晶座14，其用以 於成長爐12中連接有將νη3氣體G 氮供給源3 0。 供給至成長爐12内之The soil is better, and it is better to heat the above gasification recording layer by more than 80 rc or above. At this time, the incidence of cracks can be made lower. It is better to heat at a cooling rate below and below the minute. In the above, the gallium layer is disordered. In this case, the incidence of cracks can be made lower. Further, the surface of the gallium nitride layer is inclined by 0·03 from the (10) 〇 1) surface of the nitride recording layer. the above. At this time, the incidence of cracks can be made lower. The reason for this is not clear, and the following can be considered. A fine step is formed on the surface of the gallium nitride layer. The n-type dopant is filled in from the angle of the step, so that it is easy to enter the Ga site or the standpoint. 1 rate is reduced. ... the occurrence of cracks in the ruthenium layer of the rat. It is preferable that the dislocation density of the gallium nitride layer is ... or less. In this case, it can be cracked, and the rate of occurrence is lower. The reason is not clear. "Two n-type dopants are easy to concentrate on the position... Two: the n-type dopants are concentrated in a specific place, then the cracks are below: then in the nitridation: gallium nitride layer The dislocation density is 1xl 〇, _2 ^ η type dopant dispersed in the entire layer. Because of 130592.doc 200848558 this 'fracture rate is reduced. The method for forming a gallium nitride layer according to the present invention includes the step of forming a gallium nitride layer having a carrier concentration of 1×1 017 cm −3 or more and including an n-type dopant on the substrate, wherein the gallium nitride layer is The surface is inclined by 0.03 or more from the (0001) plane of the gallium nitride layer. In the method for forming a gallium nitride layer of the present invention, a gallium nitride layer having a low crack occurrence rate can be formed. The reason is not clear, but the following aspects can be considered. A fine step is formed on the surface of the gallium nitride layer. The n-type dopant is filled in from the angle of the step, so that it is easy to enter the Ga site or the germanium site. As a result, the occurrence rate of cracks in the gallium nitride layer is lowered. Further, the carrier concentration of the gallium nitride layer becomes high, reaching lxio17 cnT3 or more. Further, it is preferable that the dislocation density of the gallium nitride layer is 1 &gt;&lt; 1 〇 7 em_2 or less. In this case, the incidence of cracks can be made lower. The reason is not clear, but the following aspects can be considered. Generally, the dopant tends to concentrate in the space near the dislocation, and if the n-type dopant is concentrated in a specific place, the crack occurrence rate becomes high. Here, the dislocation density of the gallium nitride layer is ΐχΐ〇7 cm·2 or less, and in the gallium nitride layer, the n-type dopant is dispersed throughout the layer. Therefore, the incidence of cracks is lowered. In the gallium nitride substrate of the present invention, the gallium nitride substrate has a carrier concentration of 1 Χ 1017 cm -3 or more, and contains a dopant, and has a tilt of 0.03 from the (0001) plane of the nitrided substrate. The above surface. The gallium nitride substrate of the present invention has a carrier concentration of at most 1 χ 1 〇 1 Å (10) Å or more. Further, the gallium nitride substrate of the present invention has a low incidence of cracks. The reason for this is not clear 'but it can be considered by tilting GG3. In the above, the growth of the _stage 130592.doc 200848558 makes it easy for Si to enter the Ga site. 〇 It is easy to enter the N site, so that the strain of the crystal is reduced. Further, it is preferable that the gallium nitride substrate has a dislocation density of 1×10 7 cm −2 or less. In this case, the incidence of cracks can be made lower. The reason is not clear, but the following aspects can be considered. In general, the n-type dopant tends to concentrate on the space near the dislocation, and if the n-type dopant is concentrated in a specific place, the crack occurrence rate becomes high. Here, the dislocation density of the gallium nitride layer is lxl07 cm·2 or less, and the n-type dopant is dispersed in the entire layer in the gallium nitride layer. Therefore, the incidence of cracks is lowered. [Effects of the Invention] According to the present invention, there is provided a method of forming a gallium nitride substrate and a gallium nitride layer having a high carrier concentration and a low crack occurrence rate. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same or equivalent elements are designated by the same reference numerals, and the repeated description is omitted. Fig. 1 is a view schematically showing a hydride VPE (VapGr Phase Epitaxy) device for forming a gallium nitride layer containing an n-type dopant on a substrate. The hydride VPE apparatus 10 shown in Fig. 1 includes a growth furnace 12 that houses a substrate 5 that holds the gallium nitride layer 51 and holds the substrate 50. And a crystal holder 14 for connecting the νη3 gas G nitrogen supply source 30 to the growth furnace 12. Supply to the growth furnace 12

。鎵供給源16係例如收納有金屬鎵 給至成 長爐12内之鎵供給源丨6。鎵供 130592.doc 200848558 之供給源容器。於鎵供給源16中連接有供給用以與金屬鎵 反應之HC1氣體gh之HC1供給源28。於鎵供給源16中，安 裝有用以對金屬鎵及HC1氣體Gh進行加熱之加熱器18。利 用加熱斋18，將鎵供給源丨6維持於例如8〇〇。〇以上。藉由 使金屬鎵與HC1氣體Gh於高溫下進行反應，而生成例如 GaCl等含鎵氣體Gg。以下表示化學反應式之一例。 2Ga(l)+2HCl(g)-&gt;2GaCl(g)+H2(g) 於成長爐12中，連接有供給例如含有諸如二氯矽烷之矽 烧化&amp;物之含;δ夕氣體Gs之石夕供給源24。作為含石夕氣體gs， 例如可列舉使SiH4、siH3C1、、SiHC^、sicu等氣 體或粒狀Si與HC1反應之方法，或者使以〇2與HCl或NH3反 應之方法等。 又’於成長爐12中，亦可連接著供給例如〇2等含氧氣體 G〇之氧供給源26。將含石夕氣體Gs及含氧氣體G〇中之至少 一者供給至成長爐12内。 於成長爐12之周圍安裝有加熱器32，該加熱器32用以對 NH3氣體Gn、含鎵氣體gg、含矽氣體Gs、及含氧氣體〇〇進 行加熱。於加熱器32中連接有監測基板50之溫度之控制裝 置34。控制裝置34控制加熱器32以使基板5〇之溫度維持於 特疋溫度。藉由使NH3氣體GN、含鎵氣體Gg、含矽氣體 Gs、及含氧氣體G〇於高溫下反應，而於基板5〇上形成包含 η型摻雜物之氮化鎵層5 1。以下表示化學反應式之一例。 GaCl(g)+NH3(g)-&gt;GaN(s)+HCl(g)+H2(g) 圖2A〜圖2D係模式性表示實施形態之氮化鎵層之形成方 130592.doc 200848558 法、使用該氮化鎵層的氮化鎵基板之製造方法、及使用該 氮化鎵基板之磊晶基板之製造方法的步驟圖。 首先’於圖1所示之氫化物VPE裝置10之晶座14上載置 基板50。其次，如圖2A所示，使用氫化物VPE裝置10，於 基板50上形成包含n型摻雜物之^型氮化鎵層52。其次，如 圖2Β所示，藉由去除基板5〇，而獲得可自行支撐之氮化鎵 層52 °其次’如圖2C所示，使用例如内圓切割刀對氮化鎵 層52進行切片，藉此製造可自行支撐之複數個氮化鎵基板 5 4 °較好的是’對氮化鎵層5 2進行切片後，對氮化鎵基板 54進行研磨、拋光。較好的是，氮化鎵基板54之厚度為 100 μηι以上。 其次，如圖2D所示，於氮化鎵基板54上，依次形成氮化 物半導體層56、58、60,藉此製造磊晶基板62。氮化物半 導體層 56、58、60為例如 AlxInYGal-X-YN 層（0SXS1， 〇 $ Y $ 1)。蟲晶基板62例如用於電子元件、光學元件等。 作為電子元件，例如可列舉場效電晶體等。作為光學元 件例如可列舉半導體雷射、LED(light emitting diode， 發光二極體）等。 (第1實施形態） 第1實施形態之氮化鎵層之形成方法以如下方式實施。 首先，使用圖1所示之氫化物VPE裝置10，於基板50上 成υ δ例如石夕、氧等n型摻雜物之氮化鎵層5 1。停止供 f例如HC1氣體，以使氮化鎵層51之成長結束。較好的 疋，形成氮化鎵層51時之基板50之溫度（成長溫度）為 130592.doc -10- 200848558 92H25CTC。於該情形時’能夠獲得結晶缺陷較少之優質 氮化鎵層51。成長時間例如為1小時。皿3氣體Gn之分壓 例如為15200 Pa。HC1氣體Gh之分壓例如為3〇4 。 作為基板50，例如可列舉藍寶石基板、氮化嫁基板、 GaAs基板、SiC基板、Gap基板、Inp基板等。較好的是， 藍寶石基板、SiC基板之成長面為（〇〇〇1)面。較好的是，. The gallium supply source 16 is, for example, a metal gallium contained therein and supplied to the gallium supply source 6 in the growth furnace 12. Gallium supply 130592.doc 200848558 supply source container. An HC1 supply source 28 for supplying an HC1 gas gh for reacting with metal gallium is connected to the gallium supply source 16. A heater 18 for heating the metal gallium and the HC1 gas Gh is mounted in the gallium supply source 16. The gallium supply source 丨6 is maintained at, for example, 8 Torr by heating. 〇 Above. The gallium-containing gas Gg such as GaCl is formed by reacting metal gallium with the HC1 gas Gh at a high temperature. An example of a chemical reaction formula is shown below. 2Ga(l)+2HCl(g)-&gt;2GaCl(g)+H2(g) is connected to the growth furnace 12, and is supplied with, for example, a strontium-containing gas such as dichloromethane; Shi Xi supply source 24. Examples of the gas-containing gas gs include a method of reacting a gas such as SiH4, siH3C1, SiHC, or sicu or granular Si with HCl, or a method of reacting ruthenium 2 with HCl or NH3. Further, in the growth furnace 12, an oxygen supply source 26 for supplying an oxygen-containing gas G? such as helium 2 may be connected. At least one of the gas-containing gas Gs and the oxygen-containing gas G is supplied to the growth furnace 12. A heater 32 for heating the NH3 gas Gn, the gallium-containing gas gg, the helium-containing gas Gs, and the oxygen-containing gas is attached around the growth furnace 12. A control device 34 for monitoring the temperature of the substrate 50 is connected to the heater 32. The control unit 34 controls the heater 32 to maintain the temperature of the substrate 5〇 at the temperature. The gallium nitride layer 51 including the n-type dopant is formed on the substrate 5 by reacting the NH3 gas GN, the gallium-containing gas Gg, the helium-containing gas Gs, and the oxygen-containing gas G at a high temperature. An example of a chemical reaction formula is shown below. GaCl(g)+NH3(g)-&gt;GaN(s)+HCl(g)+H2(g) FIG. 2A to FIG. 2D schematically show the formation of the gallium nitride layer of the embodiment 130592.doc 200848558 A method of manufacturing a gallium nitride substrate using the gallium nitride layer and a step of manufacturing a epitaxial substrate using the gallium nitride substrate. First, the substrate 50 is placed on the crystal holder 14 of the hydride VPE apparatus 10 shown in Fig. 1. Next, as shown in Fig. 2A, a GaN layer 52 containing an n-type dopant is formed on the substrate 50 using the hydride VPE device 10. Next, as shown in FIG. 2A, a self-supporting gallium nitride layer 52 is obtained by removing the substrate 5A. Next, as shown in FIG. 2C, the gallium nitride layer 52 is sliced using, for example, an inner circular cutting blade. Thereby, a plurality of self-supporting gallium nitride substrates are manufactured at a temperature of 45 °. Preferably, after the gallium nitride layer 52 is sliced, the gallium nitride substrate 54 is polished and polished. Preferably, the gallium nitride substrate 54 has a thickness of 100 μη or more. Next, as shown in Fig. 2D, nitride semiconductor layers 56, 58, and 60 are sequentially formed on the gallium nitride substrate 54, whereby the epitaxial substrate 62 is manufactured. The nitride semiconductor layers 56, 58, 60 are, for example, AlxInYGal-X-YN layers (0SXS1, 〇 $ Y $ 1). The insect crystal substrate 62 is used, for example, for an electronic component, an optical component, or the like. Examples of the electronic component include field effect transistors and the like. Examples of the optical element include a semiconductor laser, an LED (light emitting diode), and the like. (First Embodiment) A method of forming a gallium nitride layer according to the first embodiment is carried out as follows. First, using the hydride VPE apparatus 10 shown in Fig. 1, a gallium nitride layer 51 of an n-type dopant such as a ruthenium or oxygen is formed on the substrate 50. The supply of f, for example, HC1 gas, is stopped to complete the growth of the gallium nitride layer 51. Preferably, the temperature (growth temperature) of the substrate 50 when the gallium nitride layer 51 is formed is 130592.doc -10- 200848558 92H25CTC. In this case, a high-quality gallium nitride layer 51 having less crystal defects can be obtained. For a long time, for example, 1 hour. The partial pressure of the gas Gn of the dish 3 is, for example, 15200 Pa. The partial pressure of the HC1 gas Gh is, for example, 3〇4. Examples of the substrate 50 include a sapphire substrate, a nitrided substrate, a GaAs substrate, a SiC substrate, a Gap substrate, and an Inp substrate. Preferably, the growth surface of the sapphire substrate or the SiC substrate is a (〇〇〇1) plane. Preferably,

GaAS基板、⑽基板、Inp基板之成長面為⑴1)A面即族The growth surface of the GaAS substrate, the (10) substrate, and the Inp substrate is (1) 1)

面）。當使用氮化鎵基板以外之基板作為基板5〇之情形 時，較好的是，於基板50上形成具有開口圖案之遮罩層r 該遮罩層例如由諸如氧切之絕緣物構成。遮罩層之厚度 例如為1 00 nm。 其次’對基板50上所形成之氮化鎵層“進行加熱(退 火）。藉此，hg!2A所示，可於基板5〇上形成氮化嫁層 52。其次’如圖2B所示，藉由去除基板5〇，而獲得可自行 支撐之氮化鎵層52。氮化鎵層52含有六角晶系⑽單晶。 鼠化鎵層52之厚度例如為7 mm，氮化鎵層52之直徑例 如為5〇 mm。較好的是，對氮化鎵層51進行加熱時基板5〇 之溫度（加熱溫度）為8〇〇〜12〇〇t。較好的是，加熱時間為 5〜300分鐘。加熱時間巾’既可將加熱溢度維持為相同溫 度，亦可逐漸降溫。 較好的是，氮化鎵層52之載子濃度為1χ1〇17 cm」以上， 更好的是為5χΐ0ΐ9 cm-3以下。可藉由使例如氮化鎵層w之 11型摻雜物濃度變高，而提高氮化鎵層52之載子濃度。氮 化鎵層52之载子濃度！|纟電洞《則定進行測定。較好的是: 130592.doc 200848558 虱化鎵層52之厚度為loo μηι以上，更好的是為4〇〇叫^以 上。 較好的是，氮化鎵層52in型摻雜物濃度為扒1〇17 cm_3 以上5xl〇i9 cm-3以下。若n型摻雜物濃度為該範圍内，則 可抑制因添加大量η型摻雜物而引起之結晶性劣化。氮化 鎵層52之η型摻雜物濃度藉由SIMS(Sec〇ndary ζ⑽Mass Spectrometry ’二次離子質譜儀）來測定。 再者，於形成氮化鎵層51之前，亦可於基板5〇上形成包 含氮化鎵之緩衝層。緩衝層之厚度例如為6〇 nm。形成緩 衝層時基板50之溫度例如為5〇(rc。若形成緩衝層，則可 使氮化鎵層5 1之結晶性提高。 本貫施形態之氮化鎵層之形成方法中，可藉由對氮化鎵 層5 1進行加熱，而形成裂痕發生率較低之氮化鎵層。其 原因尚不明確，但可考慮如下方面。可認為η型摻雜物以 較南機率存在於含有鎵（Ga)及氮之晶格間，因此結晶 會出現應變。若對氮化鎵層51進行加熱，則存在於晶格間 之η型摻雜物會移動至Ga位點或ν位點。其結果，使氮化 鎵層52之裂痕發生率降低。因此，可提高氮化鎵層52之製 造良率。可藉由利用顯微鏡對氮化鎵層52之表面進行觀察 來確認裂痕之產生。又，氮化鎵層52之載子濃度變高，達 到 lxio17 cnT3以上。 此處，上述氮化鎵層52之表面之有無裂痕，具體而言可 藉由利用微分干涉相位差顯微鏡進行觀察而確認。於對結 晶成長結束後之基板5〇之表面、背面、及外周進行加工， 130592.doc 200848558 並實施磊晶成長之前進行裂痕測定。氮化鎵層52之表面觀 察部位係除了各基板外周5 mm以外之整個面，且物鏡之觀 察倍率設定為20倍。當發現裂痕之情形時，若長度為1〇〇 μιη以上之裂痕為10條以上，則視為存在裂痕而判為不合 格，並使之不進入最後之步驟。surface). When a substrate other than the gallium nitride substrate is used as the substrate 5, it is preferable to form the mask layer r having an opening pattern on the substrate 50. The mask layer is made of, for example, an insulator such as oxygen cut. The thickness of the mask layer is, for example, 100 nm. Next, 'the gallium nitride layer formed on the substrate 50 is heated (annealed). Thereby, as shown by hg! 2A, the nitrided layer 52 can be formed on the substrate 5 。. Next, as shown in FIG. 2B, By removing the substrate 5, a self-supporting gallium nitride layer 52 is obtained. The gallium nitride layer 52 contains a hexagonal crystal (10) single crystal. The thickness of the gallium germanium layer 52 is, for example, 7 mm, and the gallium nitride layer 52 The diameter is, for example, 5 mm. Preferably, the temperature (heating temperature) of the substrate 5 is about 8 Torr to 12 Torr when the gallium nitride layer 51 is heated. Preferably, the heating time is 5 〜. 300 minutes. The heating time towel' can maintain the heating temperature at the same temperature or gradually decrease the temperature. Preferably, the carrier concentration of the gallium nitride layer 52 is 1χ1〇17 cm” or more, more preferably 5χΐ0ΐ9 cm-3 or less. The carrier concentration of the gallium nitride layer 52 can be increased by increasing the concentration of the 11-type dopant such as the gallium nitride layer w. The carrier concentration of the gallium nitride layer 52! |纟电洞" is determined to be measured. Preferably, it is: 130592.doc 200848558 The thickness of the gallium antimonide layer 52 is loo μηι or more, and more preferably 4 〇〇. Preferably, the concentration of the 52in-type dopant of the gallium nitride layer is 扒1〇17 cm_3 or more and 5xl〇i9 cm-3 or less. When the n-type dopant concentration is within this range, deterioration in crystallinity due to the addition of a large amount of n-type dopant can be suppressed. The n-type dopant concentration of the gallium nitride layer 52 was measured by SIMS (Sec〇ndary® (10) Mass Spectrometry' secondary ion mass spectrometer). Further, a buffer layer containing gallium nitride may be formed on the substrate 5A before the gallium nitride layer 51 is formed. The thickness of the buffer layer is, for example, 6 〇 nm. When the buffer layer is formed, the temperature of the substrate 50 is, for example, 5 〇 (rc. When a buffer layer is formed, the crystallinity of the gallium nitride layer 51 can be improved. In the method for forming a gallium nitride layer according to the present embodiment, The gallium nitride layer 51 is heated to form a gallium nitride layer having a low crack occurrence rate. The reason for this is not clear, but the following aspects can be considered. It can be considered that the n-type dopant exists in a relatively high probability. Between gallium (Ga) and the crystal lattice of nitrogen, strain occurs in the crystal. If the gallium nitride layer 51 is heated, the n-type dopant existing between the crystal lattices moves to the Ga site or the ν site. As a result, the occurrence rate of cracks in the gallium nitride layer 52 is lowered. Therefore, the production yield of the gallium nitride layer 52 can be improved. The surface of the gallium nitride layer 52 can be observed by a microscope to confirm the occurrence of cracks. Further, the carrier concentration of the gallium nitride layer 52 is increased to 1xio17 cnT3 or more. Here, the surface of the gallium nitride layer 52 is cracked, and specifically, it can be confirmed by observation using a differential interference phase contrast microscope. On the surface of the substrate 5 after the end of crystal growth The back surface and the outer periphery were processed, and the crack was measured before the epitaxial growth was performed. The surface observation portion of the gallium nitride layer 52 was the entire surface except for the outer circumference of each substrate of 5 mm, and the observation magnification of the objective lens was set to 20 When a crack is found, if there are more than 10 cracks having a length of 1 μm or more, it is considered to be a crack and is judged to be unacceptable, and it is not allowed to enter the final step.

又，若以800°C以上溫度對氮化鎵層51加熱5分鐘以上， 則可使裂痕發生率更低。較好的是，以8〇〇〜12〇〇〇c之溫度 對氮化鎵層51加熱5〜300分鐘。進而，若以5〇r/分鐘以下 之降溫速度對氮化鎵層5 1進行加熱，則可使裂痕發生率更 低。較好的是，以超過(rc/分鐘且5(rc/分鐘以下之降溫速 度對氮化鎵層5 1進行加熱。 圖3A及圖3B係表示基板50之溫度之時間變化具體例的 圖表。如圖3A及圖3B所示，自時刻〇至時刻t〇為止一面使 基板50之溫度維持於成長温度。（例如TQ=u〇(rc)，一面於 基板50上形成氮化鎵層51。時刻〇係氮化鎵層51之成長開 始時刻，時刻tQ係氮化鎵層51之成長停止時刻。其次，如 圖3A所示，自時m。至時為止—面㈣t/分❹r 降溫速度使溫度降低，—面對氮化鎵層51進行加敎。藉 此，於基板50上形成氮化鎵層52。於時心，基板別之^ 度降低至退火結束溫度1(例如Ti=5〇〇t)為止。 於基板50上形成氮化鎵層51之後，如圖3b所示，亦可自 時刻t。至時刻t2為止以成長溫度丁。對氮化鎵層Η進行加 熱。繼而，亦可自時刻t2至時刻^為止一面 速度使溫度下降，-面對氮化鎵層51進行加熱。^降於皿 130592.doc 13 200848558 基板50上形成氮化鎵層52。於時刻η，基板5〇之溫度降低 至退火結束溫度T】為止。 於基板50上形成氮化鎵層52之後，經由圖2B及圖2C所 不之各步驟，來製造氮化鎵基板54。氮化鎵基板54之載子 濃度為lxl〇i7 cm_3以上。又，裂痕發生率亦較低。藉由利 用Μ分干涉相位差顯微鏡對氮化鎵基板54之表面進行觀察 來確認裂痕之產生。其後，經由圖2D所示之步驟，來製造 蠢晶基板6 2。Further, when the gallium nitride layer 51 is heated at a temperature of 800 ° C or higher for 5 minutes or more, the crack occurrence rate can be made lower. Preferably, the gallium nitride layer 51 is heated at a temperature of 8 Torr to 12 Torr for 5 to 300 minutes. Further, when the gallium nitride layer 51 is heated at a temperature decreasing rate of 5 Torr/min or less, the crack occurrence rate can be made lower. Preferably, the gallium nitride layer 51 is heated at a temperature exceeding the rate of rc/min and 5 (r/min or less. Fig. 3A and Fig. 3B are graphs showing specific examples of temporal changes in temperature of the substrate 50. As shown in FIGS. 3A and 3B, the temperature of the substrate 50 is maintained at a growth temperature from the time 〇 to the time t〇 (for example, TQ=u〇(rc), the gallium nitride layer 51 is formed on the substrate 50. At the time t2, the growth start timing of the gallium nitride layer 51 is performed, and the time tQ is the growth stop timing of the gallium nitride layer 51. Next, as shown in Fig. 3A, since time m, the time-to-surface (four) t/minute r is lowered. The temperature is lowered, and the gallium nitride layer 51 is twisted. Thereby, the gallium nitride layer 52 is formed on the substrate 50. At the time of the center, the substrate is lowered to the annealing end temperature 1 (for example, Ti = 5 〇). After the gallium nitride layer 51 is formed on the substrate 50, as shown in FIG. 3b, the gallium nitride layer may be heated at a temperature from the time t to the time t2. The temperature can be lowered from the time t2 to the time ^, and the surface of the gallium nitride layer 51 can be heated. .doc 13 200848558 A gallium nitride layer 52 is formed on the substrate 50. At time η, the temperature of the substrate 5 is lowered to the annealing end temperature T. After the gallium nitride layer 52 is formed on the substrate 50, via FIG. 2B and FIG. 2C At any step, the gallium nitride substrate 54 is fabricated. The carrier concentration of the gallium nitride substrate 54 is lxl 〇 i7 cm_3 or more. Further, the incidence of cracks is also low. By using a Μ-interference phase contrast microscope for nitrogen The surface of the gallium substrate 54 was observed to confirm the occurrence of cracks. Thereafter, the stray substrate 62 was fabricated via the procedure shown in Fig. 2D.

(第2實施形態） 第2只^形恶之氮化鎵層之形成方法以如下方式實施。 如圖4所示，使用氫化物vpE裝置1〇，於基板⑼上形成載 子濃度為lxlO17 cm-3以上且包含n型摻雜物之氮化鎵層 52。圖4係表示氮化鎵層之形成步驟之圖◦此處，氮化鎵 層52之表面52a自氮化鎵層52之（〇〇〇1)面（亦稱為「c面」） 傾斜〇.〇3以上。亦即，氮化鎵層52之表面52a與氮化鎵層 52之(〇〇〇1)面所成之角θ(亦稱為「偏離角」）為0.03。以上。 較好的疋，角Θ為〇.5。〜6〇。。角θ藉由χ射線繞射來測定。 亂化鎵層52之表面52a既可為使(0001)面之法線向 &lt;11 20&gt;方向以角帽斜而獲得之面，亦可為使（綱1)面之 法線向&lt;1-1〇〇&gt;方向以角θ傾斜而獲得之面。 基板5〇既可為具有自（0001)面傾斜0.03。以上之表面之氮 化鎵基板，亦可為具有包含⑴1)Α面之表面之_基板、(Second Embodiment) A method of forming a second gallium nitride layer is carried out as follows. As shown in Fig. 4, a gallium nitride layer 52 containing an n-type dopant was formed on the substrate (9) using a hydride vpE device. 4 is a view showing a step of forming a gallium nitride layer. Here, the surface 52a of the gallium nitride layer 52 is inclined from the (〇〇〇1) plane (also referred to as "c-plane") of the gallium nitride layer 52. .〇3 or more. That is, the angle θ (also referred to as "offset angle") formed by the surface 52a of the gallium nitride layer 52 and the (〇〇〇1) plane of the gallium nitride layer 52 is 0.03. the above. A better 疋, the angle Θ is 〇.5. ~6〇. . The angle θ is determined by ray diffraction. The surface 52a of the chaotic gallium layer 52 may be a surface obtained by inclining the normal to the (0001) plane toward the &lt;11 20&gt; direction, or may be a normal to the (1) plane to &lt;1 -1〇〇&gt; The direction obtained by tilting the angle θ. The substrate 5A may have a slope of 0.03 from the (0001) plane. The gallium nitride substrate on the surface may be a substrate having a surface including (1) 1) a surface,

GaP基板、Inp基板箄。 、於，、有包含（ηι)Α面之表面之GaAs 基板等上所形成之氮化鎵層52之表面仏之傾斜角，可以 130592.doc •14- 200848558 式進行控制。若使GaAs(lll)面向&lt;1-1〇&gt;方向傾斜 〇·03 ’則所獲得之GaN結晶之（〇〇〇1)面成為向&lt;11-20〉方向 傾斜0.03。者。里 + τ 另一方面，若使GaAs(l 11)面向&lt;11_2&gt;方向 傾斜0.03 ，則所獲得之GaN結晶之（〇〇〇1)面成為向 方向傾斜0.03。者。進而，若使GaAs(lu)面向&lt;w〇&gt;方向 傾斜〇·03且向&lt;11-2&gt;方向傾斜0.03。，則所獲得之GaN結晶 之（0001)面成為向&lt;n-20&gt;方向傾斜0 03。且向&lt;1-1〇〇&gt;方向 傾斜0.03。者。 本貝施形態之氮化鎵層之形成方法中，可形成裂痕發生 率低之氮化鎵層52。其原因雖不盡明確，但可考慮如下方 面。於氮化鎵層52之表面52a上形成有微細階差。n型摻雜 物自該階差之角填充進去，因此易於進入仏位點或N位 點，其結果為，氮化鎵層52之裂痕發生率降低。因此，可 提高氮化鎵層52之製造良率。又，氮化鎵層52之載子濃度 變高，達到1 X1017 cm·3以上。 形成氮化鎵層52之後，經由圖2B及圖2C所示之各步 驟’來製造氮化蘇基板5 4。 本實施形態之氮化鎵基板54之載子濃度較高，達到 lxlO17 cm·3以上。氮化鎵基板54包含摻雜物。又，裂 痕發生率亦較低。如圖5所示，氮化鎵基板54具有自氮化 鎵基板54之（0001)面傾斜〇.〇3。以上之表面54a。亦即，氣 化鎵基板54之表面54a與氮化鎵基板54之（〇〇〇1)面之所成之 角Θ為0·03。以上。圖5係表示氮化鎵基板之製造步驟之圖。 其後，經由圖2D所示步驟，來製造磊晶基板62。 130592.doc -15- 200848558 本實施形態之氮化鎵基板54亦可以如下方式製造。、， 心 百 先’於基板50上形成使任意結晶面（例如（〇〇〇1)面）為表面 之氮化鎵層5 1。其次，去除基板50之後，沿著自氮化錄層 51之（0001)面傾斜〇.〇3。以上之面，對氮化鎵層51進行切片 或拋光。即便於該情形時，氮化鎵基板54之載子濃度亦較 高，達到lxlO17 cm·3以上，且氮化鎵基板54之裂痕發生率 較低。 於上述第1實施形態或第2實施形態中，較好的是，氮化 鎵層52之位錯密度為ixio7 cm·2以下，較好的是4&gt;&lt;1〇6咖·2 以下，更好的是lxl〇6 cnT2以下。氮化鎵層52之位錯密度 表現為I虫坑密度（EPD : Etch Pits Density)。|虫坑密度藉由 以下方式而异出，即，於任意6處之100 μηι見方内，使用 SEM(Scanning Electron Microscope，掃描式電子顯微鏡） 對#坑數量進行計數。當使用例如位錯密度為丨x丨〇7 cm_2 以下之氮化鎵基板作為基板5 〇時，可使氮化鎵層5 2之位錯 密度為lxlO7 cm·2以下。又，當使用藍寶石基板、GaAs* 板、SiC基板、GaP基板、inp基板等作為基板5〇之情形 時’若於基板50上形成具有開口圖案之遮罩層，並以埋入 該開口圖案之方式形成氮化鎵層52，則可使氮化鎵層52之 位錯密度為1 X 1 〇7 cm·2以下。 若氮化鎵層52之位錯密度為ix 1〇7 cnT2以下，則可形成 裂痕發生率較低之氮化鎵層52。其原因尚不明確，但可考 慮如下方面。通常，n型摻雜物易於集中於位錯附近之空 間’若η型摻雜物集中於特定場所，則會使裂痕發生率變 130592.doc 200848558 南 此處’右氮化錁層52之位錯密度為lxi〇7 cnT2以下， 貝J於氮化鎵層52中，n型摻雜物將分散於整個層中。因 此，裂痕發生率會降低。因此，可提高氮化鎵層52之製造 良率。 形成氮化鎵層52之後，經由圖2Β及圖2C所示之各步 驟，來製造氮化鎵基板54。於該情形時，氮化鎵基板54之 位錯密度為lxl〇7 cm-2以下。又，氮化鎵基板“之裂痕發 生率#乂低。其原因尚不明確，但可考慮如下方面。通常， η型摻雜物易於集中於位錯附近之空間，若n型摻雜物集中 於特定場所，則會使裂痕發生率變高。此處，若氮化鎵基 板54之位錯密度為lxl〇7 cm·2以下，則於氮化鎵基板54 中，η型摻雜物將分散於整個基板中。因此，可使裂痕發 生率降低。 以上，對本發明之較佳實施形態進行了詳細說明，但是 本發明並非限定於上述實施形態。 例如，亦可使用有機金屬氯化氫νρΕ裝置代替氫化物 VPE裝置來形成氮化鎵層52。 又，於第1實施形態中，亦可以第2實施形態之方式，使 氮化鎵層52之表面52a自氮化鎵層52之（〇〇〇1)面傾斜〇〇3。 以上。於該情形時，即便第丨實施形態，亦可獲得與第2實 施形態相同之作用效果。 [實施例1 ] 以下，根據實施例對本發明進行更具體地說明，但是本 發明並非限定於以下實施例。 130592.doc 200848558 圖6係表示參考例卜丨〜參考例卜2、實施例卜卜實施例2_4 中形成GaN層後之實驗結果之圖。 (參考例1-1) 百先，於直徑為50.8 mm之GaN基板上，使成長溫度（τ〇) 為1100 C ’使石夕?辰度為3·〇χΐ〇〗7 cm·3之GaN層成長。於GaN 層成長後，一面以100&lt;^/分鐘之降溫速度使溫度自u〇(rc 降低至500 C為止一面對GaN層實施退火6分鐘。GaP substrate, Inp substrate 箄. The inclination angle of the surface of the gallium nitride layer 52 formed on the GaAs substrate or the like having the surface of the (ηι) surface can be controlled by the formula 130592.doc •14-200848558. When GaAs (111) is tilted toward the &lt;1-1〇&gt; direction 〇·03 ', the (〇〇〇1) plane of the GaN crystal obtained is inclined by 0.03 in the &lt;11-20&gt; direction. By.里 + τ On the other hand, if GaAs (11) is inclined by 0.03 in the &lt;11_2&gt; direction, the (〇〇〇1) plane of the obtained GaN crystal is inclined by 0.03 in the direction. By. Further, GaAs (lu) is inclined by 〇·03 in the &lt;w〇&gt; direction and is inclined by 0.03 in the &lt;11-2&gt; direction. Then, the (0001) plane of the obtained GaN crystal is inclined to 0 03 in the &lt;n-20&gt; direction. And it is inclined to 0.03 in the direction of &lt;1-1〇〇&gt;. By. In the method of forming a gallium nitride layer of the present embodiment, a gallium nitride layer 52 having a low crack occurrence rate can be formed. Although the reasons are not clear, the following aspects can be considered. A fine step is formed on the surface 52a of the gallium nitride layer 52. The n-type dopant is filled in from the angle of the step, so that it is easy to enter the germanium site or the N site, and as a result, the incidence of cracks in the gallium nitride layer 52 is lowered. Therefore, the manufacturing yield of the gallium nitride layer 52 can be improved. Further, the carrier concentration of the gallium nitride layer 52 is increased to 1 × 10 17 cm·3 or more. After the gallium nitride layer 52 is formed, the nitrided substrate 51 is fabricated through the steps '' shown in Figs. 2B and 2C. The gallium nitride substrate 54 of the present embodiment has a high carrier concentration of lxlO17 cm·3 or more. The gallium nitride substrate 54 contains a dopant. Also, the incidence of cracks is low. As shown in Fig. 5, the gallium nitride substrate 54 has a (0001) plane tilt from the gallium nitride substrate 54. The above surface 54a. That is, the angle Θ formed by the surface 54a of the gallium nitride substrate 54 and the (〇〇〇1) plane of the gallium nitride substrate 54 is 0·03. the above. Fig. 5 is a view showing a manufacturing step of a gallium nitride substrate. Thereafter, the epitaxial substrate 62 is fabricated through the steps shown in FIG. 2D. 130592.doc -15- 200848558 The gallium nitride substrate 54 of the present embodiment can also be manufactured as follows. A gallium nitride layer 51 having a crystal face (for example, a (〇〇〇1) plane) as a surface is formed on the substrate 50. Next, after the substrate 50 is removed, 〇.〇3 is inclined along the (0001) plane of the nitride recording layer 51. In the above, the gallium nitride layer 51 is sliced or polished. That is, in this case, the carrier concentration of the gallium nitride substrate 54 is also high, reaching lxlO17 cm·3 or more, and the occurrence rate of cracks of the gallium nitride substrate 54 is low. In the first embodiment or the second embodiment, it is preferable that the dislocation density of the gallium nitride layer 52 is ixio 7 cm·2 or less, preferably 4 &lt;1〇6 coffee·2 or less. More preferably, lxl〇6 cnT2 or less. The dislocation density of the gallium nitride layer 52 is expressed as Ip pit density (EPD: Etch Pits Density). The wormhole density differs by the following method, that is, the number of #坑s is counted using an SEM (Scanning Electron Microscope) at 100 μηι square in any of the six places. When a gallium nitride substrate having a dislocation density of 丨 x 丨〇 7 cm 2 or less is used as the substrate 5 ,, the dislocation density of the gallium nitride layer 5 2 can be made lxlO7 cm·2 or less. When a sapphire substrate, a GaAs* plate, a SiC substrate, a GaP substrate, an inp substrate, or the like is used as the substrate 5, a mask layer having an opening pattern is formed on the substrate 50, and the opening pattern is buried. By forming the gallium nitride layer 52 in a manner, the dislocation density of the gallium nitride layer 52 can be 1 × 1 〇 7 cm·2 or less. If the dislocation density of the gallium nitride layer 52 is ix 1 〇 7 cnT2 or less, the gallium nitride layer 52 having a low crack occurrence rate can be formed. The reason is not clear, but the following aspects can be considered. In general, n-type dopants tend to concentrate in the space near the dislocations. If the n-type dopants are concentrated in a specific place, the incidence of cracks will be changed to 130592.doc 200848558 South here is the position of 'right tantalum nitride layer 52 The error density is below xxi〇7 cnT2, and in the gallium nitride layer 52, the n-type dopant will be dispersed throughout the layer. Therefore, the incidence of cracks will decrease. Therefore, the manufacturing yield of the gallium nitride layer 52 can be improved. After the gallium nitride layer 52 is formed, the gallium nitride substrate 54 is fabricated through the steps shown in Figs. 2A and 2C. In this case, the dislocation density of the gallium nitride substrate 54 is 1 x 10 〇 7 cm -2 or less. Further, the gallium nitride substrate "the crack occurrence rate is low. The reason for this is not clear, but the following aspects can be considered. Generally, the n-type dopant tends to concentrate in the space near the dislocations, if the n-type dopant is concentrated. In a specific place, the incidence of cracks is increased. Here, if the dislocation density of the gallium nitride substrate 54 is lxl 〇 7 cm·2 or less, the n-type dopant will be in the gallium nitride substrate 54. The preferred embodiment of the present invention has been described in detail with reference to the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiment. For example, an organometallic hydrogen chloride νρΕ device may be used instead. In the hydride VPE device, the gallium nitride layer 52 is formed. Further, in the first embodiment, the surface 52a of the gallium nitride layer 52 may be formed from the gallium nitride layer 52 as in the second embodiment. 1) The surface is inclined to 〇〇 3. In this case, even in the case of the second embodiment, the same operational effects as those of the second embodiment can be obtained. [Embodiment 1] Hereinafter, the present invention will be more specifically carried out according to the embodiment. Description, but this The invention is not limited to the following examples. 130592.doc 200848558 Fig. 6 is a view showing experimental results of forming a GaN layer in Reference Example 2 to Reference Example 2, Example Example 2_4 (Reference Example 1-1) ) On the GaN substrate with a diameter of 50.8 mm, the growth temperature (τ〇) is 1100 C ', and the GaN layer with a thickness of 3 〇χΐ〇 7 cm·3 is grown on the GaN layer. After the growth, the GaN layer was annealed for 6 minutes by reducing the temperature from u〇(rc to 500 C) at a temperature drop rate of 100 ° ^ / min.

GaN層之表面為使（〇〇〇1)面之法線向 &lt;丨UR方向傾斜 0.01 ，且向&lt;1-100&gt;方向傾斜〇 〇1。而獲得之面。GaN層之 位錯密度為5.0x1 〇7 cnT2。The surface of the GaN layer is such that the normal to the (〇〇〇1) plane is inclined by 0.01 to the &lt;丨 UR direction, and is inclined to &1 in the &lt;1-100&gt; direction. And get the face. The dislocation density of the GaN layer is 5.0x1 〇7 cnT2.

GaN層之載子濃度為l.OxlO17 cm-3(活化率：33%)。於 GaN層中未產生裂痕之比例（亦即層之製造良率）為 68%(樣A數量為1〇〇個）。χ，利用探針式形狀測定裝置測 定未產生裂痕之結晶之曲率半徑，結果平均為85⑽。曲 率半徑與結晶應變存在密切關係，曲率半徑越小，則結晶 »亦即可認心進入晶格間。再者，該曲率半 徑表示結晶之偏離角於基板内存在分布之情形，曲率半徑 越大，則基板内之偏離角之分布越小。 (參考例1-2) 除了使石夕濃度為5.0x10】9cm-3以外，以與參考例Μ相同 之方式，形成GaN層。載子濃度、活化率及良率如圖㈣ 丁又未產生裂痕之結晶之曲率半徑平均為咖。 (實施例1-1〜實施例1-10)The carrier concentration of the GaN layer was 1.0×10 17 cm −3 (activation rate: 33%). The ratio of no cracks in the GaN layer (i.e., the manufacturing yield of the layer) was 68% (the number of sample A was 1 unit). Then, the radius of curvature of the crystal which did not generate cracks was measured by a probe shape measuring device, and the average value was 85 (10). The curvature radius is closely related to the crystal strain. The smaller the radius of curvature, the more the crystals can enter the lattice. Further, the radius of curvature indicates a case where the deviation angle of the crystal is present in the substrate, and the larger the radius of curvature, the smaller the distribution of the off angle in the substrate. (Reference Example 1-2) A GaN layer was formed in the same manner as in Reference Example except that the concentration was 5.0 x 10] 9 cm-3. The concentration of the carrier, the activation rate and the yield are shown in Fig. 4. The average radius of curvature of the crystals with no cracks is the average. (Example 1-1 to Example 1-10)

於實施例1_1〜實施例W 刀⑺耵具有兩種矽濃度之 130592.doc -18- 200848558In Example 1_1~Example W, the knife (7) has two concentrations of germanium. 130592.doc -18- 200848558

GaN層，改變降溫速度進行實驗。 於貝施例1-1中，除了使降溫速度為5〇。〇/分鐘，使退火 時間為12分鐘以外，以與參考例^丨相同之方式，形成GaN 層。载子濃度、活化率及良率如圖6所示。 於實施例1-2〜實施例！-；[〇中，除了根據需要改變矽濃 度、降溫速度、退火時間以外，以與實施例U相同之方 式，形成GaN層。載子濃度、活化率及良率如圖6所示。The GaN layer was tested by changing the temperature drop rate. In Example 1-1, in addition to the cooling rate of 5 〇. The GaN layer was formed in the same manner as in the reference example except that the annealing time was 12 minutes. The carrier concentration, activation rate and yield are shown in Fig. 6. In the examples 1-2 to the examples! - [In the crucible, a GaN layer was formed in the same manner as in Example U except that the niobium concentration, the temperature drop rate, and the annealing time were changed as needed. The carrier concentration, activation rate and yield are shown in Fig. 6.

(貝加例2 -1〜實施例2 _ 4 ) 於實施例2-1〜實施例2_4中，分別對具有兩種石夕濃度之 GaN層，改變成長溫度（Tq)進行實驗。 於實施例2-1中，除了使成長溫度（T0)為1050t，使退火 時間為11分鐘以外’以與實施例1]相同之方式，形成GaN 層。載子濃度、活化率及良率如圖6所示。 於實施例2-2〜實施例2_4中，除了根據需要改變矽濃 度、成長溫度（T°)、退火時間以外，以與實施例2·1相同之 方式’形成⑽層。載子濃度、活化率及良率如圖6所 不 。 圖7係表示實施例弘丨〜實 結果之圖。 施例3-2中形成GaN層 後之實驗 (實施例〜實施例3-2) 於實施例3-1〜實施例3_2中，分別 ㈣層，改變退火條件進行實驗。 對具有兩種矽濃度之 與:U 1中冑㈣層成長之後’以11GG°C對GaN層 實施退火5分鐘，豆接 曰 /、 —面以100°c/分鐘之降溫速度自 130592.doc -19. 200848558 η 〇〇 C使溫度降低，一面對GaN層進一步實施退火6分鐘， 除此以外，以與實施例i-i相同之方式，形成GaN層。載子 浪度、活化率及良率如圖7所示。 於實施例3_2中，除了使矽濃度為5·〇χ1〇19 cm-3以外，以 與實施例3-1相同之方式，形成GaN層。載子濃度、活化率 及良率如圖7所示。 圖8係表示實施例4-1〜實施例4-54中形成GaN層後之實驗 結果之圖。 (實施例4-1〜實施例4-54) 於實施例4-1〜實施例4-54中，分別對具有兩種矽濃度之 GaN層，改變GaN層之表面偏離角，進行實驗。 於實施例4-1中，使降溫速度為6(rc/分鐘，使退火時間 為1〇分鐘，使GaN層之表面為GaN層之（〇〇〇1)面法線向以^ 2〇&gt;方向傾斜0·03。之面，除此以外，以與實施例丨_丨相同之 方式，形成GaN層。載子濃度、活化率及良率如圖8所 示。 於實施例4-2〜實施例4_54中，除了根據需要改變石夕濃 度、偏離角以夕卜以與實施例4-1相同之方式，形成⑽ 層。载子濃度、活化率及良率如圖8所示。 圖9係表不實施例5_1〜實施例Η中形成GaN層後之實驗 結果之圖。 (實施例5-1〜實施例5-8) 於實施例5-1〜實施例5_8中’分別對具有兩種矽濃度之 GaN層，改變GaN層之位錯密度後進行實驗。 130592.doc -20. 200848558 於實施例5-1中，除了使降溫速度為6(rc/分鐘，使退火 以外，以與實 、活化率及良 時間為10分鐘，使位錯密度gLOxiO7 cm·2 方也例1 -1相同之方式’形成G aN層。載子濃度 率如圖9所示。 於實施例5-2〜實施例5-8中，除了根據需要改變珍濃 度、位錯密度以外，以與實施例5-1相同之方式，形成 層。載子濃度、活化率及良率如圖9所示。(Belgian Example 2 -1 to Example 2 _ 4 ) In Examples 2-1 to 2_4, experiments were carried out for changing the growth temperature (Tq) of the GaN layer having two concentrations of celestial. In Example 2-1, a GaN layer was formed in the same manner as in Example 1 except that the growth temperature (T0) was 1050 t and the annealing time was 11 minutes. The carrier concentration, activation rate and yield are shown in Fig. 6. In Example 2-2 to Example 2_4, the layer (10) was formed in the same manner as in Example 2-1 except that the enthalpy concentration, the growth temperature (T°), and the annealing time were changed as needed. The carrier concentration, activation rate and yield are shown in Figure 6. Fig. 7 is a view showing the results of the embodiment of the 丨~~ real result. Experiment after forming a GaN layer in Example 3-2 (Examples to Examples 3-2) In Examples 3-1 to 3-2, experiments were carried out by changing the annealing conditions in each of the layers (4). For the relationship between the two concentrations of germanium: after the growth of the germanium (four) layer in U 1 , the GaN layer is annealed at 11 GG ° C for 5 minutes, and the temperature of the bean is reduced by 100 ° c / minute from 130592.doc 485. 200848558 η 〇〇 C The temperature was lowered, and a GaN layer was formed in the same manner as in Example ii except that the GaN layer was further subjected to annealing for 6 minutes. Carrier Wave, activation rate and yield are shown in Figure 7. In Example 3-2, a GaN layer was formed in the same manner as in Example 3-1, except that the germanium concentration was 5·〇χ1〇19 cm-3. The carrier concentration, activation rate and yield are shown in Fig. 7. Fig. 8 is a view showing the results of an experiment after forming a GaN layer in Examples 4-1 to 4-54. (Example 4-1 to Example 4-54) In Examples 4-1 to 4-54, experiments were carried out by changing the surface deviation angle of the GaN layer for the GaN layer having two erbium concentrations. In Example 4-1, the temperature drop rate was 6 (rc/min, and the annealing time was 1 〇 minutes, and the surface of the GaN layer was the (GaN1) plane normal direction of the GaN layer to ^ 2 〇 gt The GaN layer was formed in the same manner as in Example 丨, except that the direction was inclined to 0·03. The carrier concentration, activation ratio, and yield were as shown in Fig. 8. Example 4-2 In the embodiment 4_54, the layer (10) was formed in the same manner as in Example 4-1 except that the concentration and the off angle were changed as needed. The carrier concentration, the activation ratio and the yield are as shown in Fig. 8. 9 shows the results of the experiment after forming the GaN layer in the examples 5_1 to Η. (Example 5-1 to Example 5-8) In Example 5-1 to Example 5-8, The GaN layer of two germanium concentrations was changed after changing the dislocation density of the GaN layer. 130592.doc -20. 200848558 In Example 5-1, except that the cooling rate was 6 (rc/min, in addition to annealing, The G aN layer was formed in the same manner as the real, activation rate and good time of 10 minutes, and the dislocation density gLOxiO7 cm·2 was also the same as in Example 1-1. The carrier concentration ratio is shown in FIG. In Examples 5-2 to 5-8, layers were formed in the same manner as in Example 5-1 except that the concentration and the dislocation density were changed as needed. The carrier concentration, activation ratio, and yield were as follows. Figure 9 shows.

圖10係表示實施例6-1〜實施例6_1〇中形成層後之實 驗結果之圖。 (實施例6-1〜實施例6-10) 於實施例6-1〜實施例6-10中，使用包含各種材料之基板 代替GaN基板，進行實驗。 於實施例6-1中，使基板材料為藍寶石，使降溫速度為 6(TC/分鐘，使退火時間為10分鐘，使GaN層之表面為 層之（0001)面法線向&lt;11-20&gt;方向傾斜〇·2。，且向〈卜丨⑽〉 方向傾斜0.2。而獲得之面，除此以夕卜，以與實施例w相同 之方式，形成GaN層。載子濃度、活化率及良率如圖1〇所 示0 於實施例6-2〜實施例6_10中，除了根據需要改變基板材 料、偏離角以外，以與實施例6-丨相同之方式，形成 層。載子濃度、活化率及良率如圖丨〇所示。 圖11係表示實施例7-1〜實施例丨〇-2中形成GaN層後之實 驗結果之圖。 (實施例7-1〜實施例7-2) 130592.doc 21 200848558 於實施例7-1及實施例7-2中，除了改變偏離角以外，以 分別與實施例1-2及實施例1-7相同之方式，形成GaN層。 載子濃度、活化率及良率如圖11所示。 (貫施例8 -1〜貫施例8 - 2 ) 於實施例8-1及實施例8-2中，除了改變偏離角以外，以 分別與實施例7-1及實施例7-2相同之方式，形成GaN層。 載子濃度、活化率及良率如圖11所示。 (實施例9-1〜實施例9-2) 於實施例9-1及實施例9-2中，除了改變降溫速度及退火 時間以外，以分別與實施例7-1及實施例7-2相同之方式， 形成GaN層。載子濃度、活化率及良率如圖11所示。 (實施例10-1〜實施例10-2) 於實施例10-1及實施例10-2中，除了改變位錯密度以 外，以分別與實施例7-1及實施例7-2相同之方式，形成 GaN層。載子濃度、活化率及良率如圖11所示。 圖12係表示參考例2-1〜參考例2-2、實施例11-1〜實施例 12-4中形成GaN層後之實驗結果之圖。 (參考例2-1) 首先，於GaN基板上，使成長溫度（TG)為110(TC，使氧 濃度為3.〇xl〇17 cm 3之GaN層成長。於GaN層成長後，一 面以100°C/分鐘之降溫速度使溫度自11〇〇。〇降低至500°C為 止，一面對GaN層實施退火6分鐘。Fig. 10 is a graph showing the results of experiments in the formation of layers in Examples 6-1 to 6_1. (Example 6-1 to Example 6-10) In the examples 6-1 to 6-10, experiments were carried out using a substrate containing various materials instead of the GaN substrate. In Example 6-1, the substrate material was made of sapphire, and the temperature drop rate was 6 (TC/min, the annealing time was 10 minutes, and the surface of the GaN layer was the normal direction of the (0001) plane to &lt;11- 20&gt; direction is inclined 〇·2, and is inclined to 0.2 in the direction of <丨(10)>. The obtained surface is formed in the same manner as in the example w, and the carrier concentration and activation rate are formed. And the yield is as shown in FIG. 1A. In the embodiment 6-2 to the embodiment 6-10, a layer was formed in the same manner as in Example 6-丨 except that the substrate material and the off angle were changed as needed. The activation rate and the yield are shown in Fig. 11. Fig. 11 is a view showing the results of the experiment after forming a GaN layer in Examples 7-1 to 丨〇-2. (Examples 7-1 to 7) -2) 130592.doc 21 200848558 In Example 7-1 and Example 7-2, a GaN layer was formed in the same manner as in Example 1-2 and Example 1-7 except that the off angle was changed. The carrier concentration, activation rate, and yield are shown in Fig. 11. (Examples 8.1 to 3-8) In Example 8-1 and Example 8-2, except for changing the deviation A GaN layer was formed in the same manner as in Example 7-1 and Example 7-2 except for the angles. The carrier concentration, the activation ratio, and the yield are as shown in Fig. 11. (Examples 9-1 to 9) -2) In Example 9-1 and Example 9-2, a GaN layer was formed in the same manner as in Example 7-1 and Example 7-2 except that the temperature drop rate and the annealing time were changed. The concentration, activation rate, and yield are shown in Fig. 11. (Examples 10-1 to 10-2) In Example 10-1 and Example 10-2, in addition to changing the dislocation density, In the same manner as in Example 7-1 and Example 7-2, a GaN layer was formed. The carrier concentration, activation ratio, and yield are shown in Fig. 11. Fig. 12 shows Reference Example 2-1 to Reference Example 2-2. A graph showing the results of the experiment after forming a GaN layer in Examples 11-1 to 12-4. (Reference Example 2-1) First, a growth temperature (TG) of 110 (TC) was made on a GaN substrate. The growth of the GaN layer is 3. 〇xl 〇 17 cm 3 . After the GaN layer is grown, the temperature is reduced from 11 〇〇 to 500 ° C at a temperature drop rate of 100 ° C / min, facing the GaN layer. Annealing was carried out for 6 minutes.

GaN層之表面為使（〇〇〇 1)面法線向&lt;ι 1 _2〇&gt;方向傾斜 0.01。，且向 &lt;卜1〇〇&gt;方向傾斜〇·〇〗。而獲得之面。GaN層之 130592.doc -22- 200848558 位錯密度為5.〇X1〇7 cm-2。The surface of the GaN layer is inclined such that the (〇〇〇 1) plane normal is inclined toward the &lt;ι 1 _2 〇&gt; direction. And tilt to the &lt;Bu 1〇〇&gt; direction 〇·〇〗. And get the face. The GaN layer is 130592.doc -22- 200848558 The dislocation density is 5.〇X1〇7 cm-2.

二咐之載子濃度為1 ·2Χΐ〇〜3(活化率：40%)。GaN ^未產生裂痕之比例（亦即GaN層之製造為㈣(樣品 數量為100個）。 (參考例2-2) 除了使氧濃度為5 〇xl〇19 3 、 ^ M外，以與參考例2-1相同 之方式，形成GaN層。載子濃度、活化率及良率如圖12所 不The carrier concentration of the diterpenoid was 1 · 2 Χΐ〇 〜 3 (activation rate: 40%). The ratio of GaN ^ is not cracked (that is, the GaN layer is manufactured as (4) (the number of samples is 100). (Reference Example 2-2) In addition to the oxygen concentration of 5 〇xl 〇 19 3 , ^ M, In the same manner as in Example 2-1, a GaN layer was formed. The carrier concentration, activation rate, and yield are as shown in FIG.

(貫施例11-1〜實施例丨id 〇) 於實施例11- 1〜f施你丨1 U Ο Φ，八口， 貝也1 J τ分別對具有兩種氧濃度 之GaN層，改變降溫速度後進行實驗。 於實施例11-1中，除了使降溫速度為5(rc/分鐘，使退火 時間為12分鐘以外，以與參考例2-1相同之方式，形成GaN 層。載子?辰度、活化率及良率如圖12所示。 於實施例11-2〜實施例11-10中，除了根據需要改變氧濃 度、降溫速度、退火時間以外，以與實施例U-1相同之方 式，形成GaN層。載子濃度、活化率及良率如圖12所示。 (實施例12-1〜實施例12-4) 於實施例12-1〜實施例12-4中，分別對具有兩種氧濃度 之GaN層，改變成長溫度（tg)後進行實驗。 於實施例12-1中，除了使成長溫度為1〇5(rc，使退 火時間為11分鐘以外，以與實施例Uq相同之方式，形成 GaN層。載子濃度、活化率及良率如圖12所示。 於實施例12-2〜實施例12-4中，除了根據需要改變氧濃 130592.doc -23 - 200848558 度、成長溫度（Το)、退火時間以外，以與實施例12_丨相同 之方式，形成GaN層。載子濃度、活化率及良率如圖以所 示〇 圖13係表示實施例13-1〜實施例13-2中形成GaN層後之實 驗結果之圖。 (實施例13-1〜實施例13-2) 於實施例13-1〜實施例13-2中，分別對具有兩種氧濃度 之GaN層，改變退火條件後進行實驗。 於實施例13-1中，使GaN層成長之後，以u⑽。c對 層實施退火5分鐘，其後，一面al0(rc/分鐘之降溫速度自 ii〇〇°c使溫度降低，一面對GaN層進一步實施退火6分鐘， 除此以外，以與實施例相同之方式，形成GaN層。載 子濃度、活化率及良率如圖13所示。 於實施例13_2中，除了使氧濃度為5〇xl〇19 cm_3以外， 以與實施例13-1相同之方式，形成GaN層。載子濃度、活 化率及良率如圖13所示。 圖14係表示實施例丨4_丨〜實施例丨4_54中形成GaN層後之 實驗結果之圖。 (實施例14-1〜實施例14-54) 於實施例14-1〜實施例14_54中，分別對具有兩種氧濃度 之GaN層，改變GaN層之表面偏離角後進行實驗。 於實施例14-1中，使降溫速度為6(rc/分鐘，使退火時間 為10分鐘，使GaN層之表面為GaN層之（〇〇〇1)面法線向^卜 2〇&gt;方向傾斜〇〇3。之面’除此以外，以與實施例相同 130592.doc •24- 200848558 ’舌化率及良率如圖14所 之方式，形成GaN層。載子濃度 示0 於貫施例14-2〜實施例14-54中，除了钿祕a ⑨ί根據需要改變氧濃 度、偏離角以外，以與實施例14-1相同夕士上(Example 11-1 to Example 丨 id 〇) In Example 11-1 to f, you 丨1 U Ο Φ, eight, and B also 1 J τ, respectively, for the GaN layer having two oxygen concentrations, The experiment was carried out after the cooling rate. In Example 11-1, a GaN layer was formed in the same manner as in Reference Example 2-1 except that the temperature drop rate was 5 (rc/min, and the annealing time was 12 minutes). The yield is as shown in Fig. 12. In Example 11-2 to Example 11-10, GaN was formed in the same manner as in Example U-1 except that the oxygen concentration, the temperature drop rate, and the annealing time were changed as needed. The carrier concentration, activation rate and yield are shown in Fig. 12. (Examples 12-1 to 12-4) In Examples 12-1 to 12-4, respectively, two types of oxygen were used. The GaN layer of the concentration was subjected to an experiment after changing the growth temperature (tg). In Example 12-1, the growth temperature was set to 1 〇 5 (rc, and the annealing time was 11 minutes, in the same manner as in Example Uq. The GaN layer was formed, and the carrier concentration, activation rate, and yield were as shown in Fig. 12. In Example 12-2 to Example 12-4, in addition to changing the oxygen concentration 130592.doc -23 - 200848558 degrees, growth was performed as needed. The GaN layer was formed in the same manner as in Example 12_丨 except for the temperature (Το) and the annealing time. Carrier concentration, activation rate, and yield. 13 is a view showing experimental results of forming a GaN layer in Examples 13-1 to 13-2. (Examples 13-1 to 13-2) In Example 13- In the first to third embodiments, the GaN layer having two oxygen concentrations was subjected to an experiment after changing the annealing conditions. In Example 13-1, after the GaN layer was grown, the layer was annealed with u(10).c. Minutes, thereafter, on one side a1 (the cooling rate of rc/min is lowered from ii 〇〇 °c, and the GaN layer is further annealed for 6 minutes, except that a GaN layer is formed in the same manner as in the embodiment. The carrier concentration, the activation ratio, and the yield are shown in Fig. 13. In Example 13-2, a GaN layer was formed in the same manner as in Example 13-1 except that the oxygen concentration was 5 〇 x 〇 19 cm 3 . The carrier concentration, the activation ratio, and the yield are shown in Fig. 13. Fig. 14 is a view showing the results of an experiment in which a GaN layer was formed in Example 丨4_丨~Example 丨4_54. (Example 14-1 to Example) 14-54) In the embodiment 14-1 to the embodiment 14_54, respectively, the GaN layer having two oxygen concentrations is changed, and the surface deviation angle of the GaN layer is changed. In Example 14-1, the cooling rate was 6 (rc/min, and the annealing time was 10 minutes, and the surface of the GaN layer was the (GaN1) plane normal to the GaN layer. &gt; The direction is inclined to 〇〇3. The surface of the GaN layer is formed in the same manner as in the embodiment, 130592.doc •24-200848558. The carrier concentration is shown in Example 14-2 to Example 14-54, except that the concentration of oxygen is changed as needed, and the angle of deviation is changed as in the case of Example 14-1.

仰Ν之方式，形成GaN 層。載子濃度、活化率及良率如圖14所示。 圖15係表示實施例15 1〜實施例15 · 8中 u A J 6甲形成GaN層後之實 驗結果之圖。 (實施例15-1〜實施例15-8)The GaN layer is formed by the way of tilting. The carrier concentration, activation rate and yield are shown in Fig. 14. Fig. 15 is a view showing the results of an experiment after forming a GaN layer of u A J 6 A in Example 15 1 to Example 15·8. (Example 15-1 to Example 15-8)

於實施例15-1〜實施例15_8中，分別對具有兩種氧濃度 之GaN層，改變GaN層之位錯密度後進行實驗。 於實施例15-1中，除了使降溫速度為6(rc/分鐘，使退火 時間為10分鐘，使位錯密度為1〇xl〇7 cm-2以外，以與實 施例1H相同之方式，形成GaN層。載子濃度、活化= 良率如圖1 5所示。 於實施例15-2〜實施例15_8中，除了根據需要改變氧濃 度、位錯密度以外，以與實施例15_丨相同之方式，形成 GaN層。載子濃度、活化率及良率如圖丨5所示。 圖1 6係表示實施例i 6 _!〜實施例i 6 · i 〇中形成g &amp; n層後之 貫驗結果之圖。 (實施例1 6 -1〜實施例16 -1 〇 ) 於實施例⑹〜實施例16_10中，使用包含各種材料之基 板代替GaN基板，進行實驗。In Examples 15-1 to 15_8, experiments were carried out by changing the dislocation density of the GaN layer for the GaN layer having two oxygen concentrations. In the same manner as in Example 1H, except that the cooling rate was 6 (rc/min, the annealing time was 10 minutes, and the dislocation density was 1〇xl〇7 cm-2). The GaN layer was formed. The carrier concentration, activation = yield is shown in Fig. 15. In Example 15-2 to Example 15_8, in addition to changing the oxygen concentration and the dislocation density as needed, Example 15_丨In the same manner, a GaN layer was formed. The carrier concentration, activation rate, and yield are shown in Fig. 5. Fig. 1 shows the formation of g &amp; n layers in Example i 6 _!~ Example i 6 · i A graph of the results of the subsequent tests. (Example 1 6 -1 to Example 16 -1 〇) In the examples (6) to 16_10, experiments were carried out using a substrate containing various materials instead of the GaN substrate.

於實施例丨6·1中，使基板材料為藍寶石，使降溫速度為 6〇°C/分鐘，使退火時間為10分鐘，使GaN層之表面為GaN 130592.doc -25- 200848558 層之（0001)面之法線向&lt;11-20&gt;方向傾斜0.2。，且向&lt;;u 1 〇〇&gt;方向傾斜〇·2。而獲得之面，除此以外，以與實施例η _ 1相同之方式，形成GaN層。載子濃度、活化率及良率如 圖1 6所示。 於貫施例16-2〜實施例1 6-1 0中，除了使基板材料、偏離 角根據需要而變化以外，以與實施例1 6-1相同之方式，形 成GaN層。載子濃度、活化率及良率如圖16所示。 圖17係表示實施例1 7 -1〜實施例2 0 - 2中形成G aN層後之實 驗結果之圖。 (實施例17-1〜實施例17-2) 於實施例1 7-1及實施例1 7-2中，除了改變偏離角以外， 以分別與實施例11-2及實施例11-7相同之方式，形成GaN 層。載子濃度、活化率及良率如圖1 7所示。 (實施例18-1〜實施例18-2) 於實施例1 8-1及實施例1 8-2中，除了改變偏離角以外， 以分別與實施例17-1及實施例17-2相同之方式，形成GaN 層。載子濃度、活化率及良率如圖1 7所示。 (實施例19-1〜實施例19_2) 於實施例19-1及實施例19_2中，除了改變降溫速度及退 火時間以外，以與實施例17-1及實施例174分別相同之方 式，形成GaN層。載子濃度，活化率及良率如圖丨7所示。 (實施例20-1〜實施例20-2) 於實施例20-1及實施例20-2中，除了改變位錯密度以 外，以分別與實施例1 7-1及實施例1 7-2相同之方式，形成 130592.doc -26- 200848558In the embodiment 丨6.1, the substrate material is made of sapphire, the cooling rate is 6 〇 ° C / min, the annealing time is 10 minutes, and the surface of the GaN layer is GaN 130592.doc -25 - 200848558 ( The normal of the 0001) plane is inclined by 0.2 to the &lt;11-20&gt; direction. And tilts 〇·2 toward the &lt;;u 1 〇〇&gt; direction. On the other hand, except that the surface was obtained, a GaN layer was formed in the same manner as in the example η_1. The carrier concentration, activation rate and yield are shown in Figure 16. In the same manner as in Example 1 6-1, a GaN layer was formed in the same manner as in Example 1 6-1 except that the substrate material and the off angle were changed as needed in Example 16-2 to Example 1 6-1 0. The carrier concentration, activation rate and yield are shown in Fig. 16. Fig. 17 is a view showing the results of an experiment in which the GaN layer was formed in Example 17-1 to Example 20-2. (Examples 17-1 to 17-2) In Examples 1 7-1 and 1-7, except that the off angle was changed, it was the same as Example 11-2 and Example 11-7, respectively. In this way, a GaN layer is formed. The carrier concentration, activation rate and yield are shown in Fig. 17. (Embodiment 18-1 to Embodiment 18-2) In the embodiment 1-8-1 and the embodiment 18-2, except that the off angle is changed, they are the same as those of the embodiment 17-1 and the embodiment 17-2, respectively. In this way, a GaN layer is formed. The carrier concentration, activation rate and yield are shown in Fig. 17. (Example 19-1 to Example 19-2) In Example 19-1 and Example 19_2, GaN was formed in the same manner as in Example 17-1 and Example 174 except that the temperature drop rate and the annealing time were changed. Floor. The carrier concentration, activation rate and yield are shown in Fig. 7. (Example 20-1 to Example 20-2) In Example 20-1 and Example 20-2, except that the dislocation density was changed, it was respectively compared with Example 1 7-1 and Example 1 7-2. In the same way, form 130592.doc -26- 200848558

GaN層。載子濃度、活化率及良率如圖1 7所示。 又，於本實施例1-1〜20-2中，良率與結晶之曲率半徑存 在關係，良率為80%以上之結晶之曲率半徑為150 cm以 上，良率為84%以上之結晶之曲率半徑為180 cm以上，良 率為90%以上之結晶之曲率半徑為260 cm以上，良率為 95%以上之結晶之曲率半徑為300 cm以上。 繼而，對使用了磊晶基板62之半導體元件進行說明，該 磊晶基板62係藉由於利用上述第1實施形態及第2實施形態 所獲得之氮化鎵基板54上，形成氮化物半導體層56、58、 60而獲得者。作為半導體元件，以下例示LED、LD(Laser Diode，雷射二極體）、HEMT(High Electron Mobility Transistor，高電子遷移率電晶體）、肖特基二極體、縱型 MIS(Metal Insulator Semiconductor，金屬絕緣半導體）電 晶體。 (LED) 圖 18 係 LED(Light Emitting Diode :發光二極體）110 之剖 面圖。如圖18所示，LED 110包括··半導體層，於磊晶基 板62之上表面，依次形成有η型GaN層201、η型AlGaN層 202、發光層 203、p型 AlGaN層 204、p型 GaN層 205 ; p型 GaN層205之上表面之p側電極251 ;及磊晶基板62之下表 面之η側電極2 5 2。 發光層203亦可為將例如GaN層與InQ,2Ga〇.8N層之兩層構 造重疊多層而成之MQW(Multi-Quantum Well :多重量子 阱）構造。 130592.doc -27- 200848558 LED 11 0例如藉由以下方法製作。首先，作為元件製造 步驟，利用 MOCVD(Metal organic chemical vapor deposition，有機金屬化學氣相沈積）法而於蠢晶基板62之 上表面，依次形成η型GaN層201、η型AlGaN層202、發光 層203、p型AlGaN層204、p型GaN層205。繼而，於p型 GaN層205之上表面形成厚度為100 nm之p側電極251。進 而，藉由於磊晶基板62之下表面形成η側電極252，而獲得 LED 110 即 LED。 (LD) 圖19係LD(Laser Diode :雷射二極體）120之剖面圖。如 圖19B所示，LD 120包括：半導體層，於磊晶基板62之上 表面，依次形成有η型GaN緩衝層206、η型AlGaN包覆層 207、 η型GaN光波導層208、活性層209、非摻雜InGaN劣 化防止層210、p型AlGaN覆蓋層211、p型GaN光波導層 212、p型AlGaN包覆層213、p型GaN接觸層214;進而p型 GaN接觸層214之上表面之p側電極251 ;及磊晶基板62之 下表面之η側電極252。 LD 120例如藉由以下方法製作。首先，作為元件製造步 驟，如圖19Α所示，於蠢晶基板62之上表面依次形成η型 GaN緩衝層206、η型AlGaN包覆層207、η型GaN光波導層 208、 活性層209、非摻雜InGaN劣化防止層210、p型 AlGaN覆蓋層211、p型GaN光波導層212、p型AlGaN包覆 層213、p型GaN接觸層214。其次，於p型GaN接觸層214之 上表面整個面上藉由CVD(chemical vapor deposition，化 130592.doc • 28 - 200848558 學氣相沈積）法形成Si〇2膜之後，藉由微影法形成圖案。 其次，如圖19B所示，藉由蝕刻至P型AlGaN包覆層213之 厚度方向之特定深度為止形成隆起物215。其後，去除 SiO2膜之後，於基板整個面上形成Si〇2絕緣膜216。其 次’藉由抗蝕圖案之形成及蝕刻，而僅於13型（}·接觸層 214之上表面形成p側電極251。其後，藉由於下表面形成〇 側電極252，而獲得LD 120即LD。 再者，Si〇2膜之形成亦可使用真空蒸鍍、濺射法等’ si〇2膜之蝕刻亦可為使用包含氟之蝕刻氣體之RiE(reactive ion etch，反應性離子蝕刻）法。 (HEMT) 圖 2〇係 HEMT(High Electron Mobility transistor :高電子 遷移率黾曰曰體）130之剖面圖。如圖20所示，HEMT 13〇於 磊晶基板62之上表面，依次形成有i型GaN層22U、i型 AlGaN層221b，作為1層以上之山族氮化物半導體層221， 且進而於i型AlGaN層221b之上表面包括源極電極253、閘 極電極2 5 4及沒極電極2 5 5。 HEMT 130例如藉由以下方法製作。作為元件製造步驟， 如圖20所示，於磊晶基板62之上表面，使丨型〇_層221&amp;、 i型AlGaN層221b成長之後，藉由光微影法及舉離法，而於 1型AlGaN層221b上形成源極電極253及汲極電極255後，進 而，形成閘極電極254，藉此獲13(^hemt。 (肖特基二極體） 圖21係肖特基二極體丨4〇之剖面圖。如圖2丨所示，肖特 130592.doc -29- 200848558 基二極體140於磊晶基板62之上表面，具有型GaN層221 作為1層以上之III族氮化物半導體層，於磊晶基板62之下 表面具備歐姆電極256。又，於ιΓ型GaN層221之上表面具 備肖特基電極257。 肖特基二極體140例如藉由以下方法製作。作為元件製 造步驟，如圖2 1所示，於磊晶基板62上，藉由MOCVD 法，使ιΓ型GaN層221成長。其次，於磊晶基板62之下表面 前面形成歐姆電極2 5 6。進而，藉由光微影及舉離法，而 於n_型GaN層221上形成肖特基電極257。藉由以上方式， 獲得肖特基二極體14 0即肖特基二極體。 (縱型MIS電晶體） 圖 22係縱型 MIS(Metal Insulator Semiconductor :金屬-絕緣體-半導體）電晶體150之剖面圖。如圖22所示，縱型 MIS電晶體150於磊晶基板62之上表面，形成ιΓ型GaN層 221c作為1層以上之III族氮化物半導體層221，並於η—型 GaN層221c之上表面之一部分區域中形成ρ型GaN層22Id及 n+型GaN層221e。進而，於磊晶基板62之下表面具備汲極 電極255，於n—型GaN層221c之上表面具備閘極電極254， 於n+型GaN層221 e之上表面具備源極電極253。 本實施形態之縱型MIS電晶體1 50例如藉由以下方法製 作。作為元件製造步驟，如圖22所示，於磊晶基板62上， 藉由MOCVD法形成ιΓ型GaN層221c。繼而，藉由選擇離子 注入法，而於n_型GaN層221c之上表面之一部分區域中依 次形成P型GaN層221d及n+型GaN層221e。其次，使用Si02 130592.doc -30- 200848558 膜保護ιΓ型GaN層221c之後，進行退火使注入離子活化。 藉由 P-CVD(Plasma enhanced Chemical Vapor Deposition : 電漿輔助化學氣相沈積）法形成Si〇2膜作為縱型乂^用絕緣 膜之後’藉由光微影法及使用緩衝氟酸之選擇蝕刻法，對 上述縱型MIS用絕緣膜之一部分進行蝕刻，並藉由舉離 法，於n+型GaN層221 e之上表面形成源極電極253。其次， 藉由光微影法及舉離法，而於上述縱型MIS用絕緣膜上， 形成閘極電極254。GaN layer. The carrier concentration, activation rate and yield are shown in Fig. 17. Further, in the present examples 1-1 to 20-2, the yield is related to the radius of curvature of the crystal, and the crystal having a yield of 80% or more has a radius of curvature of 150 cm or more and a yield of 84% or more. The radius of curvature of the crystal having a radius of curvature of 180 cm or more and a yield of 90% or more is 260 cm or more, and the radius of curvature of the crystal having a yield of 95% or more is 300 cm or more. Next, a description will be given of a semiconductor device using an epitaxial substrate 62 which is formed on the gallium nitride substrate 54 obtained by the first embodiment and the second embodiment to form a nitride semiconductor layer 56. , 58, 60 and the winner. Examples of the semiconductor device include LED, LD (Laser Diode), HEMT (High Electron Mobility Transistor), Schottky diode, and Vertical MIS (Metal Insulator Semiconductor). Metal-insulated semiconductor) transistor. (LED) Fig. 18 is a cross-sectional view of an LED (Light Emitting Diode) 110. As shown in FIG. 18, the LED 110 includes a semiconductor layer. On the upper surface of the epitaxial substrate 62, an n-type GaN layer 201, an n-type AlGaN layer 202, a light-emitting layer 203, a p-type AlGaN layer 204, and a p-type are sequentially formed. The GaN layer 205; the p-side electrode 251 on the upper surface of the p-type GaN layer 205; and the n-side electrode 2 5 2 on the lower surface of the epitaxial substrate 62. The light-emitting layer 203 may have a MQW (Multi-Quantum Well) structure in which, for example, a GaN layer and an InQ, 2Ga〇.8N layer are laminated in two layers. 130592.doc -27- 200848558 LED 11 0 is produced, for example, by the following method. First, as an element manufacturing step, an n-type GaN layer 201, an n-type AlGaN layer 202, and a light-emitting layer are sequentially formed on the upper surface of the stray substrate 62 by MOCVD (Metal Organic Chemical Vapor Deposition) method. 203, a p-type AlGaN layer 204, and a p-type GaN layer 205. Then, a p-side electrode 251 having a thickness of 100 nm is formed on the upper surface of the p-type GaN layer 205. Further, by forming the n-side electrode 252 on the lower surface of the epitaxial substrate 62, the LED 110, that is, the LED, is obtained. (LD) FIG. 19 is a cross-sectional view of an LD (Laser Diode) 120. As shown in FIG. 19B, the LD 120 includes a semiconductor layer. On the upper surface of the epitaxial substrate 62, an n-type GaN buffer layer 206, an n-type AlGaN cladding layer 207, an n-type GaN optical waveguide layer 208, and an active layer are sequentially formed. 209, an undoped InGaN degradation preventing layer 210, a p-type AlGaN cladding layer 211, a p-type GaN optical waveguide layer 212, a p-type AlGaN cladding layer 213, a p-type GaN contact layer 214; and further a p-type GaN contact layer 214 The p-side electrode 251 of the surface; and the n-side electrode 252 on the lower surface of the epitaxial substrate 62. The LD 120 is produced, for example, by the following method. First, as an element manufacturing step, as shown in FIG. 19A, an n-type GaN buffer layer 206, an n-type AlGaN cladding layer 207, an n-type GaN optical waveguide layer 208, and an active layer 209 are sequentially formed on the upper surface of the dummy substrate 62. The undoped InGaN degradation preventing layer 210, the p-type AlGaN cladding layer 211, the p-type GaN optical waveguide layer 212, the p-type AlGaN cladding layer 213, and the p-type GaN contact layer 214. Next, after the Si〇2 film is formed on the entire surface of the upper surface of the p-type GaN contact layer 214 by CVD (chemical vapor deposition), the lithography method is used. pattern. Next, as shown in Fig. 19B, the bumps 215 are formed by etching to a specific depth in the thickness direction of the P-type AlGaN cladding layer 213. Thereafter, after the SiO2 film is removed, an Si 2 insulating film 216 is formed on the entire surface of the substrate. Secondly, the p-side electrode 251 is formed only on the upper surface of the type 13 (} contact layer 214 by the formation and etching of the resist pattern. Thereafter, the LD 120 is obtained by forming the side electrode 252 on the lower surface. Further, the formation of the Si〇2 film may be performed by vacuum evaporation, sputtering, or the like. The etching of the 'si〇2 film may be RiE (reactive ion etch) using an etching gas containing fluorine. (HEMT) Fig. 2 is a cross-sectional view of a HEMT (High Electron Mobility Transistor) 130. As shown in Fig. 20, the HEMT 13 is formed on the upper surface of the epitaxial substrate 62, and sequentially formed. The i-type GaN layer 22U and the i-type AlGaN layer 221b are provided as one or more layers of the mountain nitride semiconductor layer 221, and further include a source electrode 253 and a gate electrode 254 on the upper surface of the i-type AlGaN layer 221b. The electrodeless electrode 2 5 5. The HEMT 130 is produced, for example, by the following method. As a component manufacturing step, as shown in FIG. 20, on the upper surface of the epitaxial substrate 62, a 〇-type 221 layer 221 &amp; an i-type AlGaN layer 221 b is formed. After growth, it is formed on the type 1 AlGaN layer 221b by photolithography and lift-off method. After the source electrode 253 and the drain electrode 255, further, the gate electrode 254 is formed, thereby obtaining 13 (^hemt. (Schottky diode). FIG. 21 is a Schematic diagram of the Schottky diode 丨4〇. As shown in FIG. 2A, Schott 130592.doc -29- 200848558 base diode 140 is on the upper surface of the epitaxial substrate 62, and has a type GaN layer 221 as one or more layers of a group III nitride semiconductor layer. The lower surface of the crystal substrate 62 is provided with an ohmic electrode 256. Further, a Schottky electrode 257 is provided on the upper surface of the GaN-type GaN layer 221. The Schottky diode 140 is produced by, for example, the following method. As shown in Fig. 2, the ITO-type GaN layer 221 is grown by the MOCVD method on the epitaxial substrate 62. Next, the ohmic electrode 256 is formed in front of the lower surface of the epitaxial substrate 62. Further, by photolithography And the lift-off method, the Schottky electrode 257 is formed on the n-type GaN layer 221. By the above manner, the Schottky diode 110, that is, the Schottky diode is obtained. (Vertical MIS transistor) 22 is a cross-sectional view of a vertical MIS (Metal Insulator Semiconductor) transistor 150. The vertical MIS transistor 150 is on the upper surface of the epitaxial substrate 62, and the ι-type GaN layer 221c is formed as one or more layers of the group III nitride semiconductor layer 221, and is in a portion of the upper surface of the η-type GaN layer 221c. A p-type GaN layer 22Id and an n+ type GaN layer 221e are formed. Further, a drain electrode 255 is provided on the lower surface of the epitaxial substrate 62, a gate electrode 254 is provided on the upper surface of the n-type GaN layer 221c, and a source electrode 253 is provided on the upper surface of the n+ type GaN layer 221e. The vertical MIS transistor 150 of the present embodiment is produced, for example, by the following method. As a component manufacturing step, as shown in FIG. 22, an ITO-type GaN layer 221c is formed on the epitaxial substrate 62 by an MOCVD method. Then, a P-type GaN layer 221d and an n+-type GaN layer 221e are sequentially formed in a portion of the upper surface of the n-type GaN layer 221c by selective ion implantation. Next, after the ITO-type GaN layer 221c is protected by a film using SiO 2 130592.doc -30- 200848558, annealing is performed to activate the implanted ions. The Si〇2 film is formed by a P-CVD (Plasma Enhanced Chemical Vapor Deposition) method as an insulating film for a vertical type, and is selectively etched by photolithography and buffered hydrofluoric acid. In the method, one portion of the vertical MIS insulating film is etched, and the source electrode 253 is formed on the upper surface of the n + -type GaN layer 221 e by lift-off method. Next, a gate electrode 254 is formed on the vertical MIS insulating film by a photolithography method and a lift-off method.

進而，藉由於磊晶基板62之下表面整個面上形成汲極電 極255，而獲得縱型MIS電晶體150即縱型MIS電晶體。 再者，半導體元件之製造步驟中的裂痕測定，於磊晶成 長、電極形成等結束，II由切割或劈裂等而形成晶片之後 進行。 (元件評估） 關於藉由各半導體元件之製造步驟而製作之半導體元件 之元件特性的評估，如下所述。首先，測定相當於各半導 體70件比較例之半導體元件之元件特性，並分別測定LED 之發先強度’LD之雷射壽命，職T、肖特基二極 =電晶體之接通電阻，#出其等之平均值及據 遠平均值及σ，對實施例 將達到比較例之元件特性（平均值_啦上^ =件特性， 合格。比較例中所包含之元件亦门详 之、，、。果者判定為 件特性(平的佶、 將達到比較例之元 件特ί±(千均值_σ)以上之結果者判定為合格。 ㈤圖25係表不已製作之半導體元件之良率之圖。 130592.doc 200848558 首先，圖23表示參考例3 +參考例4_2 施例叫之半導體㈣（LED)之良率。、1 ^ (參考例3 -1) 石於參考例3·1中’使用參考例η中所形成之層製作 . 磊晶基板，並使用該磊晶基板製作半導體元件（LED)。半 • ^體凡件（LED)之製作方法如上所述。⑽層成長時未產 生裂痕之比例（GaN層之製造良率）如上所述為68%。又， r 於半導體元件之製造步驟中，未產生裂痕之比例（半導體 k &amp;件之製造良销62% ’對半導體元件特性進行評估之良 率為抓。因此，半導體元件之製作之所有步驟中的合計 良率為19%。 (ί考例3 - 2、參考例4 -1、參考例4 _ 2) 於參考例3·2、參考例4-1、及參考例4_2中，除了改變所 使用之蟲晶基板以外，以與參考例3-1相同之方式，製作 半導體元件。GaN層之製造良率、半導體元件之製造良 J 帛、對經製作之半導體元件特性進行評估之良率、及半導 體元件製作之所有步驟中的合計良率如圖2 3所示。 (實施例21_1〜實施例22_3) 制於實施例2H〜實施例22_3中，分別改變半導體元件之 ‘作中所使用之蟲晶基板後進行實驗。 於實施例21]中’除了使所使用之基板為使用實施例K 5中所形成之GaN層的遙晶基板以外，以與參考例W相同 之方式，製作半導體元件。⑽層之製造良率、半導體元 件之製造良率、對經製作之半導體元件特性進行評估之良 130592.doc -32- 200848558 率、及半導體元件製作之％ + _ &amp;之所有步驟中的合計良率如圖23所 示0 (實施例21_2〜實施例22-3) 於實施例21-2〜實施伽9，，丄 b 、&amp;則22-3中，除了改變所使用之磊晶 基板以外，以與實施你丨 、U21·1相同之方式，製作半導體元 件。GaN層之製造良率、半導體元件之製造良率、對經製 作之半導體元件特性進行評估之良率、及半導體元件製作Further, the vertical MIS transistor 150, that is, the vertical MIS transistor, is obtained by forming the gate electrode 255 over the entire lower surface of the epitaxial substrate 62. Further, the measurement of the crack in the manufacturing step of the semiconductor element is completed after the epitaxial growth, electrode formation, and the like, and II is formed by dicing or cleaving. (Component Evaluation) The evaluation of the element characteristics of the semiconductor element produced by the manufacturing steps of the respective semiconductor elements is as follows. First, the component characteristics of the semiconductor device corresponding to the comparative example of 70 semiconductors were measured, and the laser lifetime of the initial intensity 'LD of the LED was measured, and the T, Schottky diode = the on-resistance of the transistor, # The average value and the average value and σ according to the example will reach the component characteristics of the comparative example for the examples (average value _ 上 ^ ^ = part characteristics, qualified. The components included in the comparative example are also detailed, The result is judged to be a member characteristic (flat 佶, the result of the component ί± (thousand mean _σ) of the comparative example is judged as a pass. (5) Fig. 25 shows the yield of the semiconductor component which has not been produced. Fig. 23 first, Fig. 23 shows the yield of the semiconductor (four) (LED) of the reference example 3 + reference example 4_2. Example 1 ^ (Reference Example 3-1) Stone in Reference Example 3.1 An epitaxial substrate was fabricated using the layer formed in Reference Example η, and a semiconductor device (LED) was fabricated using the epitaxial substrate. The fabrication method of the semiconductor device (LED) was as described above. (10) Layer growth did not occur. The ratio of cracks (manufacturing yield of the GaN layer) was 68% as described above. Further, r In the manufacturing steps of the semiconductor device, the ratio of cracks (the semiconductor k &amp; member manufacturing good 62% ' is evaluated for the characteristics of the semiconductor device. Therefore, the total of all the steps in the fabrication of the semiconductor device The yield is 19%. (ί考例3 - 2, Reference Example 4-1, Reference Example 4 _ 2) In Reference Example 3·2, Reference Example 4-1, and Reference Example 4_2, except for the use of the change A semiconductor element was produced in the same manner as in Reference Example 3-1 except for the crystal substrate. The yield of the GaN layer, the fabrication of the semiconductor device, the yield of the fabricated semiconductor device, and the semiconductor were evaluated. The total yield in all the steps of the device fabrication is as shown in Fig. 23. (Example 21_1 to Example 22_3) In the example 2H to the embodiment 22_3, the crystal crystals used in the semiconductor device were changed. The experiment was carried out after the substrate. In the same manner as in Reference Example W except that the substrate to be used was a remote crystal substrate using the GaN layer formed in Example K5, in Example 21, (10) Layer manufacturing yield, The yield of the conductor element, the evaluation of the characteristics of the fabricated semiconductor component, the yield of 130592.doc -32-200848558, and the total yield of all components of the semiconductor device fabrication + _ &amp; 0 (Example 21_2 to Example 22-3) In the embodiment 21-2 to the implementation of the gamma 9, 丄b, &amp; 22-3, in addition to changing the epitaxial substrate used, In the same manner as in U21·1, a semiconductor device is fabricated, the manufacturing yield of the GaN layer, the manufacturing yield of the semiconductor device, the yield of the characteristics of the fabricated semiconductor device, and the fabrication of the semiconductor device.

之所有步驟中的合計良率如圖23所示。 圖24表不參考例5]〜參考例“、冑施例23_卜實施例2心 3之半導體元件（LD)之良率。 (參考例5-1) 於參考例5-1中，使用參考例丨-丨中形成之GaN層製作磊 曰曰基板，並使用該磊晶基板製作半導體元件（LD)。半導體 兀件（LD)之製作方法如上所述。於GaN層成長時未產生裂 痕之比例（GaN層之製造良率）如上所述為68%。又，於半 導體元件之製造步驟中，未產生裂痕之比例（半導體元件 之製造良率）為41%，對經製作之半導體元件特性進行評估 之良率為38〇/。。因此，半導體元件製作之所有步驟中的合 計良率為11%。 σ (參考例5 - 2、參考例6 -1、參考例6 - 2) 於參考例5-2、參考例6—丨、及參考例6-2中，除了改變所 使用之磊晶基板以外，以與參考例5-1相同之方式，掣作 半導體元件。GaN層之製造良率、半導體元件之製造良 率、對經製作之半導體元件特性進行評估之良率、及半導 130592.doc -33- 200848558 體凡件製作之所有步驟中的合計良率如圖24所示。 (實施例23-1〜實施例24-3) 於實施例23-1〜24-3中，分別改變半導體元件製作中所 使用之磊晶基板後進行實驗。 於實施例23-1中，除了使所使用之基板為使用實施例^ 5中所形成之GaN層的磊晶基板以外，以與參考例5_丨相同 之方式，製作半導體元件。GaN層之製造良率、半導體元 件之製造良率、對經製作之半導體元件特性進行評估之良 率、及半導體元件製作之所有步驟中的合計良率如圖。所 示。 (實施例23-2〜實施例24-3) 於貫施例23-2〜實施例24-3中，除了改變所使用之磊晶 基板以外，以與實施例23-1與相同之方式，製作半導體元 件。GaN層之製造良率、半導體元件之製造良率、對經製 作之半導體元件特性進行評估之良率、及半導體元件製作 之所有步驟中的合計良率如圖24所示， 圖25表示參考例7〜參考例9、實施例25〜實施例”之半導 體元件（HEMT、肖特基二極體、縱型MIS電晶體）之良率。 (參考例7) 於麥考例7中，使用參考例1-2中所形成之GaN層製作磊 晶基板，並使用該磊晶基板製作半導體元件（HEMT)。半 V體7L件（HEMT)之製作方法如上所述。GaN層成長時未產 生裂痕之比例（GaN層之製造良率）如上所述為63%。又， 於半導體元件之製造步驟中，未產生裂痕之比例（半導體 130592.doc -34- 200848558 元件之製造良率）為62%， 評估之良率為66%。因此 為 26% 〇 對經製作之丰墓鱗— 心千V體7L件特性進行 m件製作中的合計良率 (實施例25) 於實施例25中 板後進行實驗。 改變半導體元件製作 中所使用之磊晶基The total yield in all the steps is shown in Fig. 23. Fig. 24 shows the yield of the semiconductor device (LD) of the reference example "5" to "Example", "Example 23", and Example 2 (Reference Example 5-1). Referring to the GaN layer formed in the 丨-丨, an epitaxial substrate is fabricated, and a semiconductor device (LD) is fabricated using the epitaxial substrate. The method of fabricating the semiconductor device (LD) is as described above. No crack occurs when the GaN layer is grown. The ratio (the manufacturing yield of the GaN layer) is 68% as described above. Further, in the manufacturing step of the semiconductor element, the ratio of the crack (the manufacturing yield of the semiconductor element) is 41%, and the fabricated semiconductor element is used. The yield of the characteristic evaluation is 38 〇 /. Therefore, the total yield in all steps of fabrication of the semiconductor device is 11%. σ (Reference Example 5-2, Reference Example 6-1, Reference Example 6-2) In the same manner as in Reference Example 5-1, the semiconductor element was fabricated in the same manner as in Reference Example 5-1 except that the epitaxial substrate used was changed, and the fabrication of the GaN layer was carried out in Reference Example 5-2, Reference Example 6 - 丨, and Reference Example 6-2. Yield, manufacturing yield of semiconductor components, and evaluation of characteristics of fabricated semiconductor components And the semi-conductor 130592.doc -33- 200848558 The total yield in all the steps of the fabrication of the parts is shown in Fig. 24. (Example 23-1 to Example 24-3) In Examples 23-1 to 24 In the experiment, the epitaxial substrate used in the fabrication of the semiconductor device was changed, and the experiment was carried out. In Example 23-1, except that the substrate used was an epitaxial substrate using the GaN layer formed in Example 5. In the same manner as in Reference Example 5_丨, a semiconductor element was produced, the manufacturing yield of the GaN layer, the manufacturing yield of the semiconductor element, the yield of the characteristics of the fabricated semiconductor device, and the fabrication of the semiconductor device. The total yield in the step is as shown in the figure. (Example 23-2 to Example 24-3) In the examples 23-2 to 24-3, except for changing the epitaxial substrate used, A semiconductor device was produced in the same manner as in Example 23-1. The manufacturing yield of the GaN layer, the manufacturing yield of the semiconductor device, the yield of the characteristics of the fabricated semiconductor device, and all steps of fabrication of the semiconductor device were carried out. The total yield in Figure 24 is shown in Figure 2, Figure 2 5 shows the yields of the semiconductor elements (HEMT, Schottky diode, and vertical MIS transistor) of Reference Example 7 to Reference Example 9 and Example 25 to Example. (Reference Example 7) In the study example 7, an epitaxial substrate was produced using the GaN layer formed in Reference Example 1-2, and a semiconductor element (HEMT) was fabricated using the epitaxial substrate. The manufacturing method of the semi-V body 7L piece (HEMT) is as described above. The ratio at which cracks were not generated when the GaN layer was grown (manufacturing yield of the GaN layer) was 63% as described above. Further, in the manufacturing steps of the semiconductor element, the ratio of cracks (the manufacturing yield of the semiconductor 130592.doc -34 - 200848558 element) was 62%, and the evaluation yield was 66%. Therefore, for the 26% 〇, the total yield in the m-piece production of the produced abundance scale - the heart-shaped V-body 7L piece characteristic (Example 25) was tested after the plate in Example 25. Changing the epitaxial base used in the fabrication of semiconductor components

於實施例25中，除了使所使用之基板為使用實施例㈣ 中所形成之GaN層之蠢晶基板以外，以與參考例7相同之 方式，製作半導體元件。GaN層之製造良率、半導體元件 之製造良率、對經製作之半導體元件特性進行評估&amp;之良 率、及半導體元件製作之所有步驟中的合計良率如圖25所 示。 (參考例8)In the same manner as in Reference Example 7, except that the substrate to be used was an amorphous substrate using the GaN layer formed in Example (4), a semiconductor device was produced. The yield of the GaN layer, the manufacturing yield of the semiconductor element, the evaluation of the characteristics of the fabricated semiconductor device, the yield, and the total yield in all steps of fabrication of the semiconductor device are shown in Fig. 25. (Reference Example 8)

於麥考例8中Μ吏用參考例1-2中之_層製作磊晶基 板，並使用該磊晶基板製作半導體元件（肖特基二極體）。 半導體元件（肖特基二極體）之製作方法如上所述。層 成長時未產生裂痕之比例（GaN層之製造良率）如上所述為 63%。又，於半導體元件之製造步驟中，未產生裂痕之比 例（半導體元件之製造良率）為65%，對經製作之半導體元 件特性進行評估之良率為63%。因此，半導體元件製作之 所有步驟中的合計良率為26%。 (實施例26) 於實施例26中，改變半導體元件製造中所使用之磊晶基 板後進行實驗。 130592.doc -35- 200848558 於實施例26中，除了使所使用之基板為使用實施例1-10 中所形成之GaN層之磊晶基板以外，以與參考例8相同之 方式，製作半導體元件。GaN層之製造良率、半導體元件 之製造良率、對經製作之半導體元件特性進行評估之良 率、及半導體元件製作之所有步驟中的合計良率如圖25所 示。 (參考例9) 於參考例9中，使用參考例丨_2中之GaN層製作磊晶基 板，並使用該磊晶基板製作半導體元件（縱型電晶 體）。半導體元件（縱型MIS電晶體）之製作方法如上所述。 GaN層成長時未產生裂痕之比例（GaN層之製造良率）如上 所述為63%。又，於半導體元件之製造步驟中，未產生裂 痕之比例（半導體元件之製造良率）為59%，對經製作之半 導體元件特性進行評估之良率為59%。因此，半導體元件 製作之所有步驟中的合計良率為22。/。。 (實施例27) 於實施例27中，改變半導體元件製造中所使用之磊晶基 板後進行實驗。 曰土 於貫施例27中 必低句便用貫施例M〇 中所形成之GaN層之蠢晶基板以夕卜，以與參考例9相同之 方式，製作半導體元件。GaN層之製造良率、半導酽元件 之製造良率、對經製作之半導體元件特性進行評：良 率、及半導體元件製作之所有步驟中 义 j 口。T艮率如圖25所 示0 130592.doc -36- 200848558 曰^戶斤說明般，於上述半導體元件中，可藉由使用蟲 而降低何體元件之製造步驟巾㈣痕發生率 述:晶基板使用藉由^及第2實施形態之形成方法而形 成之亂化鎵層。又，可提高對半導體元件特性進行評估之 結果為，可提高半導體㈣製作之所有步驟 合計良率。 【圖式簡單說明】 圖1係模式性表示用以於基板上形成包含η型推雜物之氮 化鎵層之氫化物VPE裝置之圖。 圖2Α〜2D係模式性表示實施形態之氮化嫁層之形成方 法、使用該氮化鎵層之氮化鎵基板之製造方法、及使用該 氮化鎵基板之磊晶基板之製造方法的步驟圖。 圖3 A、3 Β係表示基板溫度之時間變化之具體例之圖 表。 ° 圖4係表示氮化鎵層之形成步驟之圖。 圖5係表示氮化鎵基板之製造步驟之圖。 圖6係表示參考例〜參考例1-2、實施例丨-丨〜實施例2_4 中形成GaN層後之實驗結果之圖。 圖7係表示實施例3-1〜實施例3-2中形成GaN層後之實驗 結果之圖。 圖8係表示貫施例4 -1〜實施例4 - 5 4中形成GaN層後之實驗 結果之圖。 圖9係表示實施例5-1〜實施例5-8中形成GaN層後之實驗 結果之圖。 130592.doc -37- 200848558 圖10係表示實施例6-1〜實施例6-10中形成GaN層後之實 驗結果之圖。 圖11係表示實施例7-1〜實施例10_2中形成GaN層後之實 驗結果之圖。 • 圖12係表示參考例2-1〜參考例2_2、實施例11-1〜實施例 • 丨2_4中形成GaN層後之實驗結果之圖。 圖13係表示實施例13-1〜實施例13-2中形成GaN層後之實 驗結果之圖。 (· 圖14係表示實施例14-1〜實施例1444中形成GaN層後之 實驗結果之圖。 圖15係表示實施例15-1〜實施例15-8中形成GaN層後之實 驗結果之圖。 圖16係表示實施例16-1〜實施例16-10中形成GaN層後之 貫驗結果之圖。 圖17係表示實施例17-1〜實施例20-2中形成GaN層後之實 , 驗結果之圖。 ί， 圖18係LED之剖面圖。 圖19A、19B係LD之剖面圖。 ‘ 圖20係HEMT之剖面圖。 - 圖2 1係肖特基二極體之剖面圖。 圖22係縱型MIS電晶體之剖面圖。 圖2 3係表示參考例3 -1〜參考例4〜2、實施例21 -1〜實施例 22-3十半導體元件製作後之良率之圖。 圖24係表示參考例5_ 1〜參考例6_2、實施例23-1〜實施例 130592.doc -38- 200848558 24-3中半導體元件製作後之良率之圖。 圖25係表示參考例7〜參考例9、實施例25〜實施例27中半 導體元件製作後之良率之圖。 【主要元件符號說明】 10 氫化物VPE裝置 12 成長爐 14 晶座 16 嫁供給源 18 &gt; 32 加熱器 24 矽供給源 26 氧供給源 28 HC1供給源 30 氮供給源 34 控制裝置 50 基板 5卜 52 氮化鎵層 52a 、54a 表面 54 氮化鎵基板 56、 58 &gt; 60 氮化物半導體層 62 蠢晶基板 110 LED 120 LD 130 HEMT 140 肖特基二極體 130592.doc -39- 200848558 150 縱型MIS電晶體 201 n型GaN層 202 n型AlGaN層 203 發光層 204 p型AlGaN層 205 、 221d p型GaN層 206 n型GaN緩衝層 207 η型AlGaN包覆層 208 η型GaN光波導層 209 活性層 210 非摻雜InGaN劣化防止層 211 p型AlGaN覆蓋層 212 p型GaN光波導層 213 p型AlGaN包覆層 214 p型GaN接觸層 215 隆起物 216 Si02絕緣膜 221 III族氮化物半導體層、η 221a i型GaN層 221b i型AlGaN層 221c rf型GaN層 221e n+型GaN層 251 p侧電極 252 η侧電極 型GaN層 130592.doc -40- 200848558 253 源極電極 254 閘極電極 255 汲極電極 256 歐姆電極 257 肖特基電極 t〇 Λ ti 時刻 To 成長溫度 T! 退火結束溫度 Θ 角 130592.doc -41 -In the example 8 of the invention, an epitaxial substrate was produced using the layer of Reference Example 1-2, and a semiconductor element (Schottky diode) was fabricated using the epitaxial substrate. The method of fabricating the semiconductor element (Schottky diode) is as described above. The ratio at which no crack occurred during the growth of the layer (the yield of the GaN layer) was 63% as described above. Further, in the manufacturing process of the semiconductor device, the ratio of the cracks (the manufacturing yield of the semiconductor element) was 65%, and the yield of the fabricated semiconductor device was 63%. Therefore, the total yield in all the steps of fabrication of the semiconductor device is 26%. (Example 26) In Example 26, an experiment was carried out after changing the epitaxial substrate used in the manufacture of a semiconductor element. 130592.doc -35- 200848558 In the same manner as in Reference Example 8, except that the substrate to be used was an epitaxial substrate using the GaN layer formed in Example 1-10, a semiconductor device was fabricated in the same manner as in Reference Example 8. . The manufacturing yield of the GaN layer, the manufacturing yield of the semiconductor element, the yield of the characteristics of the fabricated semiconductor device, and the total yield in all the steps of fabricating the semiconductor device are shown in Fig. 25. (Reference Example 9) In Reference Example 9, an epitaxial substrate was produced using the GaN layer in Reference Example 丨_2, and a semiconductor element (vertical electromorph) was fabricated using the epitaxial substrate. The manufacturing method of the semiconductor element (vertical MIS transistor) is as described above. The ratio at which cracks were not generated when the GaN layer was grown (the yield of the GaN layer) was 63% as described above. Further, in the manufacturing step of the semiconductor device, the ratio of the cracks (the manufacturing yield of the semiconductor element) was 59%, and the yield of the fabricated semiconductor device was 59%. Therefore, the total yield in all the steps of fabrication of the semiconductor device is 22. /. . (Example 27) In Example 27, an experiment was carried out after changing the epitaxial substrate used in the manufacture of a semiconductor element. In the case of Example 27, a semiconductor element was produced in the same manner as in Reference Example 9 by using a stray substrate of a GaN layer formed in Example M. The manufacturing yield of the GaN layer, the manufacturing yield of the semiconductor device, and the characteristics of the fabricated semiconductor device: the yield, and the steps of manufacturing the semiconductor device. The T艮 rate is as shown in Fig. 25, 130 130. doc - 36 - 200848558. In the above semiconductor element, the manufacturing process of the body element can be reduced by using the insect (4). The substrate is a chaotic gallium layer formed by the formation method of the second embodiment. Further, the evaluation of the characteristics of the semiconductor element can be improved, and the total yield of all the steps of the fabrication of the semiconductor (4) can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view schematically showing a hydride VPE apparatus for forming a gallium nitride layer containing an n-type dopant on a substrate. 2A to 2D are diagrams schematically showing a method of forming a nitrided layer in the embodiment, a method of manufacturing a gallium nitride substrate using the gallium nitride layer, and a method of manufacturing a epitaxial substrate using the gallium nitride substrate. Figure. Fig. 3 A and Fig. 3 show a diagram showing a specific example of the temporal change of the substrate temperature. ° Fig. 4 is a view showing a step of forming a gallium nitride layer. Fig. 5 is a view showing a manufacturing step of a gallium nitride substrate. Fig. 6 is a view showing experimental results of forming a GaN layer in Reference Example - Reference Example 1-2, and Example 丨-丨 to Example 2_4. Fig. 7 is a graph showing the results of an experiment after forming a GaN layer in Examples 3-1 to 3-2. Fig. 8 is a view showing the results of an experiment after forming a GaN layer in Example 4-1 to Example 4 - 5 4 . Fig. 9 is a view showing the results of an experiment after forming a GaN layer in Examples 5-1 to 5-8. 130592.doc -37- 200848558 Fig. 10 is a view showing the results of an experiment after forming a GaN layer in Examples 6-1 to 6-10. Fig. 11 is a view showing the results of an experiment after forming a GaN layer in Examples 7-1 to 10-2. Fig. 12 is a view showing experimental results of forming a GaN layer in Reference Example 2-1 to Reference Example 2-2, and Example 11-1 to Example 丨2_4. Fig. 13 is a view showing the results of an experiment after forming a GaN layer in Examples 13-1 to 13-2. (Fig. 14 is a view showing experimental results of forming a GaN layer in Examples 14-1 to 1444. Fig. 15 is a view showing experimental results of forming a GaN layer in Examples 15-1 to 15-8. Fig. 16 is a view showing the results of the inspection after forming a GaN layer in Examples 16-1 to 16-10. Fig. 17 is a view showing the formation of a GaN layer in Examples 17-1 to 20-2. Figure 18 is a cross-sectional view of the LED. Figure 19A, 19B is a cross-sectional view of the LD. Figure 20 is a cross-sectional view of the HEMT. - Figure 2 is a cross-sectional view of the Schottky diode. Fig. 22 is a cross-sectional view of a vertical MIS transistor. Fig. 2 shows the yield of the semiconductor element after the reference example 3-1 to the reference example 4 to 2, and the embodiment 21 -1 to the embodiment 22-3 Fig. 24 is a view showing yields of semiconductor elements after fabrication of Reference Example 5-1 to Reference Example 6-2, Example 23-1 to Embodiment 130592.doc-38-200848558 24-3. Fig. 25 shows a reference example. 7 to Reference Example 9, and Example 25 to Example 27, the yield of the semiconductor element after fabrication. [Description of main component symbols] 10 Hydride VPE device 12 Growth furnace 14 Block 16 graft supply 18 &gt; 32 heater 24 矽 supply 26 oxygen supply 28 HC1 supply 30 nitrogen supply 34 control device 50 substrate 5 52 gallium nitride layer 52a, 54a surface 54 gallium nitride substrate 56, 58 &gt; 60 nitride semiconductor layer 62 stray substrate 110 LED 120 LD 130 HEMT 140 Schottky diode 130592.doc -39- 200848558 150 vertical MIS transistor 201 n-type GaN layer 202 n-type AlGaN layer 203 light Layer 204 p-type AlGaN layer 205, 221d p-type GaN layer 206 n-type GaN buffer layer 207 n-type AlGaN cladding layer 208 n-type GaN optical waveguide layer 209 active layer 210 non-doped InGaN degradation preventing layer 211 p-type AlGaN cladding layer 212 p-type GaN optical waveguide layer 213 p-type AlGaN cladding layer 214 p-type GaN contact layer 215 bump 216 SiO 2 insulating film 221 group III nitride semiconductor layer, η 221 a i-type GaN layer 221 b i-type AlGaN layer 221 c rf-type GaN Layer 221e n+ type GaN layer 251 p side electrode 252 η side electrode type GaN layer 130592.doc -40- 200848558 253 source electrode 254 gate electrode 255 gate electrode 256 ohm electrode 257 Schottky electrode t〇Λ ti ! To engraved growth temperature annealing end temperature T Θ angle 130592.doc -41 -

Claims (1)

200848558 十、申請專利範圍： L :種氮化鎵層之形成方法，其係載子濃度為1X10&quot; cm-3 以上之氮化鎵層之形成方法，且包括： 於基板上形成包含n型摻雜物之氮化鎵層之步驟，及 將上述基板上所形成之上述氮化鎵層加熱之步驟。 2·如請求们之氮化鎵層之形成方法，《中以8〇吖以上加 熱上述氮化鎵層5分鐘以上。 3 ·如請求項1之氮化鎵層 u◦琢之形成方法，其中以5〇〇c/分鐘以 下之降溫速度加熱上述氮化鎵層。 4 ·如請求項1之氮化鎵層 少 豕層之形成方法，其中上述氮化鎵層 之表面係自上述氮化鎵層之（〇〇〇1)面傾斜〇〇3。以上。 5·如請求们之氮化鎵層之形成方法，其中上述氮化鎵層 之位錯密度為lxl〇7cm·2以下。 6· 一種氮化鎵層之形成方法，贫4 t , 、 η 风万忐其包括於基板上形成載子濃 度為1x10 cm以上且包含11型摻雜物之氮化鎵層之 驟， 上述氮化鎵層之表面#白卜、七各&amp; ^ P π田你自上述虱化鎵層之（〇〇〇1)面傾 斜0.03。以上。 7.如請求項6之氮化鎵層之采土、 ^ , t ^ ^ 外㈢又形成方法，其中上述氮化鎵層 之位錯密度為lxl〇7cm-2以下。 8. 種氮化S豕基板’該_彳μ # 4乳化鎵基板之載子濃度為1Χ1017 cm·3以上，並包含η型搀雜舲 0曰士人 ^雜物，且具有自該氮化鎵基板之 (0001)面傾斜0·03。以上之表面。 9·如請求項8之氮化鎵基板，1 φ 双 具甲该虱化鎵基板之位錯密 度為lxl〇7cm-2以下。 130592.doc200848558 X. Patent application scope: L: a method for forming a gallium nitride layer, which is a method for forming a gallium nitride layer having a carrier concentration of 1×10&quot; cm-3 or more, and comprising: forming an n-type doping on a substrate a step of a gallium nitride layer of the impurity and a step of heating the gallium nitride layer formed on the substrate. 2. If the gallium nitride layer is formed by the requester, the above-mentioned gallium nitride layer is heated by more than 8 中 for more than 5 minutes. 3. The method of forming a gallium nitride layer according to claim 1, wherein the gallium nitride layer is heated at a temperature decreasing rate of 5 〇〇c/min or less. 4. The method of forming a gallium nitride layer of claim 1, wherein the surface of the gallium nitride layer is inclined by 〇〇3 from a (〇〇〇1) plane of the gallium nitride layer. the above. 5. A method of forming a gallium nitride layer as claimed, wherein the gallium nitride layer has a dislocation density of 1 x 10 〇 7 cm · 2 or less. 6· a method for forming a gallium nitride layer, which comprises a step of forming a gallium nitride layer having a carrier concentration of 1×10 cm or more and containing a dopant of type 11 on a substrate, wherein the nitrogen is depleted The surface of the gallium layer #白卜,七各&amp; ^ P π田 You are inclined by 0.03 from the (〇〇〇1) plane of the above gallium antimonide layer. the above. 7. The method of forming a gallium nitride layer according to claim 6 and forming a ^, t ^ ^ outer (3) method, wherein the dislocation density of the gallium nitride layer is lxl 〇 7 cm -2 or less. 8. The nitriding S 豕 substrate 'The _ 彳 μ # 4 emulsified gallium substrate has a carrier concentration of 1 Χ 1017 cm·3 or more, and includes η-type 搀 舲 0 曰 人 ^ , , , , , , , , , The (0001) plane of the gallium substrate is tilted by 0·03. The above surface. 9. The gallium nitride substrate according to claim 8, wherein the dislocation density of the gallium antimonide substrate is 1 x l 〇 7 cm -2 or less. 130592.doc
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