TW200845735A - Solid-state imaging device and imaging apparatus - Google Patents

Abstract

There is provided a solid-state imaging device, which includes: a comparator for sequentially comparing a predetermined level of an analog pixel signal obtained from a plurality of pixels with a reference signal which is gradually changed and used for converting the predetermined level into digital data; a counter for performing a count processing in parallel with a comparison processing for the predetermined level in the comparator, and holding a count value at a time of completing the comparison processing to obtain digital data indicative of a value obtained by adding the plurality of pixel signals; and an addition spatial position adjusting unit for controlling a selection operation for selecting spatial positions of the plurality of pixels to be processed in the comparator and a ratio of a weight value during the addition to adjust spatial positions of pixels after addition.

Description

[Technical Field] The present invention relates to a solid-state image pickup device and an image pickup apparatus, which are examples of a semiconductor device for detecting a physical quantity distribution. More specifically, the present invention relates to a mechanism comprising a plurality of arranging unit elements having sensitivity to electromagnetic wave input such as light or radiation from the outside, and reading by the unit elements is converted into an electrical signal. An entity quantity distribution converts an analog electrical signal into digital data and outputs digital data to the outside. [Prior Art] In recent years, in the example of a solid-state image pickup device, a metal oxide semiconductor (MOS) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor have been attracting great attention, which can solve the charge. Various disadvantages of the coupling device (CCD) camera sensor. For example, a CMOS camera device has an amplifying circuit for each pixel, such as a floating diffusion amplifier, and when a CMOS image sensor senses a pixel signal, as an address control, a so-called line parallel output type or line type method is often used. Wherein, one column of a pixel array unit is selected and one column of pixels is simultaneously accessed in a row and a column, that is, all the pixels of one column are simultaneously and parallelly read by the pixel array unit. Furthermore, the solid-state imaging device can adopt a method in which an analog pixel signal read from a pixel array unit is converted into digital data by an analog-to-digital converter (A/D converter), and the digital data is output to external. -4- 200845735 This is like a parallel parallel output type camera sensor, and various types of signal output circuits have been developed. There is proposed a method as a most advanced type in which an A/D converter is provided for each line and a pixel signal is outputted to the outside as digital data (for example, refer to Japanese Patent Application Laid-Open No. Hei No. 2005-278135). Furthermore, in an A/D conversion method, various methods have been considered in terms of circuit specifications, processing speed, and resolution. Single slope integration or ramp comparison A/D conversion method for A/D conversion method. In this method, a class of analog signal is compared to a reference signal for digital signal conversion, and a counting process is performed in parallel with the comparison operation. According to this, the number signal of the unit signal is obtained by counting 値 when the comparison operation is completed. This method is also employed in the above patent documents. SUMMARY OF THE INVENTION The addition processing has been performed in a solid-state image pickup device such as a digital camera, which is used as a device for converting light into an electric signal to be output as an image signal. For example, the addition processing used to reduce the number of pixels depends on an example such that when pixels are captured, all pixels are read or when the animation is captured, the pixels are added and thinned for high speed. read out. Since a CMOS camera sensor converts a pixel signal into an electrical signal for each pixel, this addition processing function can be easily added thereto. The solid-state image pickup device disclosed in the above patent document also employs this addition processing system. However, by performing a simple addition process, the coefficients of the added target pixels are made uniform, but due to the relationship of the spatial positions of the pixels after the addition, the high-resolution addition image can always be obtained. This is typically because the spatial locations after the addition are not equidistant. The present invention has been accomplished in view of the above circumstances and provides a mechanism for obtaining an added image with high resolution. In a solid-state image pickup device according to an embodiment of the invention, it comprises: a comparator and a counter. The comparator first compares a predetermined level (e.g., a reset position or signal level) of the analog pixel signal obtained from a pixel with a gradually changing reference signal and converts the predetermined level into digital data. The counter is connected in parallel to the comparison processing performed by the comparator, performs a counting process' and obtains the pre-aligned digital data by retaining the count 値 when the comparison processing is completed. In other words, as a mechanism relating to A/D conversion of a pixel signal, an A/D conversion system of a so-called single-slope integration type or a ramp-wave signal comparison type is employed. In the mechanism according to an embodiment of the present invention, an addition spatial position adjustment unit is provided. The addition spatial position adjustment unit controls the selection operation of the selection spatial position of the majority of pixels to be processed in the comparator and the ratio of the weights 値 at the time of addition to adjust the spatial position of the pixels after the addition. "By controlling the ratio of the weights 値 at the time of addition, to adjust the spatial position of the pixels after the addition, the sentence indicates that the spatial position of the added pixels is adjusted" so that the resolution of the added image is high. Performing a simple addition, wherein each weighted 値 of the added target pixel is uniform. Preferably, for this purpose, the 'additional space position adjustment unit controls the weighted 値 ratio at the time of addition so that each of the added The spatial position of one pixel is arranged to be equidistant. -6 - 200845735 If the pixel is provided with a color filter for generating a color image, the addition spatial position adjustment unit controls the selection to be performed for most of the pixels performed by the comparator The spatial position selection operation causes pixel systems having the same color to be added, and controls the ratio of the weights 値 at the time of addition such that the spatial position of each pixel is arranged equidistant. If each pixel is added The subsequent spatial position is adjusted by setting an appropriate weight ,, and the pixel positions after the addition can be arranged in an optimal state to be equidistant. As a result, it is possible to surely prevent the solution. The resolution is lowered or the resolution is lowered, and if the image is added by simple addition processing, the resolution is sometimes lowered. The solid-state imaging device may sometimes be a single-chip type or a module having an imaging function. A group type in which an image pickup unit, a signal processor or an optical system is packaged. Further, the present invention can be applied not only to a solid-state image pickup device but also to an image pickup device. At this time, the image pickup device can be similarly obtained. The same advantages of the solid-state camera device. The camera device can be, for example, a camera or a mobile device with a camera function. In addition, "camera, not only for capturing normal images with a camera, but also for fingerprint detection in a broad sense. These and other features and aspects of the present invention are described in detail with reference to the drawings. [Embodiment] An embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the following example, a CMOS solid-state image pickup device is taken as an example, which is a 200845735 X-Y address type solid-state image pickup device. Furthermore, each pixel in the CMOS solid-state image pickup device is constituted by an NMOS. However, this is an example and the device is not limited to the MOS camera. All of the embodiments described hereinafter can be applied to all semiconductor devices for detecting the physical quantity distribution, which include a plurality of unit elements arranged in a linear or matrix shape, which are sensitive to light or electromagnetic waves input from the outside. [Summary of Solid-State Imaging Device] FIG. 1 is a schematic diagram of a CMOS solid-state imaging device (CMOS imaging sensor) according to an embodiment of the present invention. The solid-state image pickup device 1 has a pixel unit in which a plurality of pixels including a light receiving element (e.g., a charge generator) are output, which output signals corresponding to the amount of incident light, and are arranged in rows and columns (i.e., two-dimensional matrix shape). The signal output from each pixel provides a voltage signal. The solid-state imaging device 1 includes both a co-correlated double sampling (CDS) processing functional unit and an analog digital converter (ADC), which are arranged in parallel in a row. The "CDS processing function unit and the ADC are arranged in parallel in a row" means that most of the CDS processing function units and the ADC system are arranged in a manner of being substantially parallel to the vertical signal line 1 9 (row signal line) in the vertical line. When the apparatus is viewed in a plane, most of the functional units may be arranged only on one end side of the row direction of the pixel array unit 10 (outside of the lower portion in the drawing). Alternatively, the functional units may be arranged separately on one end side of the row direction of the pixel array unit 1 (outside of the lower portion of the drawing) and on the other side opposite to one end (upper portion in the drawing). In the latter case, preferably, horizontal scanners for performing readout scanning (horizontal scanning) in the column side-8 - 200845735 are arranged on both sides of the pixel array unit 1 , so that the horizontal scanner can Independent operation. For example, a typical example in which a CDS processing functional unit is arranged in parallel with an ADC is a row type in which a CDS processing functional unit and an ADC system for each vertical line are arranged for use in a portion called a row region. The line area is arranged on the output side of the camera unit, and the signal system is sequentially read out to the output side. Alternatively, not only the row type, but also a CDS processing functional unit and an ADC to a majority (eg, two) adjacent signal lines 19 (vertical rows), or a CDS functional unit and an ADC may be assigned to the N vertical signal line 19 ( The vertical line is on the other N lines (N is a positive integer; there is (N-1) between the two lines). Since any structure other than the row type has a structure in which a CDS processing functional unit and an ADC are shared by a plurality of vertical signal lines 19 (vertical lines), a switching circuit (switch) is provided for supply. Most of the majority of the row of pixel signals from pixel array 10 are coupled to a CDS processing functional unit and an ADC. The memory used to store the output signal may necessarily depend on the processing in the latter step. In either case, by specifying a CDS processing functional unit and an ADC to a plurality of vertical signal lines 1 9 (vertical lines), signal processing can be performed on the pixel signals after the pixel signals are purchased in units of pixels f. on. Therefore, the architecture of each unit pixel can be simplified compared to performing similar signal processing in each unit pixel, and therefore, a smaller and lower cost image sensor of multiple pixels can be implemented. In addition, the pixel signals in a single column can be simultaneously processed in parallel by a plurality of signal processors arranged in parallel in line -9-200845735. The number processor can operate at a slower speed than the output of the output circuit or one of the devices and the processing performed by an ADC. Rate consumption, band efficiency, noise, etc. are advantageous. In other words, when the rate consumption and band performance are similarly set, the entire sensor can be operated. The row type architecture can operate at low speeds and has advantages in power consumption, noise, and also does not require switching circuits (switches). The examples describe the line type except for special instructions. As shown in FIG. 1 , a solid-state camera according to an embodiment of the present invention includes: a pixel array unit 10 in which a plurality of unit pixels 3 are series and rows, which are also referred to as pixel units or a camera unit; and a drive 7 provides external pixels. The array unit 10; the read current supply 24 gives an operating current (read current) for reading out the pixel signal to the unit pixel 3 in the unit 10; the line processor 26 includes the line A/D in the vertical line The circuit 25; the reference signal generator supplies the reference signal Vslop for A/D conversion to the line f to an output unit 29. These functions can be used with any reference signal Vsl〇p provided on the same semiconductor substrate as long as it has a waveform that varies linearly with a predetermined slope; and has a smooth slope-shaped waveform, or a one-step waveform, which is sequentially Changes can be used. The row A/D circuit 25 in this embodiment has a function A/D converter which takes one as the basic position of the pixel signal So, which is implemented for the power of the CDS function, which is implemented below the high-speed band performance. The image device 1 is arranged as a dynamic controller for arranging the pixel array at each of the 27 for I 26 ; A signal, the change of the level of the person, including a quasi reset -10- 200845735 level Srst and a signal level Ssig independently converted to digital data, and a parameter processor, which performs a reset level Srst The difference between the A/D conversion result and the A/D conversion result of the signal level Ssig is processed, and the digital data of the signal component represented by the difference between the reset level Srst and the signal level Ssig is obtained. In the previous stage or the subsequent stage of the line processor 26, an automatic gain control (AGC) circuit having a signal amplifying function is disposed in the same semiconductor region, and a row processor 26 is arranged therein if necessary. When AGC, the analog amplification is performed at the previous stage of the line processor 26, and at the time of AGC, the digital amplification is performed at the next stage of the line processor 26. Since the tone seems to be corrupted when the η bit digital data is simply enlarged, preferably, the data is amplified in an analogous form and then digitally converted. The drive controller 7 includes control circuitry for sequentially reading signals from the pixel array unit 1 。. For example, the drive controller 7 includes: a horizontal scanning circuit (row scanning circuit) 12 having a horizontal decoder 12a and a horizontal driving unit 12b, which controls row addressing or line scanning; has a vertical decoder 14a and a vertical driving unit 14b. A vertical scanning circuit (column scanning circuit) 14' which controls column addressing or column scanning; and a communication/timing controller 20 having an internal clock function. In the vicinity of the communication/timing controller 20 of Fig. 1, a clock converter 23 can be arranged which generates a high speed clock generator having a pulse having a clock frequency faster than the input clock frequency. The communication/timing controller 20 generates an internal clock ' via the terminal 5a according to the input clock (main clock) CLK0 or a high-speed clock is generated in the clock converter 23. -11 - 200845735 According to the high speed clock generated in the clock converter 23, a signal is used to complete the high speed A/D conversion processing. The use of a high speed clock also makes it possible to perform motion extraction or compression that requires fast calculations. It is also possible to convert the parallel data output from the processor 26 into serial data and output it to the outside of the device as the video material D1. With this architecture, high-speed operation can be performed with fewer bits than the A/D conversion digital data. The clock converter 23 has a built-in multiplying circuit for generating a clock frequency that is higher than the input clock frequency. The clock converter 23 receives the low speed clock CLK2 from the communication/timing controller 20 and generates a clock having twice the frequency of at least the low speed clock CLK2. If kl is the frequency multiple of the low speed clock CLK2', the k1 multiplying circuit can be set for the clock converter 23, and various known circuits can be used as the multiplying circuit. In Figure 1, not all rows and columns are shown for simplicity. However, actually, tens to thousands of unit pixels 3 are arranged in each column or each row to form the pixel array unit 1 〇. Typically, each of the pixels 3 includes a photo-polar body as a light-receiving unit (charge generator), and an in-pixel amplifier having an amplifying semiconductor element (e.g., a transistor). The in-pixel amplifier can be a circuit capable of outputting a signal charge which is generated and accumulated in the charge generator in the unit pixel 3 as an electric signal, and various structures can be used as an in-pixel amplifier. It is usually used as a diffusion amplifier structure. For example, a floating diffusion amplifier comprising four transistors arranged in a single generator is typically used in C Μ Ο S-type inductors. The four transistors are: a readout selection transistor, which is an example of a charge readout unit -12-200845735 (transfer gate/readout gate); a reset transistor, which is an example of a reset gate; Selecting a transistor; and amplifying the transistor of a source follower structure, which is a detecting element for detecting a possible charge in the floating diffusion (for example, refer to FIG. 2 as described later) or, possibly using A floating diffusion amplifier having three transistors 'i.e., an amplifying transistor connected to a drain line (DRN) is used to amplify a signal voltage corresponding to the charge generator; and a reset transistor is used to The charge generator is disposed; and a read select transistor (transistor gate) is a vertical shift register that is scanned via a transfer line (TRF). In the solid-state image pickup device 1, the pixel array unit 10 can be made to perform color imaging by using a dichroic filter. More specifically, any of the color filters of the color separation filter can be arranged in a so-called Bayer configuration to arrange electromagnetic waves in the pixel array unit 1 to receive each charge generator (for example, a photodiode). The light in the example) is used to complete color imaging, wherein the filter is made up of a combination of color filters having multiple colors. If the color filter is arranged in a Bayer configuration as shown in Figures 8 and 12-14, G (green) and R (red) filters or B (blue) and G (green) filters are arranged. In the same column, they are arranged in a two-dimensional grid. The unit pixel 3 is connected to the vertical scanning circuit 14 via a column control line 15 for selecting a column and connected to the line processor 26 via a vertical signal line 19, wherein the row A/D circuit 25 is arranged in each vertical line in. The column control line 15 represents all of the lines from the vertical scanning circuit 14 to the pixels. The horizontal scanning circuit 12 has a function of a readout scanner for reading the count from the processor 26 to the horizontal signal line 18. The output circuit 28 is set to the next stage (output side) of the horizontal signal line 18 from -13 to 200845735. A digital arithmetic unit 29 can be provided in the previous stage of the output circuit 28 if necessary. "If necessary, it means that when there is a need for other processing regarding the horizontal direction. Therefore, the digital arithmetic unit 29 has a function of performing addition processing of a plurality of lines of data for the horizontal direction. In addition, 'depending on the horizontal signal line 1 A line connection of 8 is provided for storing data of a plurality of added target lines. For example, when a plurality of target lines are transmitted to the line connection of the digital arithmetic unit 29 via the horizontal signal line 18 of the individual system, Memory is required. If a majority of the added target lines are transmitted via the horizontal signal line 18 of a system, the memory is required to store the data of the added target line. The horizontal scanning circuit 12 synchronizes with the low speed clock CLK2, and sequentially selects the lines. The row A/D circuit 25 in the processor 26 directs the signal to the horizontal signal line (horizontal output line) 18. For example, the horizontal scanning circuit 12 has a horizontal decoder 12a for defining the readout line in the horizontal direction. (Selecting individual row A/D circuits 25 in row processor 26), and horizontal drive unit 12b for each signal of row processor 26 as defined by horizontal decoder 12a The out address is directed to the horizontal signal line 18. The horizontal signal line 18 is arranged, for example, for the number of bits η processed by the row A/D circuit 25 (n is a positive integer) if 1 〇 (= η) bits The pixel array unit 10 line is arranged to correspond to the number of bits. Each element of the drive controller 7, such as the horizontal scanning circuit 12 and the vertical scanning circuit 14 is formed together with the pixel array unit 1 On a semiconductor region formed by a single crystal germanium or the like, this is performed by using a technique similar to that of the semiconducting-14-200845735 bulk body circuit fabrication technique to form a solid-state image pickup device such as a semiconductor system. These individual functional units form the present embodiment. A portion of the solid-state imaging device 1 in the example, also referred to as "single-wafer type" (provided on the same semiconductor substrate), includes each functional unit integrally formed on a semiconductor region made of a single crystal germanium or the like. This is performed by using a semiconductor integrated circuit manufacturing technique to become a CMOS image pickup device such as a semiconductor system. The solid-state image pickup device 1 may be of a single wafer type in which individual components are The body is molded on the same semiconductor component, but it is not shown, and may also be a module type having an image pickup function, except for various signal processors of the pixel array unit 1 , the drive controller 7 and the line processor 26 . An optical system such as a pick-up lens, an optical low-pass mirror, or an infrared cut-off filter is packaged. The horizontal scanning circuit 12 and the vertical scanning circuit 14 include, for example, a decoder and are supplied in response to the self-communication/timing controller 20. The control signals CN2 and C N1 start a shift operation (scan). Therefore, the column control line 15 includes various pulse signals for driving the unit pixel 3 (for example, the pixel reset pulse RST, the transfer pulse TRG, and a vertical Select pulse VSEL). Although not seen, the communication/timing controller 20 has a functional block of a timing generator TG (eg, a read address control device) that supplies a clock and predetermined timing pulse signals required for each unit operation, and A functional block of a communication interface receives a main clock CLK0 supplied from an external main controller via a terminal 5a, and receives data DATA indicating an operation mode and the like supplied from an external main controller via the terminal 5b, and outputs a solid state including Photo -15- 200845735 Information from device 1 to the external host controller. For example, the communication/timing controller 20 outputs a horizontal address signal to the horizontal decoder 12a and outputs a vertical address signal to the vertical decoder i4a. Each decoder receives the signal and selects the corresponding column or row. At this time, since the unit pixels 3 are arranged in a two-dimensional matrix, it is preferable to perform high-speed reading of pixel signals and pixel data by performing the following steps: performing (vertical) scanning reading, in which pixel signals are The analog pixel signal generated by the generator 5 and output via the vertical signal line 19 is accessed and read in column units (in a row parallel manner), and then (horizontal) scan reading is performed, where the pixel signal (this The digital pixel data in the example is accessed in the column direction in the column direction, which is the arrangement direction of the vertical lines, and is read out to the outside. Of course, not only the scanning and reading are performed, but also the random access can be completed by directly specifying the address of the pixel unit 3 to be read, so that only the necessary unit pixel 3 can be read. The communication/timing controller 20 supplies a clock obtained by dividing the clock CLK1 having the same frequency as the main clock CLK0 via the terminal 5a, dividing the clock CLK1 by 2, or further dividing the clock CLK1 by the obtained low-speed clock to each unit in the device, for example To the horizontal scanning circuit 1, the vertical scanning circuit 14, and the line processor 26. In the following, a clock obtained by dividing by 2 or a clock having all of the acquired clocks is referred to as a low-speed clock C L K 2 . The vertical scanning circuit 14 selects a column of the pixel array unit 1 , and supplies the necessary pulses to the selected column. For example, the vertical scanning circuit 14 has a vertical decoder 14a for defining one of the readout columns in the vertical direction (selected - one column of the pixel array unit 10), and a vertical drive unit 14b for supplying a pulse - 16- 200845735 The read address (in the column direction) defined by the vertical decoder for driving to the control line 15 of the cell pixel 3. The vertical decoder 14a simultaneously defines a readout column and also selects a column as an electronic shutter. In this embodiment, it is possible to select an A/D conversion operation, that is, a normal frame mode, to progressively scan to read the information of the unit pixel 3 and increase the frame rate by N times the high-speed frame rate according to each operation mode. The speed is twice as high as the normal frame mode. Preferably, in addition to sequentially scanning in the normal frame rate mode with the horizontal decoder 12a, the horizontal scanning circuit 12 or the vertical scanning circuit 1 4 address decoder, arbitrarily selects the columns and rows to be processed, The addition read operation or the decimal read operation can be performed in the high-speed frame mode. In particular, when the color separation filter for capturing the color image is provided in the relationship with respect to the phase-out operation, each of the pixels in the pixel array unit 1 is provided. Preferably, at least in the vertical scanning circuit 14, the addition can be performed on the unit pixels 3 having the same color. For the parallel A/D conversion processing, the addition processing is performed in the vertical direction, and a vertical decoder 14a is preferably provided for selecting the control line 15 at least in the vertical scanning circuit 14. When capturing a color image, color mixing occurs if the addition process is performed on pixels having different filter elements. On the other hand, if the pixels are reasonably executed on pixels having the same color, for example, in Bayer with pixels in odd or even columns, color mixing does not occur. "Parallel to A/D conversion, performing the addition processing in the vertical direction" on the last addition processing target column in the majority addition processing target column

p 14a In addition to the execution of the example, the execution includes the reading of the meta-image processing in the ground, and the count of the conversion processing result indicated by the A/D -17-200845735 in the optional color element plus processing displays a state, wherein The results of the A/D conversion process performed on the pixel signals of the unit pixels 3 in the majority of the processing target columns are added. In particular, if the CDS processing is performed together with the A/D conversion in the counter 2 54 , the count 値 displays the addition result of the pixel signal components. In other words, this means that the addition processing in the vertical direction is performed together with the A/D conversion processing in the row A/D circuit 25. Of course, this is not necessary in this case. It is also possible to perform the addition processing by digital arithmetic processing after reading out the readout columns listed in the vertical direction of the sequential scanning, and use the simple scanning circuit for sequentially selecting the readout columns without using the arbitrarily selectable readout. Column vertical decoder 1 4a. However, when external memory (for line memory of most columns) is necessary, the data of the majority of the added target columns is stored. Alternatively, in addition to the line processor 26, the majority of the addition target columns are individually read and added to the digital arithmetic processing. At this time, external memory (line memory for a plurality of columns) is not required. However, the disadvantage is that the circuit scale is larger because the row processor 26 (row A/D circuit 25) and the reference signal are generated. The processor 27, the horizontal scanning circuit 12 and the vertical scanning circuit 14 do not need to be placed in each of the plurality of columns. For example, if the addition process performs two columns, the above two circuits are arranged with the pixel array unit 10 in between. On the contrary, if the addition processing in the vertical direction is performed in parallel with the A/D conversion processing in the row A/D circuit 25, there is an advantage that the external memory or the majority system line processor 26 is not required. In response to this, the present embodiment employs a mechanism for performing the addition processing in the vertical direction and the A/D conversion processing in the line -18-200845735 A/D circuit 25 together. On the other hand, the addition processing in the horizontal direction for the unit pixels 3 having the same color can be performed by using a simple sequential scanning circuit that sequentially selects the readout lines after sequentially scanning the horizontal direction for reading. The addition of the target unit pixel 3 having the same color is selected in the arithmetic processing without using the horizontal decoder 12a which can arbitrarily select the readout line to the output circuit 28. Alternatively, the addition processing may be performed while completing the appropriate switching in the readout column order selected by the horizontal decoder 1 2a so that the addition target units having the same color are read after being sequentially read in accordance with the selection order in the horizontal direction. The elements of pixel 3 are sequentially transferred to elements of unit pixels of the same color that are sequentially transmitted by digital arithmetic processing (e.g., using a digital arithmetic unit 29). Furthermore, as described in Japanese Patent Application No. 2005-278 135, that is, its fourth and fifth embodiments, an architecture may be employed in which it may be implemented, for example, in odd rows (for example, the first row and the third row). ), or adding pixels on even lines (for example, the second line and the fourth line), or a combination of lines in which pixels are added can be arbitrarily switched by arranging a selection switch to be in the pixel array unit Switching a read target line with the row A/D circuit 25, and by arranging each pair of line processors 26 (row A/D circuit 25), reference signal generator 27, horizontal scanning circuit 12, and vertical scanning Circuit 1 4 to switch pixel array unit 10. In the solid-state image pickup device 1 having this configuration, the pixel signals output from the unit pixel 3 are supplied to the row A/D circuit 25 in the line processor 26, via each vertical line, via the vertical signal line 19 . -19- 200845735 Each row A/D circuit 25 in row processor 26 receives the analog signal So of a pixel in a column and processes the analog signal So. For example, each row of A/D circuits 25 has an analog-to-digital converter (ADC) circuit that converts an analog signal into, for example, a 10-bit digital signal, and is used, for example, for a low-speed clock CLK2. The A/D conversion process performed in the line processor 26 uses an analog A/D conversion method for each column, using the row A/D circuit 25 arranged in each row to store the analogy in parallel in each column. The signal is carried out. At this time, a single slope integral (or ramp signal comparison) A/D conversion technique is used. Since this technique can implement the A/D converter in a simple structure, even if the A/D converters are arranged in parallel, the circuit scale does not increase. In order to add single-slope integral A/D conversion, the processing target analog signal is converted into a digital signal according to the self-conversion start until the matching reference signal Vslop and a processing target signal voltage. In principle, the ramp waveform reference signal Vslop is supplied to the comparator (voltage comparator), and at the same time, the count starts with the clock signal. The A/D conversion is performed to count the clock until the pulse signal is obtained, which indicates the comparison between the analog pixel signal input via the vertical signal line 19 and the reference signal Vslop. Furthermore, at this time, with respect to the pulse signal input in the voltage mode via the vertical signal line 197, by introducing an appropriate circuit, it is possible to perform an operation by A/D conversion to remove after resetting the pixel. The difference between the signal level (called the noise level or the reset level) and the true signal level V sig corresponding to the amount of light. This operation is equivalent to the so-called CDS processing. In this way, the noise signal components such as fixed pattern noise (FPN) or reset noise are thus shifted. -20- 200845735

[Details of Reference Signal Generator and Row A/D Circuit] The reference signal generator 27 includes a DA converter (DAC) 27a. The reference signal generator 27 synchronizes with the count clock CKdac by the communication/timing controller 20 to generate a step sawtooth wave starting from the start point indicated by the control data CN4, or a ramp wave signal (hereinafter also referred to as a reference signal Vslop), and then The step sawtooth reference signal Vslop generated for the A/D conversion is supplied as a reference signal or an ADC reference signal to each of the row A/D circuits 25 in the line processor 26. Although not shown, a noise suppression filter is preferably provided. The reference signal Vslop generated by the multiplied clock (high-speed clock) generated by the multiplying circuit in the clock converter 23 can be changed faster than the one generated by the input of the terminal 5a according to the main clock CLK0. The control data CN4 supplied from the communication/timing controller 20 to the DA converter 27a of the reference signal generator 27 contains information to comply with the rate of change of the digital data with respect to time, so that the reference signal Vslop for each comparison process is basically Have the same rate of change. More specifically, a counting system is changed every unit time in synchronization with the count clock CKdac, and a counting converter is converted into a voltage signal by a DA converter of a current addition type. Under the control of the communication/timing controller 20, the DA converter 27a of the present embodiment can change (in a specific example, become larger) the variation characteristic of the reference signal Vslop (in a specific case) in the comparison processing in the voltage comparator 252 In the case of the slope). -21 - 200845735 The slope of the reference signal can be adjusted by changing the frequency (clock cycle) of the count clock CKdac. For example, when the frequency of the count clock CKdac supplied to the DA converter 27a is started to be the same as the frequency of the count clock CK0, preferably, once the predetermined count is reached, the frequency of the count clock CKdac becomes 2 Am times faster than the count. The frequency of the clock CK0. Specifically, when the first predetermined count is reached, the frequency of the count clock CKdac is twice as fast as the frequency of the count clock CK0, and when the second predetermined count is reached, the frequency of the count clock CKdac is four times faster than the count. The frequency of the clock CK0. The above method is only an example, and the change in slope is not limited to this method. For example, any circuit can be used in a method in which, when the cycle of the count clock CKdac supplied to the reference signal generator 27 is kept constant, the output has a potential calculated by y = a - yS * X, where X is a count 値, ^ is the start 値, and /3 is the slope (rate of change) of the reference signal Vslop contained in the control data CN4, or based on the information indicating the slope (rate of change) of the ramp voltage included in the control data CN4. The voltage Δ SLP change of each count clock CKdac is adjusted. The adjustment of the slope of the reference signal Vsi〇p can be implemented by varying the current in the unit current source in addition to changing the clock cycle, and adjusting Δ S L P per clock. The row A/D circuit 25 includes a voltage comparator 25 2 and a counter 254 and has an n-bit A/D conversion function. The voltage comparator 252 compares the reference signal Vslop generated from the DA converter 27a of the reference signal generator 27 with the vertical signal line i9 (h〇, H1, ...) supplied from the unit pixel 3 to each column control line 15 (V0). , VI, ...) analog pixel signals. • 22- 200845735 The counter 254 counts the time until the voltage comparator 252 completes the comparison process and stores the resulting count. In the present embodiment, the reference signal Vslop is supplied from the DA converter 2 7 a to the voltage comparators 2 5 2 arranged in the individual columns, and the comparison processing is performed by using each of the voltage comparators 2 5 2 The common reference signal Vslop on the processed pixel signal voltage Vx is performed. The communication/timing controller 20 has a control function to switch the count processing mode of the counter 254 depending on whether or not the voltage comparator 252 performs a comparison operation of the reset level Vrst of the pixel signal or the signal component Vsig. A control signal CN5 is supplied to the counter 254 in each row of A/D circuits 25 by the communication/timing controller 20 to instruct the counter 254 to execute the down mode or the up mode. The step reference signal Vslop generated by the reference signal generator 27 is input to an input terminal RAMP of the voltage comparator 252 and to the other input terminal RAMP of the other voltage comparator 252. The vertical signal line IX corresponding to the vertical line is connected to the other input terminal of the voltage comparator 252, and the pixel signal voltages from the pixel array unit 1 个别 are individually input. The output signal of the voltage comparator 252 is supplied to the counter 254. The count clock CK0 is input together by the communication/timing controller 20 to the clock terminal CK of the counter 254 and to the other clock terminal CK of the other counter 254. Similar to the reference signal Vslop, a multiplied clock (high speed clock) generated for the multiplication circuit of the clock converter 23 can be used as the count clock CK0. At this time, a higher resolution can be achieved than with the main clock -23-200845735 CLK0 input via the terminal 5a. The counter 2 5 4 has a characteristic that uses a common up/down counter (U/D CNT) regardless of the count mode, and the counting process can be completed by switching between the lower number operation and the upper number operation. Although the architecture of the counter 254 is not shown, the counter 254 can be implemented by modifying the wiring configuration of the data storage unit 265 with a latch into the sync counter, and by receiving a single count clock C Κ 0 Perform an internal count. However, in the present embodiment, it is preferable to use a non-synchronous counter as the counter 2 54, which can output a count output 値 without being synchronized with the count clock CK0. Basically, a sync counter can also be used, however, when a sync counter is used, all flip-flops, in other words, the operation of the counter base element are limited by the count clock CK0. Therefore, if higher frequency operation is required, it is preferable to use a non-synchronous counter suitable for high speed operation because its operation limit frequency is determined only by the limiting frequency of the first flip-flop. Although all the details will be described later, the line processor 26 (particularly the row A/D circuit 25) and the reference signal generator 27 in this embodiment have the following features: high speed frame rate at the use of the addition read operation During the mode, the frequency of the count clock of each bit (referred to as the count cycle) and/or the slope of the reference signal Vsl op supplied to the row A/D circuit 25 for each column are appropriately changed to perform the pair Each column applies a different weighted addition process in the vertical direction, so that the spatial position of each color in the vertical direction after the addition can be appropriately adjusted to an appropriate pitch to obtain a high resolution-24-200845735 Image. Preferably, the weighted addition performed by the digital arithmetic unit 29 is also performed in the vertical direction so that the spatial position of each color in the added horizontal direction can be adjusted to an appropriate pitch to achieve high An image of resolution. More specifically, at the time of the addition processing, by performing the weighted digital addition processing to change the weight of the added target pixel, the center of the added pixel is not eccentric in the vertical direction or the horizontal direction, but is moved. On the side to which the larger weight is applied. "Change the weight of the addition target pixel" means that at least one pixel of the addition target pixel has a different weight from the other pixels in the vertical direction and the horizontal direction. For example, in the addition processing of two pixels, the individual weighting can be set to a ratio of 1 to n (n is greater than 1). Preferably, n is a positive integer greater than 2 or any 値, such as 2, 3, 4, ..., etc., preferably η is a power of 2, such as 2, 4, 8, etc. Furthermore, in the case of digital addition processing, particularly in terms of processing time or dynamic range, preferably, a method is employed in which the slope of the reference signal Vsl op remains the same when the majority of the added target columns are processed, the counter The frequency of the clock is switched. Considering the flip-flop that accelerates each bit, it is better to use a method in which only the flip-flops in the more efficient bits or lower-effect bits are made to operate at high speed instead of making all bits positive. The counters operate at the local speed. A control pulse is input from the horizontal scanning circuit 12 to the counter 2 5 4 via the control line 1 2 c. The counter 254 has a latch function for retaining the count result 'and therefore' has a count 値 until a control pulse of -25-200845735 is received via the control line 〖2c as an instruction. The output side of the row A/D circuit 25 and the output from the counter 254 can be connected to the horizontal signal line 18. Alternatively, as shown in the figure, a data storage unit 25 stored as a η-bit unit stored in the counter 254 and a switch 2 58 arranged between the counter 254 and the data storage unit 256 may be arranged. At the next level of counter 254. If the architecture including the data storage unit 256 is employed, the memory transfer command pulse CN 8 as a control pulse is supplied to the switch 2 58 in the other vertical rows together with the communication/timing controller 20 at a predetermined timing. Other switches 2 5 8. When the memory transfer command pulse CN 8 is received, the switch 258 transmits a count corresponding to the counter 2 5 4 to the data storage unit 2 5 6 . The data storage unit 2 5 6 holds/stores the transmitted count 値. The mechanism for storing the counters of the counters 254 at a predetermined timing to the data storage unit 256 is not limited to the architecture in which the switches 258 are placed. For example, the mechanism can also be implemented by using an architecture in which the counter 254 is directly connected to the data storage unit 256 and the output enable of the counter 254 is controlled by the gS memory transfer command pulse C Ν 8 or The architecture, wherein the memory transfer command pulse CN 8 is used as a latch clock to determine the data acquisition timing of the data storage unit 256. The data storage unit 256 receives control pulses from the horizontal scanning circuit 12 via the control line 12c. The greedy storage unit 2 5 6 stores the count 取得 obtained from the counter 2 5 4 until the control pulse is received as an instruction via the control line i 2c. The horizontal scanning circuit 12 has a function as a readout scanning unit, and is -26-200845735 and is processed in parallel with each of the voltage comparators 252 and 256 in the line processor 26, and is read and stored in the data storage unit 2. Counting in 5 6 "The output of the data storage unit 2 5 6 is connected to the horizontal signal line 1 The flat signal line 18 has an η-bit wide signal line, which is the bit width of the row A/D power, and is via A sensing circuit corresponding to the individual input of the number n which is not shown is connected to the output circuit 28. In particular, if the data storage unit 256 is included in this architecture, the count results stored for the counter 254 can be transferred to the data store 256. Therefore, the counting operation of the counter 254, that is, the A/D conversion and the reading operation of the counting result of the horizontal signal line 18 can be individually made, so that the pipeline operation can be realized, wherein the A/D conversion processing and the signal reading operation thereto are performed. It can be done in parallel with each other. In this architecture, the row A/D circuit 25 performs a counting operation at the pixel signal readout period corresponding to the horizontal blanking, and counts the result at a predetermined timing. More specifically, first, the voltage comparator 252 compares the ramp voltage supplied from the test signal generator 27 with the pixel signal voltage lined through the vertical signal, and when the two voltages are equal to each other, the comparator output of the voltage ratio 252 Is reversed. For example, the voltage comparator 252 sets the potential level of the potential to be inactive, and when the pixel signal voltage is equal to the parameter Vslop, it is set to the L level (operating state). The counter 254 starts the counting operation in synchronization with the ramp voltage supplied from the reference signal generator 27, and the following number mode or the upper mode. When the comparator outputs the inverted information, the counter 2 54 stops counting the operation lock (hold/save). At this time, the count is used as the pixel data, and thus the number is straight. ! 〇水路25 outgoing line, then the deposit receipt processing ground control external cycle output self-referencing 1 9 converter comparator a source test letter to receive and latch complete -27- 200845735 A / D conversion. Subsequently, based on the shift operation of the horizontal selection signal CH(i) input by the horizontal scanning circuit 12 at a predetermined timing via the control line 1 2 c, the counter 254 sequentially outputs the storage/hold pixel data to the outside of the line processor 26 or Output to the outside of the wafer having the pixel array unit 10 via the output terminal 5c. Other various signal processing circuits may also be included in the elements forming the solid-state image pickup device 1, and since they are not directly related to the present embodiment, they are not displayed. [Pixel Unit] Fig. 2 is a view showing the structure of the unit pixel 3 used in the solid-state image pickup device 1 of Fig. 1, and the line connection between the drive unit, the drive control line, and the pixel transistor. The structure of each unit pixel (pixel unit) 3 in the pixel array unit 1 is similar to that of a general CMOS image sensor. In this embodiment, the 4TR structure is generally used in a CMOS sensor or a 3 TR structure including a tri-crystal can also be used. Needless to say, these pixel structures are merely examples, and any structure can be used as long as it is an array structure used in a general CMOS image sensor. In an in-pixel amplifier, for example, a floating diffusion amplifier can be used. For example, a pixel amplifier having four transistors (hereinafter referred to as "4 TR structure") generally used in a CMOS sensor can be used for each charge generator. The 4TR structure includes: a read select transistor, which is an example of a charge readout unit (transfer gate/readout gate); a reset transistor for resetting the gate; a vertical selection transistor; and a source Follow the amplifying transistor, which is a detector for detecting the potential change of the floating diffusion of -28 - 200845735. For example, a unit pixel 3 having a structure of 4 T R which is not in Fig. 2 includes a charge generator 32 and a four-electrode connected thereto. Specifically, the charge generator 32 has a charge accumulation function for accumulating charges; and a photoelectric conversion function for receiving light and converting the received light into a charge. The four transistors include a read select transistor (transfer transistor) 34, which is an example of a charge readout unit (transfer gate/readout gate), and a reset transistor 36, which is an example of a reset gate; The vertical selection transistor 40; and a source follower amplification transistor 4 2 ^ are detectors for detecting the potential change of the floating diffusion 38. The unit pixel 3 includes a floating diffusion amplifier (F D A) pixel signal generator 5 having a floating diffusion 38. The floating diffusion is an example of a charge injection unit having a charge product function and is a diffusion layer having a parasitic capacitance.曰 Buying the electrified transistor (the same as the transmission channel) 3 4 is a transmission line (read selection line Τχ) 55 driven by the transmission drive buffer BF1, and the buffer is supplied with the transmission signal Φ TRG. The reset transistor 36 is a reset line (RST) 56 driven by the reset drive buffer BF2, and the buffer BF2 is supplied with a reset signal Φ RST. The vertical selection transistor 40 is a vertical selection line (SEL) 52 driven by the selection drive buffer BF3, and the buffer BF3 is supplied with a vertical selection signal Φ VSEL. Each of the drive buffers can be driven by a vertical drive circuit 14b in the vertical scan circuit 14. The source of the reset transistor 36 in the pixel signal generator 5 is connected to the floating diffusion 38 and its drain is connected to the power supply VD (which can be common to the power supply Vdd), and a pixel reset pulse RST is Reset Drive Buffer -29- 200845735 BF2 Input to Gate (Reset Gate RG). For example, the drain of the vertical selection transistor 40 is connected to the source of the amplifying transistor 42, and the source is connected to the pixel line 51, and its gate (clearly referred to as "vertical selection gate SELV") is Connected to the vertical selection line 52. However, the wiring structure is not limited thereto, and the vertical selection transistor 40 may have its drain connected to the power source Vdd and its source connected to the drain of the amplifying transistor 42, and the vertical selection gate SELV may be connected to the vertical selection line 52. . The vertical selection signal Φ VSEL is supplied to the vertical selection line 52. The transistor 42 has its gate connected to the floating diffusion 38, its drain connected to the power supply Vdd via the vertical selection transistor 40, and its source connected to the pixel line 51 and the vertical signal line 53 (19). Furthermore, one end of the vertical signal line 53 extends toward the line processor 26, and the vertical signal line 53 is routed toward the line processor 26, connected to the sense current supply 24, thereby forming a source follower architecture. A substantially constant operating current (read current) is supplied between the vertical signal line 53 and the amplifying transistor 42. In particular, the sense current supply 24 includes an NMOS transistor (definitely referred to as a "load MOS transistor") 242 disposed in each vertical row, and a reference current source 244 includes current sharing for all vertical rows. The data storage unit 256, and an NMOS transistor 246, have a gate connected to the drain and a source connected to a source line 248. Each of the drain electrodes connected to the NMOS transistor 242 is connected to the corresponding vertical signal line 5 3 in the row and its source is connected to the source line 2 4 8 as a ground line. Therefore, the gate of the load ΝΜ S transistor -30-200845735 242 arranged in each vertical row is connected to the gate of the NMOS transistor 246 to form a current mirror circuit, which functions as a vertical signal line 1 9 current source. The source line 248 is connected to the ground (GND) at its end in the horizontal direction (the vertical lines shown in the left and right of Fig. 1), which is the substrate bias. The operating current (read current) for the ground applied to the NMOS transistor 242 is supplied from the left and right ends of the wafer. The load control signal SFLACT for allowing the current generator 24 5 to output a predetermined current is supplied to the current generator 245 by a load controller not shown, if necessary. When the signal is read, the current generator 245 having an active load control signal SFLACT is continuously allowed to use the load NMOS transistor 242 connected to the amplifying transistor 42 to flow a predetermined constant current at a predetermined constant current. In other words, the load NMOS transistor 242 supplies a sense current to the amplifying transistor 42 by forming a source follower and an amplifying transistor 42 disposed in the selected column, thereby outputting a signal to the vertical signal line 53. In the above-described 4TR structure, since the floating diffusion 38 is connected to the gate of the amplifying transistor 42, and the amplifying transistor 42 outputs a potential corresponding to the floating diffusion 38 in the voltage mode via the pixel line 51 (hereinafter referred to as "FD" The potential ") to the vertical signal line 53 (19). Reset the transistor 3 6 to reset the floating diffusion 3 8 . The read select transistor (transfer transistor) 34 transfers the signal charge generated by the charge generator 32 to the floating diffusion 38. A number of pixels are connected to the vertical signal line 197 to select a pixel, and only the vertical selection transistor 40 in the selected pixel is turned on. Therefore, only the pixel selected by the selected pixel is connected to the vertical signal line 159, and the pixel signal of the selected -31 - 200845735 is output to the vertical signal line 197. [Example of interface between voltage comparator and counter] Fig. 3 is a diagram showing an example of a connection interface beside voltage comparator 252 and counter 254. When the pixel signal voltage Vx read out from the pixel array unit 1 匹配 matches the reference signal Vslop supplied from the reference signal generator 27, the voltage comparators 2 5 2 of the corresponding vertical signal lines 19 in each row are inverted. The device output Comp is inverted from an inactive state (eg, a high level) to an active state (eg, a low level). The counter counter 254 includes a gate 502 for controlling (gates) the output of the count clock CK0 according to the comparator output Comp from the voltage comparator 252; and a count execution unit 504 for the slave gate 〇2 Counting the clock CIN and performing a counting operation. The communication/timing controller 20 supplies the slope change command signal CHNG to the reference signal generator 27, a count mode control signal UDC, the reset control signal CLR, the data hold control pulse HLDC, and the count clock control signal TH to the count execution unit 5, respectively. 04. In the slope change command signal CHNG, a signal system suitable for changing the slope of the reference signal Vslop in accordance with the DA converter 27a is used. For example, the slope change command signal CHNG may be a count clock CKdac capable of appropriately switching the frequency (clock cycle), or may be included in the control material CN4 as the slope (change rate) /3 of the reference signal Vslop. The communication/timing controller 20 can independently adjust the change reference signal -32- 200845735

The timing of the slope of Vslop and the timing of the counting cycle of the change counter 254 (counting execution unit 504). By controlling the vertical scanning circuit 14 to control a selection operation 'the selection is for selecting the spatial position of the majority of the pixels to be processed by the voltage comparator 252, and by adding the columns to the processing for processing in multiple columns. The weighting 时 at the time of addition of the frequency dividing speed adjustment, the communication/timing controller 20 also has an addition spatial position adjusting unit to adjust the spatial position of the added pixels. For example, in the addition processing operation of the first embodiment to be described later, in the majority addition target processing of the column, the slope of the reference signal Vslop of each column is kept the same, and the counting cycle (dividing speed) is Twist to switch. For example, when the weight of the previous column (addition target column) is applied to the next column (addition column), the counting cycle is completed faster in order to make the more efficient bit flip-flop operate at high speed. The count mode control signal UDC, the reset control signal CLR, the data hold control pulse HLDC, and the count clock control signal TH are supplied to the count execution unit 504 in the counter 254, thereby changing the frequency division operation of each bit. The output is L times this speed. If the speed of the frequency division operation is changed to L times the speed while keeping the slope of the reference signal Vslop constant 'actually' the A/D conversion system is performed with an L/time maximum A/D conversion gain. As a result, the addition processing can be performed with a weighting of L times. Further, in the second embodiment as will be described later, the processing operation 'except for the addition processing operation in the first embodiment', even in the operation for one column, at the processing of the signal level Ssig, Before the comparison processing for the voltage comparator 252 is completed, the slope change command signal CHNG is supplied to the reference signal generator 27 by -33-200845735 to change the slope of the reference signal vs 1 ο p to J times larger. At the same time, the count mode control signal UDC, the reset control signal CLR, the data hold control pulse HLDC, and the count clock control signal τη are supplied to the count execution unit 504 in the counter 254 such that each output to the count execution unit The frequency division operation of the bit in 5 04 is changed to the multiple of the previous operation speed (preferably Κ times = J times). If the slope of the reference signal V s 1 ο ρ is set to J times larger and the frequency division operation is changed to Κ times the speed, in practice, the period of the A/D conversion process is shortened to 1/J times and A/ The D conversion system is performed at a multiple of Κ/Κ of the A/D conversion gain. By setting Κ times, in practice, the period of A/D conversion processing can be shortened by 1 / J times and the A/D conversion gain can be kept constant, so that the linearity of the A/D conversion result is not damaged. If the L-weighted column of the addition processing operation of the first embodiment is combined with the above-described addition processing, it is possible to obtain the A/D conversion result /, 'Vsigl with respect to the pixel signals Vsig 1 and Vsig2 corresponding to the two columns. +K-Vsig2" without damaging the individual linearity, while reducing the cycle of A/D conversion processing by 1 / J times (=1/K times). The communication/timing controller 20 is based on the data from the external host controller. To determine the on/off timing for the slope change command signal CHNG, the count mode control signal UDC, the reset control signal CLR, the data hold control pulse HLDC, and the count clock control signal TH. The addition processing in the first embodiment In operation, these on/off timings are determined according to the weighting setting. In the additive processing operation of the second embodiment, these on/off timings are based on the relationship between photon shot noise and quantum noise -34-200845735 Depending on the purpose of higher accuracy or faster speed, when the comparator output is not dynamic, the gate 52 transmission does not change the input count clock CK0 as the count clock CIN, and the count is executed 5 04, but when Comparators When the output is inverted to the active state, the gate 502 transmits the count clock CK0. When the count clock CK0 is stopped, the count execution unit 504 stops the operation and maintains a count 値 to reflect the pixel signal voltage Vx at that time, that is, The counting execution unit 504 converts the pixel signal voltage Vx into the bit data and holds the digital data. [Counter] FIGS. 4 and 5 are diagrams showing an example of the structure of the counting unit 504 in the counter 254. Here, the display support 1 The 2-bit architecture. The counting unit 504 in each row corresponding to each vertical signal line 19 has substantially a non-synchronous counting architecture, wherein the cascade has a D-type and the counting output of the previous stage is input to The clock of the next stage is further characterized by the architecture of the present embodiment, wherein when the flip-flop itself inverts the output NQ back to a D input, each flip-flop can open one of the control inverted outputs NQ. Maintaining the on/off operation of the function. Between these levels, there is a function unit for switching between the number of counting modes and the number of the lowers, and a function unit for switching the count output of the previous stage clock. pulse From between the gate 502 of the count clock. Stopping unit stops the count variable number of electrically number

Execution of the line single positive and negative CK takes it extra, as described above in the root CIN-35-200845735, the counting execution unit 504 has the first flip-flops (FF) 510-00 to 510_11 (hereinafter collectively referred to as 510) . The count execution unit 5 04 has a data holding unit (hold) 512_00 to 512_11 (hereinafter collectively referred to as 512) capable of holding the data of the inverted output terminal N Q between the inverting output terminals NQ and D of the flip-flop 510. Each data holding unit 5 1 2 is controlled by other data holding control pulses HLDC (00 to 1 1). The data holding unit 512 has a function of maintaining the count output regardless of the input state of the flip-flop 510, for example, this can be implemented for mutual exclusion or gate. For example, when the material hold control pulse HLDC is operating H (H: high level), the data holding unit 512 holds the input data (inverted output NQ of the flip-flop 510), and when the data hold control pulse HLDC is inactive L (L) When the low level is on, the hold operation is released to transfer the input data (inverted output NQ of the flip-flop 510) to the D input of the flip-flop 510. The reset control signal CLR is input together to each reset terminal R of the flip-flop 510. When the reset control signal CLR is active, the flip-flop 510 sets, for example, a non-inverted output Q to an L level, and the inverted output terminal NQ is a Η level. Furthermore, the counting execution unit 504 includes counting mode switches (U/D) 514 — 00 to 514 — 11 (hereinafter collectively referred to as 514 ) for switching the counting mode to the upper or lower number between the stages of each of the flip-flops 5 1 0 . . In response to the counting mode handle number U D C, the counting mode switch 5 1 4 switches the mode of the data at the inverting output terminal NQ of the previous stage flip-flop 510 and outputs it after being invariant or inverted. For example, the count mode switch 5丨4 can be implemented as a mutex or gate. -36- 200845735 For example, the counting mode switch 5 1 4 switches the inverting output terminal NQ of the flip-flop 5 1 0 between inverting and non-inverting, so that when the counting mode control signal UDC is at a high level, the counting execution unit 5 0 4 operates the upper number operation, and when the signal UDC is low, the count execution unit 504 performs the next operation, and the count execution unit 504 includes the count clock switches (SEL) 516_00 to 516_10 (hereinafter collectively referred to as 516), at each A flip-flop 510 is interposed between the count mode switch 5 1 4 of the next stage. The count clock switch 5 16 switches the output pulse of the count mode switch 514 and the count clock CIN from the gate 502 in response to the count clock control signals ΤΗ_00 to TH_10 (hereinafter collectively referred to as TH), respectively, and supplies them to the flip-flop of the next stage. 5 10 0 clock terminal CK. Each count clock switch 5 16 is controlled by another count clock control signal TH. The count clock control signal TH at the previous stage becomes active, and the signal TH at the next stage is sequentially activated at a predetermined delay timing (details are described later). For example, when the count clock signal TH is not active, count. The clock switch 5 1 6 transfers the output of the count mode switch 5 1 4, and when the count clock control signal TH is switched to the operation ,, it transmits the count clock CIN from the gate 502. The count clock switch 5 1 6 takes the count clock CIN from the gate 5 02 in the following manner. In the first example shown in Fig. 4, the wiring is arranged such that the clock of the flip-flop 5 10 in the previous stage is held for each row. On the other hand, in the second example shown in Fig. 5, the count clock lines 517_00 - 37 - 200845735 to 5 17_1 1 (hereinafter collectively referred to as 517) are supplied and wired together to each row and at each flip-flop 510. The count clock C IN between the stages and from the gate 502 is taken out by the count clock line 51. In the example shown in Fig. 4, less wiring is required than the count clock C IN of the second example of Fig. 5. However, when the count clock CIN is sequentially transferred to the more efficient bit flip-flop 510, the lower-effect bit flip-flop 5 10 is still operating even if the data output therefrom is processed to be inactive. On the other hand, in the second example shown in Fig. 5, although much more is needed for the count clock C IN wiring as shown in Fig. 4, there is an advantage in that less power consumption is achieved. This is because the counting operation of the flip-flop 5 10 in the preceding stage can be stopped after the switching, for example, by setting the clock stop unit (stop) to the individual stages between the gate 502 and the count clock line 5 17 18 (_00 to _ 1 〇), in response to the count clock control signal TH, the supply of the count clock to the flip-flop 5 1 0 is stopped. Both the first and second embodiments can be used to allow the counting execution unit 504 to operate as a non-synchronized binary counter, and by allowing the counting clock switch 516 to operate in response to the counting clock control signal TH, counting execution f has a function of transmitting a clock input to the flip-flop 5 10 at the next stage (lower bit side) at each time the flip-flop 510 of each stage is transmitted. In other words, the higher-speed clocks for the lower-effect bit outputs are sequentially transferred to the next-stage side (the more efficient bit side) at a predetermined timing, so that the higher-efficiency bit output for the count clock CIN is divided. The frequency operation system is completed faster in sequence. For example, the 1/4 division operation of the count clock C IN before switching can be changed to the 1/2 frequency division operation of the count clock CIN after the switching -38- 200845735 After the count clock is switched, because of the counting operation (Divided operation) is performed by a faster clock than before, so the A/D conversion can be performed at a higher speed while maintaining the linearity of the A/D conversion by adjusting the slope of the reference signal Vslop. This will be described in more detail below. [Operation of Solid-State Image Pickup Apparatus: Basic Operation] Fig. 6 is a timing chart showing the signal acquisition differential principle, which is the basic operation of the line A/D circuit 25 of the solid-state image pickup device 1 shown in Fig. 1. The analog pixel signal detected for the unit pixel 3 of the pixel array unit 10 is converted into a digital signal in accordance with the following operation. For example, a search is performed to find a point at which the reference signal Vslop is lowered by a predetermined slope in a ramp waveform, and a point at which each voltage of the reference component or the signal component of the pixel signal from the unit pixel 3 matches. A count clock self-reference signal Vslop is used as a point of comparison processing to a point corresponding to the reference element or signal element matching the reference signal, counting the time period. As a result, the counts corresponding to each of the reference elements and the signal elements are obtained. In other words, the voltage comparator 252 disposed in each of the rows 25 compares the analog pixel signal voltage V X read out to the vertical signal line 19 with the reference signal Vslop. At this time, the counter 254 disposed in each row is activated similarly to the voltage comparator 252, and a certain potential of the reference signal Vslop is changed to a one-to-one correspondence with the counter 254, and the pixel signal voltage VX is converted. For digital data. In the present description, the change of the reference signal Vslop is to convert the change in voltage into a change in time. Count -39- 200845735 The 254 counts the time by quantifying a certain cycle (clock) to convert to digital data. If it is assumed that the reference signal Vslop is changed by ΔV in the time period Δt and the counter 2 5 4 is operated in the Δt cycle, the counter 値 becomes n when the reference signal Vslop is changed to ΝχΔν. The pixel signal s 〇 (pixel signal voltage Vx) output from the vertical signal line 19 causes the signal level Ssig appearing at the reset level Srst containing the pixel signal noise as a reference level in time series. If the first operation is performed on the reference level (reset level Srst, which is substantially equal to the reset level Vrst), then the second operation is performed on the summed signal component V sig and the reset level Srst The signal level is on Ssig. This operation is detailed below. In the first operation, that is, in the A/D conversion period Trst for resetting the level Srst, the communication/timing controller 20 first sets a reset control signal CLR to the operation Η, and resets each of the self-counters 254. The count 値 of the non-inverted output terminal Q output of the flip-flop 510 is "0", and the counter 254 is also set to the lower mode (tl). At this time, the communication/timing controller 20 sets the data hold control pulse HLDC to the operation Η, and the count mode control signal UDC to the low level (i.e., the lower number mode). At this time, the vertical selection signal Φ VSEL in the read target column Vn in the unit pixel 3 is set to the operation Η, and the pixel signal So is allowed to be output to the vertical signal line 119, and the signal is almost simultaneously reset. φ RS T is set to the operation Η and 38 is set to the reset potential (U to t2). The reset potential is output to the vertical signal line 1 9 as the pixel signal S 〇. Therefore, the reset level S r s t at which the vertical signal line 1 9 appears becomes the pixel signal voltage V X . At this time, the potential of the convergence reset signal Srst is changed due to the change of the in-pixel amplifier (pixel amplifier -40-200845735 amplifier 5) of each unit pixel 3. After the first readout operation of the pixel signal read out from the unit pixel 3 in the read target column Vn to the corresponding vertical signal line 19 (H0, H1, ...) is stabilized, that is, after the reset level Srst converges' The communication/timing controller 20 supplies control data CN4 for generating the reference signal Vs lop to the reference signal generator 27. Here, in order to cause the counting operation for the counter 2 54 to start changing simultaneously with the reference signal Vslop, the data of the hold control pulse HLDC is used as the control data CN4 and is set to be inactive L (t10). In response to this, when the reference signal Vslop is used as a comparison voltage to the input terminal RAMP of one of the voltage comparators 252, the reference signal generator 27 inputs a step-by-step or linear voltage waveform which changes with time as a sawtooth wave (slant wave shape) The whole starts with the starting voltage SLP_ini. The voltage comparator 252 compares the reference signal Vslop with the pixel signal voltage Vx of the vertical signal line 19 supplied from the pixel array unit 10. Simultaneously with the input signal RAM1 input to the input terminal RAMP of the voltage comparator 252, the comparison period in the voltage comparator 252 is such that the counter 254 disposed in each column is synchronized with the reference signal Vslop supplied from the reference signal generator 27. Measure. Actually, the data hold control pulse HLDC is set to be inactive L to generate the reference signal Vslop, and the hold operation of the data holding unit 512 is performed, and therefore, the counter 254 starts the self-starting number as the first counting operation. More specifically, the counting operation starts from the negative direction. The voltage comparator 2 5 2 compares the oblique-41 - 200845735 wave reference signal Vslop supplied from the reference signal generator 27 with the pixel signal voltage Vx input via the vertical signal line 19, and when the two voltages are equal, the voltage comparator 252 The comparator output is inverted from the Η level to the L level. In other words, the voltage comparator compares the voltage signal (reset level Srst) corresponding to the reset level Vrst with the reference signal Vslop, and generates a low-state active (L) pulse signal having a corresponding value in the time axis direction. The level of the level Vrst is reset and the generated pulse signal is supplied to the counter 254. As a result, the counter 254 is almost inverted with the output of the comparator while stopping the counting operation, and latches (holds/stores) the count of the time 値 as pixel data, thereby completing the A/D conversion. In other words, the pulse of the pulse signal having a quasi-low state active (L) obtained by the comparison operation of the voltage comparator 2 52 is counted by the count clock CK0, and a display corresponding to Reset the count 値 of the digit 値Drst (eg, the sign is -Drst) at the level of the Vrst level. After a predetermined number of cycles have elapsed, the communication/timing controller 20 sets the material hold control pulse HLDC to the actuation H (tl4). Therefore, the communication/timing controller 20 stops generating the ramp reference signal V s 1 〇 p (11 4) and returns to the start voltage SLP_ini. Since in the first operation, the voltage comparator 252 detects the reset level Vrst in the pixel signal voltage Vx and the counter 254 performs the counting operation, the reset level Vrst of the unit pixel 3 is read out to reset the bit. Quasi-vrst performs A/D conversion. The reset level Vrst contains offset noise, which is changed by the unit pixel 3. However, the change in the reset level Vrst is usually small, and the reset -42-200845735 level Vrst is approximately the same for all pixels. Therefore, the output 値 of the reset level Vrst of the pixel signal voltage Vx of the arbitrary vertical signal line 19 has been generally known. Therefore, in the first readout operation and the A/D conversion for resetting the level Vrst, the lower period (comparison period) can be shortened by adjusting the reference signal Vslop force D. For example, the comparison operation is performed by setting the maximum period for the comparison operation (ie, the A/D conversion period for resetting the element) to a 7-bit count period (128 clocks), and performing the reset level Srst (heavy) Set on the standard Vrst). In the next second operation, that is, in the A/D conversion period Tsig for the signal level Ssig, in addition to the reset level Vrst, the signal component in response to the amount of incident light of each unit pixel 3 is also read out. And perform an operation similar to the first read operation. More specifically, the communication/timing controller 20 first sets the count mode control signal UDC to the high level and the set counter 254 to the upper mode (tl6). At this time, in the unit pixel 3, when the vertical selection signal φ VSEL in the read target column Vn is held as the operation ,, a transfer signal φ TRG is set to the operation Η and the signal level Ssig is read out to The vertical signal line is perpendicular to the signal line 19 (tl8 to t19). After the second readout of the unit pixel 3 in the read target column V η is stabilized to the vertical signal line 19 (Η0, Η1, ...), the communication/timing controller 2 〇 supplies control data for generating the reference signal Vslop. CN4 is supplied to the reference signal generator 27. Meanwhile, in order to cause the reference signal Vslop to start changing simultaneously with the counting operation of the counter 254, the data holding control pulse HLDC uses -43-200845735 as the control data CN4, and is set to be inactive L (t20). In response to this, the reference signal generator 27 inputs a step-by-step or linear voltage waveform as a reference signal V s 1 ο p to the comparison voltage of the input terminal RAMP of the voltage comparator 252, which is a sawtooth wave in time. (Ramp) changes and starts with the starting voltage SLP_ini. The voltage comparator 2 52 compares the reference voltage Vslop with the pixel signal voltage Vx supplied from the pixel array unit 10 to the vertical signal line 19. Simultaneously with the reference signal Vslop input to the input terminal RAMP of the voltage comparator 252, the comparison period in the voltage comparator 252 is the amount of the reference signal Vslop supplied from the reference signal generator 27 in synchronization with the counter 25 in each column. Measurement. Actually, at this time, the material hold control pulse HLDC is set to be inactive L to generate the reference signal Vslop, which releases the holding operation of the material holding unit 51. Therefore, in the second counting operation, the counter 254 starts counting backwards with the first operation, and the digit 値Drst of the reset level Srst of the pixel signal voltage Vx obtained by the first reading (here, negative 値), And A/D conversion operations. In other words, the counting operation starts in the positive direction. The voltage comparator 25 2 compares the ramp reference signal Vslop supplied from the reference signal generator 27 with the pixel signal voltage Vx input via the vertical signal line 19, and when the two are equal, the voltage comparator 252 outputs the output of the comparator. The level is inverted to the L level (t22). In other words, the voltage comparator 2 52 compares the voltage signal (signal level Ssig of the pixel signal voltage Vx) corresponding to the reset level Vrst with the reference signal Vslop, and generates a low-state active (L) pulse signal, which is The time axis direction has a level corresponding to the signal component -44 - 200845735 V sig and supplies the generated pulse signal to the counter 2 5 4 . As a result, the counter 254 stops the counting operation almost simultaneously with the inversion of the comparator output, and latches (holds/stores) the count at that time as the pixel data, thereby completing the A/D conversion. In other words, the width of the low-level active (L) pulse signal obtained in the time axis for the comparison operation in the voltage comparator 252 is counted by the count clock CK0, and is obtained corresponding to the pixel signal voltage Vx. The count of the signal level Ssig is 値. In the unit pixel 3, after a predetermined number of cycles, the vertical selection signal Φ VSEL in the read target column Vn is set to be inactive L, and the pixel signal S 输出 output to the vertical signal line 19 is stopped, and is used. The vertical selection signal φ VS EL in the column below the read target column Vn+1 is set to the active level (t26). At this time, the communication/timing controller 2 is prepared to process the next read target column Vn+1. For example, the count mode control signal UD C is set to the low level and the counter 2 5 4 is the lower mode. In the second operation, since the counting operation is performed by detecting the signal level S sig of the pixel signal voltage VX by the voltage comparator 252, the signal component Vsig of the unit pixel 3 is read out to match the signal level. Ssig performs A/D conversion. Since the signal level Ssig is a level obtained by adding the signal component Vsig to the reset level Srst, the count 値 for the A/D conversion of the signal level ssig is basically "Drst + Dsig". However, since the upper number is started by "-Drst" which resets the A/D conversion result of the level Srst, a count 値 becomes "-〇^1 + (〇3丨8 + 〇1^) = 〇8丨吕,,. If the A/D conversion period Trst and -45-200845735 for resetting the level Srst are assumed to be used for each digit of the A/D conversion period Tsig of the signal level Ssig (conversion) The coefficient is α [V/digit], and the A/D conversion period meter Dsig is converted into voltage 値, and the voltage of the signal component Vsig is mutated. D sig 〇 For example, as shown in FIG. 6, it represents the pixel signal voltage. In the position 値 in the brackets of Vx, the reset level Srst of the pixel signal voltage Vx in the vertical signal line 19 is 10, the signal component is 60, and the letter Ssig is 70 for the digit 値. In the A/D conversion period Trst of the quasi-Srst, when the count Drst becomes -10, the reference signal Vslop and the pixel signal voltage Vx (intersection) and the comparator output of the voltage comparator 252 are inverted to the operation, so that the counter 254 is stopped. The next operation is performed. Therefore, the A/D conversion result of the reset level becomes the -pixel array unit 10, and the 値 is guaranteed until the signal is used. The A/D conversion period Tsig of the quasi-Ssig ends as the period for reading the next pixel signal. Furthermore, in the A/D conversion period Tsig of the signal level Ssig, the number level is read by the unit pixel 3. The counter 254 is caused to start up in the A/D conversion period Trst (point P in the figure), when the reference V slop becomes equal to the potential of the pixel signal voltage Vx, the count is changed, and when the reference signal Vslop and the pixel signal voltage When the signals Ssig of Vx are equal to each other, the comparator output from the voltage comparator 252 is inverted to the actuation L, whereby the counter 254 stops the upper operation. At this time, the actual number of the counter 25 4 is 70, However, the counter 2 5 4 starts from the negative 値-1 ,, so the actual counted electric number 値 becomes the α position P. Tfe· /^[-^ Number of digits 値 Match L bit Srst Hold, stop, , signal. The signal becomes a clamp, and 値 is -46-200845735 ”- 1 0 + 70 = 60”, so that it becomes the digit of the signal component Vsig 値D sig = 6 0 〇 In other words, in this embodiment, The counter 2 5 4 performs the first operation down number and performs the second operation upper number. Therefore, in the counter 254, the differential processing (subtraction processing) is automatically performed between the count 値 "-Drst" and the count 値 "Drst + Dsig", "-Drst" is the A/D conversion period, "D rst + D Sig, the A/D conversion period for the signal level Ssig, and the count 値Dsig corresponding to the result of the differential processing are held in the counter 254. The count corresponding to the difference processing result and held in the counter 254値Dsig corresponds to the signal component Vsig. As described above, by performing the comparison processing of the reset level Srst (actually equal to the reset component Vrst) and the signal level Ssig, and performing the sub-processing with the comparison processing The upper number processing maintains a count 値 corresponding to the subtraction result (count 値 in the second comparison period) - (count 値 in the first comparison period). At this time, the row A/D circuit 25 The offset component must be actually considered. Therefore, the equation (count 値 in the second comparison period) - the count of the shift in the first comparison period 値) = (reset level Srst + signal component Vsig + row) A/D circuit 25 offset Quantity) - (reset level Srst + offset component of row A/D circuit 25) = (signal component Vsig). By the above two read processing and automatic differential processing in counter 254, except for each unit In addition to the changed reset component V rst of the pixel 3, it is also possible to eliminate the offset component of each row of the A/D circuit 25. Therefore, it is possible to obtain A/ of the signal component Vsig corresponding to the amount of incident light of each unit pixel 3. D-conversion node 47-200845735. Therefore, the row A/D circuit 25 of the present embodiment is not only used as a unit for converting an analog pixel signal into a digital pixel signal, and is also a CDS processing functional unit. The A/D conversion is performed by reading out the signal component V sig corresponding to the input amount. Therefore, in order to judge the amount of light at the level, it is necessary to set the upper period (t20 to t24 period) to make it The reference signal supplied to the voltage comparator 252 can be significantly changed. Therefore, in the present embodiment, the comparison longest period of the signal level Ssig is set to, for example, a 12-bit count period (4096 hours _ comparison is performed) Signal level Ssig. In other words, the longest period of the comparison processing (for resetting the A/D conversion period) for the weight Srst (reset level Vrst/reference component) is set to be shorter than the longest period of the comparison processing for the letter Ssig (ie, the a/D period of the signal component). The longest period of the comparison processing of the reset level S rst is set to the longest period for the comparison processing of the signal level S sig , and is determined to be equal to the two of the comparison processing. The longest period, that is, the maximum 値 equalization of the A/D conversion period for the reset level for the signal level Ssig, the total length of the two A/D conversion periods is shortened. At this time, although the comparison bit between the first time and the second time is the same, the communication/timing controller 20 supplies the control data to the reference unit 27, and the reference signal generator 27 generates the reference Vs1 based on the control signal. ο p. Therefore, the slope of the reference signal V s 1 ο p, g 卩 when the reference signal digit is single, also the range of the number of shots Z is compared with V s 1 ο ρ operation I), and the position of the set quasi-component is defined as Short is not set to Srst and. Therefore, the rate of change does not produce the test signal V s 1 ο ρ -48- 200845735 The rate of change is the same for the first time and the second time. If the reference signal V s 1 ο p is generated under digital control, the slope of the reference signal V s 1 ο p is easily made the same between the first and second times. In this way, the accuracy of the A/D conversion can be made equal, and the result of the subtraction processing by the up and down counters can be correctly obtained. The row A/D circuit 25 of the present embodiment has a data storage unit 256 at the counter 254 of the next stage. Before the operation of the counter 254, the count result obtained by processing the previous column Hx-1 is transmitted to the data storage unit 2 according to the memory transfer command pulse CN 8 from the communication/timing controller 2, in other words, After the end of the A/D conversion period, the data in the counter 254 is stored in the data storage unit 256, and the row A/D circuit 25 starts the A/D conversion processing of the next column Vx+Ι. The data stored in the data storage unit 256 after the A/D conversion process is sequentially selected by the horizontal scanning circuit 12 and can be read by the output circuit 28. In the architecture in which the data storage unit 256 is not provided, since the pixel data is output to the outside of the line processor 22 only after the second read processing, that is, after the A/D conversion processing is completed, there is a limit to the read processing. . On the other hand, by arranging the data storage unit 25 6, before the read processing (A/D conversion processing), the count indicating the result of the last subtraction processing is transmitted to the data storage unit 256, and therefore, the readout There is no limit to processing. Furthermore, since the counting result held in the counter 254 can be transmitted to the data storage unit 2 5 6, the counting result of the counter 2 5 4, that is, the A/D conversion, and the reading result to the horizontal signal line are read. 1 8 reading -49- 200845735 Out operations can be controlled independently. Therefore, it is possible to perform a pipeline operation which performs A/D conversion processing and readout operation in parallel with signals read out to the outside. As described above, in the solid-state imaging device 1 of the present embodiment, the upper and lower numbers can be switched. At this time, the upper counter which can switch the counting mode itself is used to perform the counting process twice, and at the same time, the processing mode is switched. The structure in which the unit pixels 3 are arranged in columns and rows is constructed in a row parallel A/D circuit in which row A/D circuits 25 are arranged in each vertical row. Therefore, it is possible to directly obtain the result of the subtraction processing between the reference level (reset level Srst) and the signal level Ssig as a result of the second count processing for each vertical line. The memory device for storing the reset level Srst and the signal level Ssig is implemented as a latch function of the counter. Therefore, there is no need to use a separate dedicated memory outside the counter to store the AD conversion data. In addition, it is not necessary to prepare a special subtractor for counting the difference between the digital data corresponding to the signal level (reset level Sr st ) of the reference component and the digital data corresponding to the signal level of the signal component. Therefore, it is possible to directly obtain the result of the subtraction processing between the reference level (reset level Srst) and the signal level Ssig as a result of the first count processing for each vertical line. The memory device for storing the count result of the reset level Srst and the signal level Ssig is performed by the latch function of the counter. Therefore, it is not necessary to provide a dedicated memory for storing AD conversion data outside the counter. In addition, it is not necessary to prepare a special subtractor for calculating the digital data corresponding to the signal level (reset level Srst) of the component of the reference-50-200845735 and the digital data corresponding to the signal level of the signal component. difference. This architecture can be accomplished by combining individual upper and lower numbers. However, at this time, it is possible, for example, to require a function element to start after loading the count of a counter (in the above example, the down counter) into another counter (upper counter in the above example). Count operation 'or, minus each count 为 for digital count processing. For example, it is possible to perform the next operation in the A/D conversion period in order to reset the level Srst to maintain the A/D conversion result of the reset level Srst of the unit pixel 3, and for the signal level Ssig, at A The upper number operation is performed in the /D conversion period Tsig to obtain the A/D conversion result from the signal component Vsig of the reset level Srst. That is, actually, the A/D conversion function and the CDS processing of the signal component Vsig are simultaneously performed. Moreover, since the pixel data indicated by the count 保持 held in the counter 254 displays a positive signal voltage, it is not necessary to perform a complementary calculation for changing the negative signal voltage to the positive signal voltage, which is consistent with the current system height. . Furthermore, by providing the data storage unit 256 at a lower level of the counter 2 5 4, it is possible to perform the signal output operation by the data storage unit 256 via the horizontal signal line 18 and the output circuit 28 to the outside in parallel, and for The current column Hx read operation and the counter 2 5 count operation 'to complete more valid signal output. The count 値Dsig obtained by converting the signal component Vsig of the pixel signal voltage Vx into digital data is stored in the data storage unit 256, and then sequentially read out to the outside by the horizontal scanning circuit 12. In this manner, since the -51 - 200845735 signal charge generated by the charge generator 32 is processed as an analog electrical signal and is processed in parallel by each column to the digital data, and then converted to digital data, one can be completed. High-speed counting and high-speed processing. [A/D conversion + addition processing: basic operation] Fig. 7 is a timing chart for displaying the addition processing in the vertical direction in parallel with the A/D conversion processing operation. For simplicity of explanation, the offset of the row A/D circuit is ignored. Each of the timings and signals in Fig. 7 is represented by the sequence and signal shown in one of the rows of Fig. 6, regardless of whether or not processing is the target column. In the description, the timing and signal are treated to distinguish the reference symbol representation of the target column. The same is true for other similar timing diagrams. The addition processing in the vertical direction performed in parallel with the A/D conversion processing operation is performed in the high-speed frame mode by setting the exposure period of the unit pixel to 1 /2 time compared with the normal frame mode. The pixel information is read out by all the unit pixels 3 in the pixel array unit 10. Even after the A/D conversion processing is performed, for the unit pixel 3 in a certain column, the counter 256 can express the A/D conversion result for the signal level Ssig by the count of η-bits. In the present embodiment, by using the data retention characteristic of the counter 2 54, the processing for converting the A/D conversions of the unit pixels 3 in the plurality of columns is performed in the counter 254. Most of the columns that are subject to addition processing can be two or more columns, or any number of columns greater than three. The acceptable relationship between the majority of the columns is not just the adjacent columns but also the columns. For example, typically, if the pixel array unit; [〇 -52- 200845735 is used to capture a color image, the appropriate column is selected in order to match the color configuration of the color separation filter, ie, the same color element is added. For example, if configured for B a er, the addition process is performed in an odd column or an even column. The same is true for the addition processing in the horizontal direction. Most columns that are subject to additional processing can also be two or more columns, or any number of columns greater than three. The acceptable relationship between most columns is not just for adjacent rows but also for several rows. For example, typically, if pixel array unit 10 is used for color image capture, in order to match the color configuration of the color separation filter, i.e., the additive color components are summed, the appropriate line system is selected as the target. For example, if configured for Bayer, the addition process is performed on odd or even rows. The following description is based on the assumption that the addition processing is performed by the counter 254 between two columns of any column Iv and any column Jv (addition calculation in units of two columns), and the counter 254 is in the row A/D circuit 25 There is an up/down number function, and thereafter, the addition processing is performed by the digit arithmetic unit 29 between two lines of an arbitrary line Ih and an arbitrary line Jh (calculated by adding two rows of rows). In other words, the explanation assumes that the addition calculation is based on two columns and two rows having a predetermined relationship. Furthermore, it is assumed that the column ϊν is the addition target column and its A/D conversion system is executed first, and then the A/D conversion is performed on the column Jv. The basic operation description of the differential processing can be obtained from the signal. When the signal of the unit pixel 3 in the column Iv is read and the A/D conversion processing is performed, first, the vertical selection signal cpVSEL_Iv of the target column Iv is read. It is set to operate Η and allows the pixel signal S 〇 to be output to the vertical signal line 19. At this time, although not shown, all the data hold control pulses HLDC00 to HLDC1 1 are set to the actuation H (tl_Iv to tlO_Iv) -53 - 200845735, and are set to the inactive L' and count processing during the comparison processing ( From tiOJv to t14_Iv), all of the count clock control signals ΤΗ00 to TH11 are set to be inactive L (tl_Iv to t26_Iv). It is assumed that the reset element of the column Iv is Vrst_Iv and its reset level is Srst_Iv, and the signal component of the column Iv is Vsig_Iv and its signal level is Ssig_Iv. By performing comparison processing and counting processing (tl_Iv to t26_Iv) on them, the counter 254 holds the digit 値Dsig_Iv(t26_Iv) obtained by the equation, where (·the count in the second comparison period 値)-(in the The count in a comparison cycle 値) = "(Srst_IV + VSig__Iv) - Srst_Iv = Vsig_Iv". After the A/D conversion period of the column I v is completed, it is not necessary to reset the counter 2 5 4, and the signal read operation and the A/D conversion processing of the unit pixel 3 in the column Jv are sequentially performed, similarly for The read operation of the processing of the column Iv is repeated. Therefore, first, the vertical selection signal φ VSEL_Iv of the previous read target column Iv is set to be inactive L, and the vertical selection signal φ VSEL_Jv of the next read target column Jv is set to the operation Η, and the pixel signal So is allowed. It is output to the vertical signal line 19 (tl_Jv = t26_Iv). At this time, all the data hold control pulses HLDC00 to HLDC11 are initially set to the actuation H (t l_Jv to tl 0_Jv), and are set to the inactive L during the comparison processing and the counting processing (t10_Iv to t14_Iv), although not displayed. However, all the count clock control signals T Η 0 0 to Η Η 1 1 are set to be inactive L (tl_Jv to t26_Jv). Assume that the weight component in column Jv is Vrst_Jv, its reset level is Srst — Jv, and the signal component in column Jv is Vsig_Jv and its signal bit -54-200845735 is Ssig_Jv. By performing comparison processing and counting processing (tl-Iv to t26_Iv) on them, after the A/D conversion of the column Jv, the counter 254 holds the digits obtained by the equation, where: "Vsig_IV + (SrSt_Jv + VSig__jv)_ Srst_Jv = Vsig_Iv + Vsig_Jv''. In other words, the counts obtained by the two signal components Vsig_Iv and Vsig_Jv of the columns Iv and Jv in the vertical direction of the phase port are held in the counter 254 (t26_Jv). As shown in FIG. 7, one of the digits is indicated in the parentheses of the line graph of the pixel signal voltage Vx, which assumes that the reset level Srst_Iv in the column Iv and the Srst_Jv in the column Jv are 10, and the signal components Vsig_Iv and Vsig_Jv 60, and the signal levels Ssig_Iv and Ssig_Jv are 70. At this time, in the A/D conversion of the signal level Ssig_Iv (signal component Vsig_Iv) in the column Iv, by performing A/ of the self-resetting level Srst_Iv The D 转换Drst_Iv(= -10) obtained by the D conversion is used as the upper number of the starting point. After the processing, the count 値Dsig_Iv in the counter 254 becomes 10+70=60" °, and then the A/D conversion in the column Jv The count 値Dsig_Iv(= 60) obtained by the A/D conversion of the column Iv Used as a starting point, the number of lines to re-execute the first level Srst_JV, and be held in the counter 254 is in the Zhi Drst_Jv becomes "60-10 = 50." Furthermore, the upper number is executed on the signal level Ssig_Jv by using the count 値Drst_Jv (= 50) as a starting point, and the count 値 ADD which is held in the counter 25 4 after processing becomes "5 0 + 70 = 1 20”. This 値 indicates the result of adding the signal component Vsig_Iv in the column Iv to the signal component Vsig_Jv in the JV. In the former example, the digital addition processing is performed in the row A/D circuit 25 by switching the upper and lower numbers -55 to 200845735. At this time, if the counter can switch the counting mode by using itself, it is advantageous in that it is possible to automatically perform CDS processing for eliminating the reset component V r s t of the signal Vsig of the unit pixel 3 and the addition processing. This architecture can be implemented by combining individual up-counters and down-counters. However, in this case, a functional component may be required, for example, counting from one device counter (in this case, the lower-counter) to another counter ( In this example, the counting operation is started after the counting device, or each counting 相 is subtracted or added by the digital calculation processing. After the A/D conversion process, the counter 254 transmits the count 値 to the horizontal signal line 18 via the data storage unit 256. At this time, the addition result obtained by adding the signal components Vsig_Iv and Vsig_Jv of the two columns Iv and Jv in the vertical direction is sequentially supplied to the digital arithmetic unit 29. By repeating the operation similar to the above, it is possible to obtain an image in which the pixel information is reduced to 1 /2 in the vertical direction (in the vertical (row) direction of the sensing surface). As a result, the frame rate can be increased up to twice as high as the normal frame rate mode in which all pixel information is read. The digital arithmetic unit 29 adds the signal components Vsig_Iv and Vsig_Jv (hereinafter referred to as column addition data ADD) of the two columns Iv and Jv in the vertical direction supplied from the self processor 26 and the data Add_Ih in the row Ih and The column in the row jh adds the data ADD Jh, and finally obtains the digital data indicating the addition result of the two columns and the two rows. For example, it is assumed that the counter 254 performs addition processing for odd columns and adjacent one even columns, and the digital arithmetic unit 29 performs addition processing for odd rows and one adjacent even rows. At this time, the 'digital arithmetic unit 29 reads out the addition data of the even-numbered lines and the odd-numbered lines from the data storage unit 56-200845735 storage unit 2 5 6 and adds them, thereby performing the addition operation between the two lines. As a result, the digital arithmetic unit 29 obtains the digital data 'which represents the addition result obtained by adding the signal components Vsig_lvlh and Vsig_IvJh of the two lines and the signal components Vsig_JvIh and Vsig_JvJh of the two lines, the former two behaviors being in the horizontal direction The odd row in the odd row Ih and the adjacent even row Jh, the latter two are the odd row Ih in the horizontal direction and the even column Jv adjacent to the odd column Iv. In other words, the addition operation is performed on four pixels arranged in two adjacent columns and two rows. The pixel signal voltage Vx output from the unit pixel 3 via the vertical signal line 19 is converted into a digital volume by the row A/D circuit 25, and the digital unit is added to the majority of the unit pixels 3 in the vertical direction (row direction). (In the previous example, the unit pixels 3 are arranged in two columns). With the above operation, it is possible to obtain the following effects. For example, 'from the representation of the pixel information amount, this is the same as the subtraction read (jump read) 1 /2 of the pixel resource in the vertical direction. However, since the pixel information is added between two pixels in the vertical direction, the information amount of the pixel information piece is multiplied. Therefore, even if the exposure period for the unit pixel 3 is set to 1 /2 time to ensure that the frame rate is, for example, twice as high, the digit 値 is added between the two columns of unit pixels at the time of a/d conversion, and one pixel The amount of information in the information has been multiplied. Therefore, the sensitivity is not reduced compared to the normal frame rate mode. In other words, the shorter exposure time of the single-pixel 3 does not cause a reduction in the amount of information of one pixel information. Therefore, it is possible to achieve a higher frame rate without lowering the sensitivity. Furthermore, since the addition processing is performed by switching the mode between the upper and lower numbers by the row A/D circuit 25 provided with the built-in -57-200845735/down counter, it is possible to achieve higher The accuracy addition operation does not have to use an external memory device separate from the wafer' or use an additional circuit device as a row parallel AD C having pixel array cells 10 and 26 mounted in the same semiconductor region. In the above example, the addition of the pixels performed in the two columns is exemplified and explained, however, this is not limited to the processing of adding two columns, and may be used for a plurality of columns. At this time, if the number of added columns is Μ, the amount of image data can be compressed to 1/Μ. Furthermore, when the amount of image data is compressed to 1 / ,, the frame rate can be increased by a factor of two by changing the data output rate. Similar to the techniques disclosed in the above patent documents, various modifications can be made in paragraphs 68 to 71 and 87. Detailed descriptions thereof can be omitted here. [Disadvantages of Digital Addition Processing] Figs. 8A to 8D are diagrams for showing the disadvantages of the digital addition processing of the counter 254 in the vertical direction and the digital addition processing of the digital arithmetic unit 29 in the horizontal direction. The figure shows the pixel configuration performed in the addition operation in the vertical direction and the horizontal direction. If the digital addition processing is performed as above, the spatial center of the pixel in the added image is the intermediate position of the addition target pixel. This relationship is sequentially accumulated, and the pixel position in the added image is determined if the column order or the row order of the added target pixel is sequentially, for example, 1 -58-200845735, 2,3,4 '... There is no problem, but if, for example, a column order or a row order is not sequential, for example 1, unit pixels 3, 2, 4, ... are problematic. In fact, when capturing a monochrome image, there is no problem in most cases because the usual addition processing does not have to change the order in which the target pixels are added. However, when "adding a wafer type image pickup device" is used to add the addition target pixels having the same color, a problem may occur because the order of adding the target pixels must be determined in accordance with the color configuration of the color separation filter. For example, it was decided to use a Ba er configuration filter as a color separation filter having R, G, and B color filters as shown in FIG. 8A (Gr is G in column R, and Gb is in column B). G). When the addition processing is performed on two columns and two rows, the vertical selection signal φ VSEL is in the first column, the third column, the second column, the fourth column, the fifth column, the seventh column, the sixth column, and the eighth column. The order of ... is specified by the bottom of each column. Therefore, as shown in the schematic diagram (Fig. 8B), the pixels arranged in the order read by the line processor 26, the two columns having the same color, i.e., the odd-numbered columns and the even-numbered columns are supplied to the line processor 26. When the same color is input in the vertical direction, each of the line A/D circuits 25 disposed in the vertical line in the line processor 26 performs an addition process. For example, the row A/D circuit 25 sequentially performs an addition process on each pixel signal having an R component and a Gr component in the first column and the third column; and having the second column and the fourth column in the second column and the fourth column Each pixel signal of the G b component and the B component; each pixel signal of the R component and the Gr component in the fifth column and the seventh column; and each of the Gb component and the B component in the sixth column and the eighth column One pixel signal. In other words, when two equal color sub-pixels of -59 - 200845735 are input to the row A/D circuit 25 in the vertical direction, the row A/D circuit 25 performs an addition operation on the same color component. The schematic diagram after % addition processing is shown in Figure 8C. The center column of the two-addition target column, that is, the center in the vertical direction at the time of addition becomes the center of the added pixel. For example, each center position is: a second column after adding the first column and the third column; and a third column after the second column and the fourth column are added; in the fifth column and the seventh column The sixth column after the addition; and the seventh column after the sixth column and the eighth column are added. Once this image is targeted, the digit arithmetic unit 29 sequentially takes the column addition data ADD, and when the same color is input in the horizontal direction, performs an addition operation. For example, the digital arithmetic unit 29 sequentially performs an addition operation on each of the pixel signals having the R component and the Gb component in the first row and the third row, and the Gr component in the second row and the fourth row. Each pixel signal of the B component; each pixel signal having an R component and a Gb component in the fifth row and the seventh row; and each of the Gr component and the B component in the sixth row and the eighth row Pixel signal. In other words, when two pixels having the same color component in the horizontal direction are input to the digital arithmetic unit 29, the digital arithmetic unit 29 performs an addition operation on the same color component. In the schematic diagram after the addition processing, there is a center line in which the two phases are added to the phase line in the horizontal direction, that is, the center in the horizontal direction at the time of addition becomes the center of the pixel after the addition. For example, each center position is: a second row after the first row and the third row are added; a third column after the second row and the fourth row are added; after the fifth row and the seventh row are added The sixth line; and the seventh line after the sixth line -60-200845735 and the eighth line are added. If the center pixel system combination shown in FIG. 8C with respect to the vertical direction is as described above, as shown on the right side of FIG. 8D, the center of the 2x2 cells formed by each color becomes the added color. Spatial location. For example, according to the operation code n (n is 〇 or a positive integer), four columns and four rows are assumed to be a combination, and the center of the pixel R is a "2 + 4n" column and a "2 + 4n" row, and the center of the pixel Gr For the "2 + 4n" column and the "3+4n" row, the center of the pixel Gb is the "3+4n" column and the "2 + 4n" row, and the center of the pixel B is the "3 + 4n" column and "3+" 4n" line. At this time, it can be understood from the original position of the pixel shown on the left side of FIG. 8D that the spatial positions of each color are arranged equidistantly before the addition, after the addition, each color is The spatial position is grouped in groups of four columns and four rows, and the other groups of four columns and four rows are also considered, and the pixels are not arranged in equal distance. This causes a problem in image resolution after addition. It is clear that it is difficult to obtain a high-resolution additive image. [Method for improving the resolution of the added image: First Embodiment] FIGS. 9 to 11 are diagrams for showing the first embodiment, which is a method for solving the digital addition processing of the counter 254 in the vertical direction. And the problem that the resolution is lowered in the digital addition processing in the horizontal direction by the digital arithmetic unit 29. Figs. 9 and 1 are timing charts showing the weighted addition processing for paralleling the vertical direction of the A/D conversion processing in the resolution improvement method of the first embodiment. For the sake of simplicity, the offset component of the row A/D circuit is omitted. Fig. 11 is a view showing the action of the count clock switch 516 operated in the improved method of the resolution -61 - 200845735 of the first embodiment. An example shown in Fig. 9 and the pixel array unit 1 is for two addition processing, and the weighting ratio between the two phases is set to 1 to double weighted addition). The first example shown in Fig. 9 is when the ratio is the double-weighted addition, wherein in the two-addition target column, the weighting of the first column Iv at the A/D turn is set to 1, and at A The weight of the /D conversion to the new column Jv is set to 2. On the other hand, as shown in the second example of the figure, the double-weighted addition of the ratio of 2 to 1 is added, wherein in the target column, at the time of A/D conversion, the weight of the first column Iv is 2, and at A/ In the D conversion, the weight of the next column Jv is set to 1 in the addition processing in the vertical direction, if the weighting is counted to 2, that is, if the A/D conversion gain is multiplied, then any method can be used. The first method is to reduce the reference signal Vslop (in this case, the slope is multiplied by 1/2); the second method is to increase the counter driving speed (in this case, twice the speed); and the third method is to test the signal Vslop The slope adjustment and the frequency division speed adjustment of the counter are likely to arbitrarily change the slope in the first method for reducing the slope of the reference signal V s 1 ο p , but the A/D conversion period becomes longer. That is, since the switchable voltage width (i.e., dynamic range) becomes narrower in the predetermined A/D conversion period, there are several disadvantages if the A/D conversion is operated at a high speed or a wide dynamic range. Unlike the first method, the second method increases the frequency division weight of the counter and can be set without affecting the A/D conversion period or dynamic range. However, if it is supplied to the counter 2 2 4 when counting the pixel 2 (referred to as 1 to 2 conversion processing, 两 ,, the two phases are set to the 2 2 2 4 to use the frequency combination of the slopes, Although the length of the reason requires speed, and the clock CK0-62-200845735 itself changes, the clock frequency can be arbitrarily changed. However, since it is taken in this embodiment, the weight 値 is set to a power of 2, if It is a mechanism for changing the frequency dividing speed of the counter 2 5 4 of the bit unit without changing the clock frequency of the counting clock CK0. On the other hand, the slope of the combined reference signal Vslop in the third method is adjusted to the frequency of the counter. In the adjustment, the individual advantages of the adjustment are combined. Even if the frequency division mechanism of the counter 254 of the one-element unit is changed, without changing the clock frequency of the count clock CK0, it is possible to set an arbitrary weight 値 without A /D conversion period or dynamic range is affected. [Weighted addition in the vertical direction] As shown in Figure 9, when the signal of the first column IV of the two added target columns is read out and The A/D conversion process is performed. First, the vertical selection signal φ VSEL_Iv of the read target column Iv is set to be active, and the output of the pixel signal S 允许 is allowed to be output to the vertical signal line 19. At this time, all the data The hold control pulses HLDC00 to HLDC1 1 are set to the active H (tl_Iv to t10_Iv) and set to the inactive L when the comparison process and the count process (t10_Iv to t14_Iv) are performed, and all the count clock control signals ΤΗ0 0 to TH1 1 is set to be inactive L (tl_Iv to t26_Iv). Therefore, by the comparison processing and counting processing (tl_Iv to t26_Iv), the counter 254 holds the digit 値Dsig_Iv (t26_Iv) of Vsig_Iv. This is the same as the processing shown in Fig. 7. Furthermore, in order to read the signal of one column Jv under the two-addition target column to perform the A/D conversion process, the vertical selection signal of the read target column Jv-63-200845735 φ VS EL is set to be activated and allowed. The pixel signal So is output to the vertical signal line 19. At this time, it is not necessary to reset the counter 254, and the read operation and the A/D conversion processing of the unit pixel 3 in the column JV are sequentially performed (tl_Jv = t26_Iv). This is related to Figure 7 On the other hand, the features of this embodiment are as follows: When the next column Jv (tl_Jv to t26_Jv) is read, although the processing of the first column Iv is used to change the slope of the reference signal Vslop (tl_Iv to t26_Iv), the data The data hold control pulse HLDC00 of the holding unit 5 12_0 0 is set to the operation Η for the entire period (tl_Jv to t26_Jv). Meanwhile, the data holding control pulses HLDC01 to HLDC10 to the remaining data holding unit data holding unit 512_01 to the data holding unit 512_pixel array unit 10 are set to the actuation H (tl__Jv to t10_jv) at the beginning and are subjected to comparison processing and counting processing. Set to no action L (tlO_Jv to t14_Jv). Further, the count clock control signal ΤΗ00 is set to the operation Η, and all other count clock control signals ΤΗ01 to ΤΗ11 are set to the inactive L (tljv to t26 - Iv). In this way, the data retention control pulse HLD C00 first becomes active, and the data recorded in the least significant bit flip-flop 5 1 0_〇 0 is held. When the next column Jv. When processed (tl_Jv to t26__Jv), the least significant bit output becomes substantially inactive. Therefore, the processing for the next column J v becomes a low resolution processing. When the next column Jv is processed (tl_JV to t26_Jv), if the is control fg 5 tiger TH 0 0 becomes active when counting, the input clock of the least significant bit (〇 bit) flip-flop 5 10 00 is Transfer to the second-stage (1-bit) flip-flop -64 - 200845735 5 10_01 clock side. By transmitting the least significant bit clock to the next bit, the frequency division operation speed of the other higher efficiency bit outputs is doubled except for the least significant bit, and the counter 254 counts twice as fast as at the same time, The quantization step is performed coarser. For example, Fig. 11 shows that when the clock control signal ΤΗ00 is counted, the output of the flip-flop 510 from each bit, the slope of the reference signal Vslop (and the gain according to the slope) and the frequency dividing speed change. When the count clock control signal ΤΗ00 is switched to the operation Η, the count clock CIN supplied to the least significant bit flip-flop 510_00 is transmitted to the second-stage flip-flop 510_01, so that after switching, the more efficient bit is positive and negative. The device can operate faster than before switching. However, since the previous inefficient bit output becomes inactive, the quantization can be performed coarser than before. For example, if the count of the count output D00 of the first-order flip-flop 510_00 is 100 MHz before the count of the count clock control signal ΤΗ00, the loop of the count output D01 of the second-stage flip-flop 510_01 is 50 MHz. Meanwhile, when the count clock control signal ThOO is switched to the clamp level, the cycle of the count output D01 of the second-stage flip-flop 510_01 is 100 MHz, so that the frequency division operation in the more efficient bit-reactor 5 1 0 is Operates at twice the speed.

At this time, the slope of the reference signal Vslop is the same as the processing in the first column Iv (tl_Iv to t26_Iv) and the processing of the next column Jv to t26_Jv). Therefore, in the first column Iv processing, the relationship between the count 値 and the voltage 为 is ΔV/Δt, and the total gain of the A/D conversion process becomes, on the other hand, the voltage at the processing of the next column Jv値The total gain of 2 ΔV/Δ t and A/D -65- 200845735 conversion processing becomes 2. More specifically, in the present embodiment, when the next column 1 v is processed (tl_jv to t26_JV), the frequency dividing speed of the counter becomes k times the speed (twice in the previous example) ' without having to change the first column 1v The processed reference signal Vslop slope. Therefore, when compared with the A/D conversion processing of the signal component Vsigjv of the first column Iv, a double gain is applied to the A/D conversion processing of the signal component Vsig_Jv of the next column Jv. Therefore, assume that the voltage 値 (conversion coefficient) of each digit in the A/D conversion of the first column 1v is ^[v/bit] and the degree of increase in the speed in the counter 254 (corresponding to the counter 254) The gain is Lv, and the voltage 値 (conversion coefficient) of each digit in the A/D conversion of the next column Jv becomes Lvx α. In the previous example, Lv = 2 and the voltage 値 is 2α. Therefore, after the completion of the A/D conversion of the column Jv, that is, after the final count 加权 of the weighted digit addition processing is completed, the digit 値 held in the counter 2 5 4 becomes "a xVsig - Iv + 2a xVsig_Jv". For example, assuming that the digits in parentheses on the line graph of the pixel signal V x of FIG. 9 are, the signal components V sig _ I v and Vsig_Jv in the column I v and the column J v are 60, and the reset level Srst_Iv And Srst__Iv is 10. At this time, in the A/D conversion of the signal level Ssig_Iv (signal component Vsig_Iv) in the column Iv, by performing the 値"〇"11〃" obtained by the eight/〇 conversion of the heavy level Srst_Iv ( = -10) As the starting point up, after processing, the count 値 "-l 〇 + 70 = 60 = Dsig_Iv" is held in the counter 254. Subsequently, in the A/D conversion of the column Jv, by the column Iv The a/d switch-66-200845735 The obtained count 値 "60 = Dsig_Iv" is used as the starting point, and the number of reset levels Srst - Jv is first counted, and remains in the counter 254. "Dsig_Iv-2· Drst_Jv = 50-2xl0 = 40". Further, the upper level is performed on the signal level Ssig_Jv, starting from the count 値40 using the start point, and after the processing, the count stored in the counter 254 is 値It becomes "40 + 2x7 0 = 1 8 0". The count 値 means 値 "Dsig - Iv + 2 · Dsig - Jv", which is obtained by double the number 値Dsig_Jv in the column Jv and the number in the column Iv 値Dsig_Iv is added and obtained. In the first example not shown in Fig. 9, the addition of 2"Dsig_Iv + Lv·Dsig_IV" is borrowed. The frequency division operation of the speed of processing Lv (= 2) by the following column Jv is obtained. However, as in the second example of the pixel array unit 10, when the first column Iv is processed, if the counter is divided The operation is performed by multiplying Lv (= 2) by twice the processing of the next column Jv, and "Lv • Dsig_Iv + DSig_Iv" can be obtained as the addition result. In the previous example, only the higher order of the counter The frequency division operation on the bit side is changed to L times, and the speed and data on the lower order bit side are regarded as invalid to keep the frequency of the start count clock CIN at the same speed, and to avoid increasing the power consumption in the counter. This is not necessary. If the increase in power consumption in the counter is acceptable, the switching operation can be performed differently by the counting clock switch 5, and the starting counting clock CIN itself can also be used as the clock converter 2 The high-speed clock generated by the multiplication function of 3 is changed to a high frequency so that the counting execution unit 504 can perform the frequency dividing operation at a high speed. In this mode, since all the bit data can be used as The data is valid, so the A/D conversion accuracy is not lowered and the addition processing in the vertical direction of -67-200845735 can be implemented in the row A/D circuit 25. Further, in order to control the flip-flop 510 to execute at high speed Counting operation (frequency division operation), the circuit is structured to control the frequency division of the remaining portion of the higher order bit output when the weighting relationship of the bit of the flip flop is unchanged and the lower order bit output is invalid. The operation is performed at high speed. However, this is only an example, and any architecture is possible as long as it can increase the speed of the frequency division operation of the flip-flop 5 10 , and various modifications are possible. For example, a switching mechanism may be provided for sequentially shifting the one-element output to the low-order side of the flip-flop 5 10 , while omitting the change of the flip-flop 5 10 that is supplied to each stage. A count clock switch 516 that counts the supply mode of the clock. At this time, the data output from the flip-flop 510 of the next stage can be regarded as invalid. This is also like the A/D conversion data, which becomes invalid for lower order bit data. However, at this time, there is a need for a circuit for loading the count of each bit to the previous stage side at the time of switching. Therefore, a circuit configuration will be more complicated than the previous example in which the count clock switch 5 16 is used to switch the count clock. However, at the time, since, for example, the supply of the count clock of the flip-flop 5 10 in the next stage is stopped after the switching operation, the counting operation can be stopped, so that the advantage of consuming lower power can be completed. Furthermore, although the application example illustrates the use of a non-synchronous counter as the counter 2 54, the same idea can be applied to the use of a synchronous counter. For example, if a sync counter is used, each flip-flop 510 is operated by using a common count clock, and each flip-flop 5 10 requires a gate circuit that allows each flip-flop 5 1 0 to It is inverted when 较低 of the lower order bits is 丨 (in the upper number) or when 値 of all lower order bits is 0 (in the lower number). -68- 200845735 In this configuration, in order to increase the speed of the frequency division operation of the flip-flop 5 10 , a switching circuit can be provided to cause the gate circuit to be output on the lower order bit side. However, this circuit configuration is more complicated than the use of the count clock switch 5 1 6 to switch the count clock with a non-synchronous counter. Alternatively, as described in the modification using the asynchronous counter, it is also possible to configure the circuit to be provided to load the count of each bit to the lower order side at the time of switching, and the switching mechanism is provided for Move one bit output to the lower order side. [Double Weighted Addition and Final Addition Image in Horizontal Direction] Figs. 12 to 14 show pixel configurations at the time of the addition operation in the horizontal direction and the vertical direction in the resolution improvement method of the first embodiment. Similar to FIGS. 8A to 8D, as an addition process for two columns and two rows, it is shown that when there are R, G, B (G is represented as Gr in column R, and Gb is represented in column ,, The Bayer configuration filter of the color filters that are distinguished from each other is used as a dichroic filter. Figures 12A through 12F show the pixels in the same column and row order as shown in Figure 8A, and the double-weighted addition system shown in Figure 9 is applied to these pixels. 13A to 13F show the same column and row order shown in Fig. 8A, and the combination of the double weighted addition shown in Fig. 9 and the double weighted addition shown in the pixel array unit 10 is applied to these pixels. . Fig. 1 4A to 1 4F show that the order of taking pixels is different from the order in Fig. 8A and the double weight addition addition shown in Fig. 9 is applied to these pixels. Regarding the double-weighted addition processing in the horizontal direction, in the vertical side -69-200845735, the pixel system to which the Lv-weighted weight is added is transmitted to the digital arithmetic unit 2 9, and the 'digital arithmetic unit 2 9 performs Addition processing in the horizontal direction. The addition processing is performed with the processing shown in Figs. 8A to 8D. In the present embodiment, Lh-fold weighted addition is performed similarly to the L v-fold (= 2) weighted addition processing. Specifically, the addition data ADD_Jh of the next line Jh is obtained by adding the Lh multiple weight to the addition data ADD_Ih of the first line Ih. Typically, it is set to Lh = Lv. According to the former example, for example, it is set to double weighting. [Double Weighted Addition Example of Ratios 1 to 2] When the pixel is subjected to the same column and row order as shown in FIG. 8A and the double weighted addition shown in FIG. 9 is applied to the pixels, first, As shown in Fig. 1 2 A (same as Fig. 8A), the vertical selection signal φ VSEL is in the first column, the third column, the second column, the fourth column, the fifth column, the seventh column, the sixth column, and the eighth column. The order of the columns is specified by the bottom of the number of columns. As shown in the figure (Fig. 12B), in which the pixels are arranged in the order in which they are read by the line processor 26, when two columns having the same color are input to the odd or even columns in the vertical direction, the line processor Each row A/D circuit 25 in each of the vertical rows 26 performs an addition process. At this time, it can be understood from the description of FIG. 9 that the frequency dividing operation for the counter of the next column Jv is twice as fast as the processing for the first column Iv, and the addition processing is set first. The weights of the columns Iv (first column, second column, fifth column, and sixth column) are 1, and weighting for the next column Jv (third column, fourth column, seventh column, and eighth column) 2, as shown on the right side of the figure, x -70- 200845735 2" indicates execution. For example, 'addition processing is executed sequentially: double R component in the first column in the third column and in the first column The Gb component in the second column and the B component in the double Gb in the fourth column and the double b component in the fourth column; the component and the double R component in the seventh column and in the fifth column Double Gr component in the seventh column; double Gb component in the 28th column in the sixth column and double B component in B in the sixth column, ', and so on. In other words The same color component of the two pixels is input to the row, and the row A/D circuit 25 performs the addition operation of the same color component by making the division of the next column JV twice. As shown in Fig. 1 2, the pixel center system is shifted to a larger weight, and is not in the center column of the two added target columns, that is, at the center of gravity of the phase. Specifically, it is not vertical when added. The position obtained by the distance between the first column Iv and the next column JV is changed to the center after the addition, and the center is heavily weighted by the next column Jv side 1/3 歹!J (refer to FIG. 12E), for example, each center Position: After the double-weighted addition of the first column, the displacement to the third column leaves the second: ; For the second and fourth columns, the third column is separated from the third column by the third column and the fourth column Position; for the first, after double-weighted addition, shift to the R component of the seventh column side, the :Gr component; in the first component and in the second column in the fifth column, R 丨The Gr component and the 1 Gb component are in the first component and in the eighth column. When in the vertical A/D circuit 25, I is the first column Iv. On the added column Jv side, and the time-added The center of gravity in the vertical direction, by: 2: 1 The internal division is shifted to the third and seventh columns, and is added to the fifth and seventh columns after the column 1/3 column is added, and the sixth column is 1/3 column - 71 - 200845735; and for the sixth and eighth columns, after the double-weighted addition, shift to the position of the eighth column side leaving the seventh column 1/3 column. The digital arithmetic unit 29 sequentially acquires the column addition data ADD, and performs an addition operation on the image in the above state when the same color is input to the horizontal direction. For example, the digital arithmetic unit 29 sequentially performs the addition operation on the R component in the first row, the double R component in the third row, and the Gr component in the first row and the double in the third row. a multiple of the Gr component; the Gb component in the second row and the double Gb component in the fourth row and the B component in the second row and the doubled B component in the fourth row; the R component in the fifth row And the double R component in the seventh row and the Gr component in the fifth row and the double Gi: component in the seventh row; the Gb component in the sixth row and the double Gb component in the eighth row And the B component in the sixth row and the double B component in the eighth row, and so on. In other words, when the addition data of the same color component of two lines in the horizontal direction is sent to the digital arithmetic unit 29, the digital arithmetic unit 29 makes the component of the next line J v into the first line I v by two Times, and the addition processing of the same color is performed. In the schematic diagram after the addition operation, the center of the pixel after the addition is shifted to the side of the next line Jh to which the larger weight is applied, instead of the center line of the two addition target lines, that is, the level at the time of addition. The center of gravity of the direction. Specifically, it is not the center of gravity in the horizontal direction at the time of addition, by changing the position obtained by dividing the spatial distance between the first line Ih and the next line Jh by 2:1 into the center after the addition, the center It is shifted to the next line Jv side 1/3 line to which a larger weight is applied (refer to FIG. 12F). -72- 200845735 For example, each center position is: for the first row and the third row 'after the double weighted addition, the displacement to the third row leaves the second row 1/3 row; for the second row and The fourth line, after the double weighted addition, shifts to the position where the fourth line side leaves the third line 1/3 line; for the fifth line and the seventh line', after the double weighted addition, shift To the seventh line side, leave the position of the 1/3 line of the sixth line; and for the sixth line and the eighth line, after the double weighted addition, 'shift to the eighth line side and leave the seventh line 1/3 line s position. If the centers shown in Fig. 1 2 C are combined in the vertical direction after the addition, the spatial distance between the first column Iv and the next column Jv is divided by 2:1 at the center after the addition. And the spatial distance between the first row Ih and the next row Jh is divided by a ratio of 2:1, as shown in Fig. 1 2D. At this time, it is possible to compare the original positions of the pixels on the left side of Fig. 12D, although it is different from the state shown on the right side of Fig. 8D, the spatial positions of each color are not arranged equidistantly. [Combined double-weighted addition example in the ratio of 1:2 and 2:1] When the pixels in the same column are used and the row order and the double-weighted addition shown in Fig. 8A are combined by the operation of Fig. 9 When applied to the pixel with the operation of Fig. 10, the double-weighted addition of the ratio 1: 2 (the mode of Fig. 9) and the double weighted addition of the ratio of 2: 1 (the mode of Fig. 1) Repeated alternately. This completes the weighted addition based on the shift direction. For example, as shown in Fig. 13A (same as Fig. 12A), the vertical selection signal φ VSEL is in the first column, the third column, the second column, the fourth column, the fifth column, and the seventh column of -73-200845735 The order of the sixth and eighth columns is specified by the bottom column. As shown in the figure (Fig. 13B), when the same color column of the odd column or the even column is input to the vertical direction, the pixel system is rearranged into the order in which the row processor 26 reads out. The row A/D circuit 25 in each of the vertical rows of the row processor 26 performs an addition operation. At this time, the double-weighted addition by the ratio of 1:2 shown in Fig. 9 is performed by the first addition processing and the ratio of 2:1 and double-weighted addition shown in Fig. 1 It is executed for the next addition process. In this way, the 'g decimator 2 5 4 performs a frequency division operation on the first column Iv twice as fast as the frequency division operation of the next column J v faster than the first addition processing, and the addition processing is performed by A column Iv (first column and fifth column) is weighted to 2 to be "x2" shown on the right side of the figure, and weighted to one in the next column JV (third column and seventh column). In the next addition processing, the counter 2 5 4 performs the frequency division operation of the next column Jv twice as fast as the processing of the first column Iv, and the addition processing is performed by the first column I v (the second column and the The weighting of the six columns is set to 1, and the weight of the next column Jv (fourth and eighth columns) is 2, as indicated by the "x2" on the right side of the figure. The addition processing of the first column, the fourth column, the fifth column, and the eighth column is performed by doubling the weighting. For example, the addition process is performed sequentially on the double R component in the first column, the R component in the third column, and the double Gr component in the first column and the Gr component in the third column. ; the Gb component in the second column and the double Gb component in the fourth column and the B component in the second column and the double B component in the fourth column; the double R component in the fifth column And the R component in the seventh column and the double Gr component in the fifth column and the Gr component in the seventh column -74-200845735; the Gb component in the sixth column and the double in the eighth column The Gb component and the B component in the sixth column and the double B component in the eighth column, and so on. In other words, when the same color component of two pixels in the vertical direction is input to the row A/D circuit 25, the row A/D circuit 25 makes the component of the first column Iv by the first addition operation. The addition operation of the same color component is performed twice for the next column Jv, and the same color component is performed by making the next column Jv component twice the component of the first column Iv in the next addition operation Add operations and repeat these operations. The schematic diagram after the addition operation is shown in Fig. 13C. The pixel center after the addition is shifted to the next column Jv side applied by the larger weight, instead of the center column of the two added target columns, i.e., the center of gravity in the vertical direction at the time of addition. Specifically, instead of the center of gravity in the vertical direction at the time of addition, the position obtained by dividing the spatial distance between the first column Iv and the next column JV by 2:1 becomes the center after the addition, the center is Shift to the next column Jv side 1/3 column to which a larger weight is applied (refer to FIG. 13E). This is the same as Figure 12C. However, since the shift directions are alternately different at this time, the center of the added pixels is also different from that of Fig. 12C. For example, 'each center position is: for the first column and the third column, after the double weighted addition, the displacement to the first column leaves the 1/3 column of the second column; for the second column and the fourth column, After the double-weighted addition, shift to the position of the third column side leaving the third column 1/3 column; for the fifth column and the seventh column, after the double-weighted addition, shift to the fifth The column side leaves the position of the 1/3 column of the sixth column; and for the sixth column and the eighth column, after the double weighted addition, -75-200845735 shifts to the eighth column side and leaves the seventh column 1/3 The position of the column. The digital arithmetic unit 29 sequentially acquires the column addition data ADD, and performs an addition operation on the image in the above state when the same color is input to the horizontal direction. At this time, as in the processing in the vertical direction, the double-weighted addition in a ratio of 2:1 and the double-weighted addition in a ratio of 1:2 are alternately performed. More specifically, the first addition processing is performed by setting the weight of the first row Ih (the first row and the fifth row) to 2, as shown in the lower part of the figure "x2", and the next row Jh (the third row and the The weight of the seven lines) is 1 and executed. The next column of addition processing is set to the lower side of the figure by setting the weight of the first row Ih (the second row and the sixth row) to 1 and the next column Jh (the fourth row and the eighth row) to be 2 X2” means to be executed. The addition processing of the first line, the fourth line, the fifth line, and the eighth line is performed by doubling the weight. For example, the digital arithmetic unit 29 sequentially performs the addition operation in the double R component in the first row, the R component in the third row, and the double Gr component in the first row and in the third row. The Gr component, the Gb component in the second row and the double Gb component in the fourth row and the B branch in the second row and the double B component in the fourth row; in the fifth row Double R component and the R component in the seventh row and the double Gr component in the fifth row and the Gr component in the seventh row; the Gb component in the sixth row and the double Gb in the eighth row The component and the B component in the sixth row and the double B component in the eighth row. . And so on. In other words, when the same color split of two pixels in the horizontal direction is sent to the digital arithmetic unit 29, in the first addition operation, the digit counts -76-200845735 by the first unit The component of Ih is the addition processing of the same color for the next line Jv, and the arithmetic unit 29 performs the addition processing of the same color by making the component of the second column JV the first column Iv in the next addition processing. And repeat these operations. In the schematic diagram after the addition operation, the pixel center associated with the addition in the horizontal direction is shifted to the next row to which the larger weight is applied, instead of the center row of the two addition target rows, that is, at the time of addition The center of gravity. Specifically, not in the horizontal direction at the time of addition, the position obtained by dividing the spatial distance between the first line Ih and the next line Jh by 2 points becomes the center after the addition, and the center is shifted. The next weighted Jh side 1/3 line of the large weight (refer to Fig. 13F). The case of this 1 2D is the same, however, since the weighted shift direction is intersected, the pixel center after the addition becomes different from Fig. 12D. For example, each center position is: for the first row and the third row, the ratio of 2:1 is doubled and weighted, and the displacement is shifted to the position where the first row leaves 1/3 row; for the second row and the fourth row, In order to add by double the weight of 1: 2, shift to the third row side and leave the third row 1/3; for the fifth row and the seventh row, after double addition, shift by 2:1 ratio The position from the fifth line side to the sixth line 1 / 3 line; the sixth line and the eighth line, in the ratio of 1: 2 in the double weighted addition bit to the eighth line side leaves the seventh line 1 / 3 line s position. If the sum of the sums in the vertical direction shown in Fig. 13 C is as above, the center of the addition is obtained by subdividing as follows, and the first column I v is divided by 2:1. And twice in the next column J v, twice the number of digits, the center of gravity of the horizontal side of the phase Jh: 1 to the change of the applied system and the figure, the weight of the line in the second line is proportional to the The shifting heart is grouped: the distance between each space -77-200845735, and the distance between the first row Ih and the next row Jh within 2:1, as shown on the right side of Figure 13D. In this example, the pixels in the same column order in Fig. 8A are read out, and the weighted shift directions due to the addition processing are alternately changed. Therefore, the center of the added pixels is arranged at a more equal distance in the case where the simple addition is performed. As a result, it is possible to obtain a resolution signal (digital signal) in which simple addition is performed, and the weighting of the simple addition is uniform. [Example of switching between sequential and double-weighted addition of 1:2 ratio] When the double-weighted addition of the 1: 2 ratio shown in Fig. 9 is applied and the order of use of the column or row is different from that shown in Fig. 8A By alternately switching the order of access, in practice, the spatially related relationship between the column and row configurations '1: 2 ratio double-weighted addition and the 2:1 ratio double-weighted addition are alternately repeated. This completes the weighted addition seen in the shift direction. For example, as shown in FIG. 14A, in the addition processing in the vertical direction, the vertical selection signal Φ VSEL is in the third column, the first column, the second column, the fourth column, the seventh column, the fifth column, and the The order of the six columns and the eighth column is specified by the bottom column (Fig. 14B), which is arranged in the order in which it is read by the line processor 26, when the same color of the odd or even columns is When input is in the vertical direction, each row A/D circuit 25 arranged in each vertical line in the line processor 26 performs an addition operation. At this time, since the row A/D circuit 25 is operated at the timing shown in FIG. 9, in each addition operation, the counter 254 performs the next column Jv frequency division operation as the first column Iv - 78- 200845735 It is twice as fast. The addition processing is performed by setting the weight of the first column 1V (the third column, the second column, the seventh column, and the sixth column) to 1 and the next column Jv (the first column, the fourth column, the fifth column, and the The weight of the eight columns is 2, which is executed by the "X 2" on the right side of the figure. Under the prior control of the vertical scanning circuit 14, there is a spatial relationship in the column arrangement, in particular, the added columns Iv and Jv are switched to double the weighted addition by the 1:2 ratio and 2 : The double-weighted addition of the ratios is alternately repeated. The addition processing performed by the weighted doubling of the first column, the fourth column, the fifth column, and the eighth column is similar to the processing of Figs. 13A to 13F. As a result, as shown in Fig. 14C, the intention after the addition becomes the same as that shown in Fig. 13C. The digital arithmetic unit 29 sequentially acquires the column addition data ADD, and performs an addition operation on the image in the above state when the same color is input to the horizontal direction. At this time, similar to the processing in the horizontal direction, the digit arithmetic unit 29 is in the order of the third row, the first row, the second row, the fourth row, the seventh row, the fifth row, the sixth row, and the eighth row. The analogy is used to obtain the added data, and the double weighted addition is performed in a ratio of 1:2. In each addition operation, the addition processing is performed by setting the first row ih (the third row, the second row, the seventh row, and the sixth row) to be weighted to 1 and the next row Jh (first row, first The weights of the four rows, the fifth row, and the eighth row are 2, as indicated by the "x2" in the lower part of the figure. The next column of addition processing is set to weight the weight of the first row Ih (the second row and the sixth row) to 1 and the next column Jh (the fourth row and the eighth row) to 2, to the lower side of the figure. x 2" means to be executed. The first row, the fourth row, the fifth row 79-200845735 and the eighth row are processed by doubling the weighting. Under the prior control of the horizontal scanning circuit 12, there is a spatial relationship in the row configuration, in particular, the rows Ih and Jh which are subjected to the addition are switched to double the weighted addition by the ratio of 1:2 and 2 : The double-weighted addition of the ratios is alternately repeated. The addition processing performed by the weighted doubling of the first line, the fourth line, the fifth line, and the eighth line is similar to the processing of Figs. 13A to 13F. As a result, as shown in Fig. 14D, the intention after the addition becomes the same as that shown in Fig. 13 D. In this example, at each addition processing, the double-weighted addition of the ratio 1:2 shown in Fig. 9 is weighted for the counter 254 (specifically, the control of the count clock control signal TH) When executed, in fact, related to the spatial relationship in the column and row configuration, the double-weighted addition of the ratio 1: 2 and the double-weighted addition of the ratio 2: 1 are alternately switched by alternately. The order of the columns or rows is alternately repeated. As a result, similarly to Fig. 13, the center of the pixels after the addition is arranged at a more equal interval than when the simple addition is performed. As a result, a higher resolution signal (digital data) can be obtained by performing simple addition, and the weighting 値 in the simple addition is uniformly applied. It can be understood from the above description that it is not always possible to arrange the positions of the pixels to be equidistant after the addition by simply applying the weighted addition. In order to make the pixel centers more evenly spaced after the addition of weights, it is important to consider how to add the target pixels and what 値 is used as the weight 値. Furthermore, when capturing a color image, the image can be affected by the color arrangement of the color separation filter. In other words, in order to perform the addition without color mixing -80-200845735, and the spatial distance relationship is made into the same color configuration of the original color separation filter, the relationship between the added target pixel and the weighted 値 selection can be imagined. There are a number of restrictions. [Modified Example of Force Function] In the above detailed description, the double-weighted addition processing of two columns and two rows arranged in Bayer is described. However, this is only an example. It is possible to vary the weighting 値, the spatial position of the added target column and the row, and the number of added target columns and rows. For example, for weighting 値, it is not limited to twice, and a larger number, for example, a power of 2 of 4, 8, ... can be used. For example, in the above description, the display counter 254 performs the frequency dividing operation at the time of A/D conversion at twice the speed, but is not limited thereto, and the flip-flop 5 10 is controlled to perform the counting operation at a higher speed (dividing operating). At this time, the quantization step can be performed coarser. For example, if the count execution unit 504 is configured as shown in FIGS. 4 and 5, by setting the count clock control signals ΤΗ00 and TH01 to be active Η 'the frequency division operation of the counter 254 in the last 2 bits can be increased by 4 times. fast. This allows the digital data "Dsig - Iv + 4 · Dsig__Iv" to be obtained by adding the digit 値 Dsigjv of the signal component Vsig_Iv in the column Ιν to the digit 値 Dsig__Jv of the signal component Vsig_Jv of the 4x column JV. Furthermore, by setting the count clock control signal ΤΗ 02 to be active, the frequency division operation of the counter 254 of the 3-bit pixel of the rear unit pixel can be increased to 8 times faster. This allows the digit data "Dsig_Iv+8 · Dsig_Iv" to be obtained by adding the digit 値Dsig_jv of the signal component Vsigjv in the column Jv to the digit 値Dsig_Iv of the signal component Vsig_Iv -81 - 200845735 of the column Iv. If the count clock control signal TH0T (T = S-1) is set to be active, the frequency division operation of the counter 254 after the S bit can be increased to 2 - S times faster, so that a gain can be increased by 2 - S Bigger. This allows the digital data "Dsig_Iv + 2A S · Dsig__Iv" to be obtained by adding the digit 値Dsig_Iv of the signal component Vsig_Iv in the column Ιν to the digit 値Dsig_Jv of the signal component Vsig_Jv of 2, S times column Jv. When the frequency division operation of the counter is made into a high-speed division operation (faster) via several stages, such as L1 times (= 2), L2 times (4), L3 times (= 8), etc., if lower, if lower The frequency-division operation of the order bit output is invalidated and the remaining higher-order bit outputs are executed at a higher speed to perform the quantization step more coarsely, and the start count clock for controlling the higher order bits can be maintained. For the same speed as the count clock CIN. Although it seems that the resolution of the A/D conversion for the signal component Vsig_Jv in the weighted target column Jv is lowered by the counter operation, there is no substantial difference in the entire counter operation according to the original count clock CIN, and therefore, the power is not increased. Consumption. As described above, the weighting 値 can be applied as a power of 2, for example, 2 times, 4 times, 8 times, ... and so on, by changing the setting of the count clock control signal TH, and the weighting 値 can be adjusted 'to make The added pixel spatial position is arranged to obtain a higher resolution image, that is, the pixel positions after the addition can be arranged at a more equal pitch. Figure 15 is a diagram showing the mechanism for setting the weighting 値 to an arbitrary integer. -82- 200845735 In terms of setting the weighting, it is not only the power of 2, but also any 値. At this time, if the slope of the reference signal Vslop is maintained at a fixed level, it is preferable to change the count clock CK0 supplied to the counter 254 to a higher speed clock. Furthermore, when a mechanism that does not have to change the clock frequency of the count clock CK0 is employed, the setting of the count clock control signal TH is changed to change the frequency dividing speed of the counter 254 by one bit unit, and a weighting 値 is set to arbitrary Integer, the slope of the reference signal is adjusted by changing the setting of the slope change command signal CHNG. At this time, there are two relationships between the setting of the reference signal Vslop, the setting of the frequency dividing speed of the counter 254, and the weighting 値G to be set, as shown in Fig. 15. Specifically, assuming that the weighting 値 set is G, the conceivable method is: the first method, wherein the frequency dividing speed of the counter 254 is set to 2·n times and the slope of the reference signal Vslop is set to the factory n. /G, to satisfy the formula, where '2~(n+l)>G>2~ η", and the second method 'where the frequency dividing speed of the counter 254 is set to n times and the slope of the reference signal is Set to factory n/G to satisfy the formula "2, n > G > 2~ (η-1). In any case, the product G is obtained by multiplying the A/D conversion gain 2 to n obtained by increasing the frequency dividing speed by the A/D conversion gain G/2 - η obtained by changing the slope of the reference signal Vslop ( The reciprocal of the multiplication factor of the slope is obtained. For example, if the weighting 値 is set to unit pixel 3 'the frequency dividing speed is set to twice the speed' and the slope of the reference signal Vslop is set to 2/3 times the slope in the first method, in the second method The mid-divide speed is set to 4 times, and the slope of the reference signal Vslop is set to 4/3 times -83 - 200845735. It can be seen from the figure that in the second method, the multiplication coefficient set to the frequency dividing speed of the counter 254 is larger, so that the slope of the reference signal Vslop can be larger than the difference amount, and the advantage is that the A/D conversion period can be Make it smaller, even if the resolution is reduced. On the other hand, in the first method, although the multiplication coefficient set to the frequency dividing speed of the counter 254 is small and the A/D conversion speed is long, the resolution is not lowered. As described above, in addition to the power of 2 for changing the setting of the count clock control signal TH and the setting of the slope change command signal CHNG, it is also possible to change the weighting 藉 by using an arbitrary 値. Therefore, the weighting 値 can be adjusted so that the spatial positions of the added pixels are arranged at more complete intervals to obtain a higher resolution image. As described above, even if the pixel positions after the addition cannot be arranged by the weighting 2 of the power of 2, it is possible to set the weighting 藉 by setting the weighting 値 in any 値, so that the addition is performed. The pixel locations are then arranged at exactly equal spacing. For example, Figures 16A through 16F show "addition of ratio 3:1 + addition of ratio 1:3", where the weighting 値 is set to 3, and Figures 7A to 17F show "proportion of ratio 4:1" Plus + ratio 1: 4 plus", where weighting. 値 is set to a weight of 42. The setting of the weighting 値 adjustment and the adjustment of any power other than the power of 2 increase the elasticity of the pixel space position adjustment after the addition, and thus it is possible to find a ratio. The weighting 値 allows the pixel spatial locations after the addition to be arranged equidistantly. [Method for improving the resolution of the added image: Second Embodiment] A second embodiment of the display method of FIGS. 18 to 21 is for solving the digital addition processing of the counter 254 in the direction of the vertical -84-200845735 and in the digital position. The arithmetic unit 29 performs a problem that the resolution in the digital addition processing is deteriorated in the horizontal direction. 18A to 18C show the disadvantages of the single oblique integral A/D conversion system. More specifically, these figures explain the effect of comparing the processing cycles on the A/D conversion performance, especially for the conversion processing speed, where the analog pixel signal Vx is compared with the reference signal V s 1 ο p for digital data conversion. And at the same time, an example of a method of shortening the comparison processing cycle is displayed. Fig. 19 is a timing chart for showing the addition processing in the vertical direction in parallel with the A/D conversion processing to explain the second embodiment. Figure 20 is a diagram for showing the effect of the resolution improvement method when the count clock switch 51 is operated in the second embodiment. Figure 2 is a diagram showing the relationship between the change control of the slope of the reference signal Vslop and the frequency division speed control of the counter. In addition to the addition processing operation of the first embodiment, the second embodiment has a feature in that even In the processing of one column, when the signal level Ssig is processed, before the comparison processing is completed, in the comparison processing period of the voltage comparator 252, the slope of the reference signal Vslop and the frequency dividing speed of the counter 254 are changed in cooperation with each other, so that The A/D conversion gain remains unchanged in this column, i.e., the weighted chirp of the pixels in the column is held at a fixed chirp. This makes it possible to obtain a higher resolution added image at a high speed. Specifically, the slope change command signal CHNG is supplied to the reference signal generator 27 to change the slope of the reference signal Vslop to the J-fold slope, and the count mode control signal UDC, the reset control signal CLR, the data hold control pulse HLDC, And the count clock control signal TH is supplied to the counter execution unit 504 of the -85-200845735 counter 2 5 4 so that the frequency division operation of each bit output in the count execution unit 504 is changed to the κ speed ( Preferably, K times = J times). While changing the slope of the reference signal Vslop to a J-fold slope, the flip-flop 5 10 is controlled to operate at a K-speed (preferably J-speed) counting operation (frequency dividing operation), but as long as the error (change) Within the allowable range, it is not necessary to accurately "at the same time" or precise J-fold multiplication factor. This is the same as the general technique of allowing an error to be controlled within a setting range as long as the error (change) is within a permissible range. However, basically (in principle), in the A/D conversion processing of the signal component Vsig, the multiplication coefficient and the change timing are necessarily the same to obtain the digital data Dsig of the true reflection signal component Vsig without the correction operation, even in the reference. The signal Vslop is changed to be the same before the signal level Ssig and the reference signal Vslop match. In the present embodiment, the line processor 26 (specifically, the row A/D circuit 25) performs a single oblique integration A/D for each reset level (reset potential) and a signal level (signal potential). Conversion processing. At the same time, the reset potential is processed by one of the upper or lower modes (in the previous example, the lower mode), and the signal potential is processed by another mode (in the previous example, the upper mode), The digital data of the difference between the two processes can be automatically obtained by the result of the counting process of the second process. In the single-slope integral A/D conversion system used in this embodiment, the resolution of the A/D conversion, that is, the size of the 1LSB is the counter 254 when the slope of the reference signal Vslop and the period and the reference signal Vslop is changed - 86- 200845735 The counting speed (that is, the frequency of the counting clock) is determined. For example, assume that the period in which the counter 254 counts a count is a count cycle, the amount of change in the reference signal Vslop in the count cycle becomes the resolution of the A/D conversion (width 1 LSB). When the width of 1LSB is small (narrow), the resolution of A/D conversion is high, and when the width of 1LSB is large (wide), the resolution of A/D conversion is low. Therefore, for example, when expressed in the counting speed, the faster the speed, the shorter the counting cycle. If the slope of the reference signal Vs lop is the same, the variation of the reference signal Vslop, that is, the width of 1 LSB becomes small at the time of the counting cycle, so that the resolution of the A/D conversion becomes high. If the slope of the reference signal Vslop is the same, if the counting speed becomes faster, the counting 値 advances to the point where the reference signal Vslop and the signal voltage on the vertical signal line 19 match, then a larger digital data and A/D conversion can be obtained. The gain becomes higher. This means that the change in the count speed is equivalent to the adjustment of the A/D conversion increase and the control of the read gain. Furthermore, the slope of the reference signal Vslop is expressed. When the counting speed is the same, the larger the slope is, the smaller the amount of the reference signal Vslop is changed in the period, that is, the width of the ALS is higher when the width is 1 LSB. . Moreover, when the counting speed is the same, the larger the slope, the more time it takes to match the signal voltage on the reference signal Vslop and the vertical signal line 19, so that a larger digital data and an A/D conversion gain can be obtained. high. In other words, when the count speed is the same, when the slope of the reference signal Vslop is changed to control the twist of 1 LSB, the matching time of the reference signal Vslop and the pixel voltage Vx on the vertical signal line 19 is adjusted. As a result, even if the pixel signal voltage Vx on the vertical signal line 19 is kept the same, the count 値 at the time of the -87-200845735, that is, the digital data of the signal voltage is adjusted. This means that the slope change of the reference signal V s 1 ο p is equivalent to the adjustment of the A / D conversion gain and the adjustment of the read gain control. In the embodiment of the present invention, the above is used, and in the addition processing, the frequency dividing speed is set to a high speed (the reference signal Vslop is changed depending on the weighting 値) and weighted addition is performed. At this time, in order to perform higher speed and higher accurate processing, it is necessary to make the line A/D circuit 25 faster. In the row A/D circuit 25, in order to complete the further speed ' If the slope of the reference signal Vslop is not adjusted, the counter 2 5 4 needs to operate faster. In order to increase the speed of the counter, the counting clock speed is increased. However, since the row A/D circuit 25 and the row A/D circuit 25 in each row must perform the counting operation at a high speed at a high speed, the problem of an increase in power consumption can occur. In order to complete the high-speed A/D conversion processing and solve these problems at the same time, it is thought that the speed of the A/D conversion can be made variable by compressing the counting time by adjusting the reference signal Vslop side without increasing the counting clock speed. Complete high speed processing. For example, as shown in FIG. 18A, background noise (inductor noise reference) and optical scattered noise in the pixel signal generator 5 are known in addition to signal components (signal responses) corresponding to the light particles. (Photon shot noise) is applied to an optical signal output (sensor output) regarding the light intensity output from the unit pixel 3. When the sensor output is A/D converted, if the sensor output below the level of the sensor noise reference is A/D converted, the signal from the sensor output -88-200845735 is buried in the sensor. The 'so' conversion of the benchmark has become meaningless. Therefore, the sensor output that exceeds at least the sensor noise level is the effective range for A/D conversion. The photon shot noise is relative to the photon change corresponding to the 1 /2 power optical signal. Therefore, when the amount of signal is small, there is less photon-scattering noise, so that the optical signal can be accurately converted to A/D with high-resolution A/D conversion. However, when the amount of signal is large, the photon shot noise is relatively large, so that even if the optical signal is A/D converted with high resolution, the optical signal is not always accurate due to the amount of photon shot noise. A/D conversion. In a region where the amount of optical signals is large and a large amount of photon shot noise is included, only the resolution of the signal component for removing photon shot noise may be used. For this reason, if the resolution of the A/D conversion is lowered (in other words, if the quantization step becomes thicker) within the range, there is no problem with the accuracy of the A/D conversion result. In the above method, it can be imagined that the A/D conversion speed can be adjusted according to the signal by adjusting the accuracy of the A/D conversion, in other words, by adjusting the resolution or the quantization step when the signal amount becomes large. The amount gets faster. For example, as shown in Fig. 18B, when the sensor outputs (corresponding to the amount of photoelectrons of the signal component: the unit is "a. u. ") is between level 0 and level 1, then the quantization step is set to 1LSB, and the sensor output is between level 1 and level 2, and the quantization step is set to 2LSB, similarly And similarly according to the upward level, the quantization step is thicker, that is, the resolution is lower. This means that if the sensor output level is upward, the lower order of the counting execution unit 5 0 4 in the counter 254 is formed. The bit-reactor 5 1 0-89-200845735 is ignored in the order of the sensor output level, and only the higher-order bit-reactor 5 1 0 can be operated. On the other hand, in order to be based on the sensor output The level gradually changes the resolution. It can be understood from the above description that the slope of the reference signal Vslop is gradually changed to a steep slope, and the voltage change per unit time, that is, the voltage difference (mV/digit) of each count is changed as This is shown in Fig. 18C. However, in the above case, since the A/D conversion gain becomes small, the linearity of the A/D conversion result regarding the sensor output is impaired. For example, each digit is at the reset level. Srst A/D conversion period Trst and A/D at signal level Ssig The voltage 値 (conversion coefficient) before the change point in the conversion period Tsig is α [V/digit], and the voltage 値 (conversion coefficient) of each digit after the change point becomes a /J. Therefore, if A/ The count of the D conversion result 値D is converted into a voltage 値· If the count 値 at the change point is “m”, it becomes “α · m + (Dm) · a /J”, which makes the size of the sensor output In order to avoid this, it is conceivable to add the gain correction by making the count clock faster, offsetting the degree of change of the slope of the reference signal Vslop, that is, the relationship between the count 値 and the voltage △. The V/Δt system is kept constant. At this time, the technique of simply making the count clock faster cannot be practically used because the aforementioned problem may occur. Therefore, if a mechanism is employed, the internal count clock is actually The change is not changed, and the count of the A/D conversion result is automatically corrected by the slope of the reference signal Vslop, for example, to "α · m + (D_m) • α/J· J", and the count 値 becomes "α". · m + (Dm)· a = a · D,,, make -90- 200845735 The size of the sensor output can be accurately obtained. In the second embodiment, as a mechanism for automatically correcting, a mechanism for changing the frequency dividing speed of the counter 254 is employed. It is explained in detail as follows, in which the order of addition is set to be the same as the processing shown in Fig. 13. In the A/D conversion period Trst of the reset level Srst, the reset levels Srst_Iv and Srst_:iv of the unit pixel 3 are read, and the counter 254 counts down the levels Srst_Iv and Srst_Jv. At this time, all of the count clock control signals ΤΗ00 to TH1 1 are set to be inactive L. Furthermore, in the A/D conversion period Tsig of the signal level Ssig, the reference signal Vslop is changed to be the same as the slope at the beginning of the A/D conversion period, and the counter 254 is counted by each of the digits 値Drst_Iv and Drst_Jv. At this time, all of the data hold control pulses HLDC00 to HLDC1 1 are set to be inactive L, and all of the count clock control signals ΤΗ00 to TH11 are set to be inactive L. At a point R(t21_Iv), the slope of the reference signal Vslop is changed to a double slope (for example, twice the slope), and the frequency division operation of the flip-flop 5 1 0 before the point R is made K times speed ( Preferably, K = J). For example, at the time of processing of the first addition target column Iv, the slope of the reference signal Vslop is changed to twice the slope at the point R_Iv(t21_Iv), and the data holding control pulse HLDC00 to the data holding unit 5 12_00 is switched. The operation clock and the count clock control signal TH 0 0 to the count clock switch 516_00 are switched to the operation Η. At this time, the pixel fe number voltage V X _ I ν in the column I ν in a certain row on the vertical signal line 19 is digitally converted to the count 値m 0 __ I ν . For the count -91 - 200845735, the actual number of the number 254; the system is determined by the period between the "t21__Iv-t20 Iv" and the count clock cycle, because the upper number is started by the negative 値Drst_Iv, here again At the time 'because the data hold control pulse HLDC 0 0 is set to the operation Η 'so the data recorded in the least significant bit flip-flop 5 1 0 is held. After the point R — Iv(t21_Iv), the least significant bit output is invalidated. Since the least significant bit output is made invalid after the point R_Jv(t21_Iv), the period after the point R_lv(t2 1jv) becomes the low resolution period Tssig_LlIv. Furthermore, at the same time, if the count clock control signal ΤΗ00 is switched to the operation Η, and the least significant bit (in the 〇 bit) the input clock of the flip-flop 510_00 is transferred to the second-stage (at 1-bit) flip-flop 512_〇1 clock terminal. By transmitting the clock of the least significant bit to the next bit, the frequency dividing operation of the remaining higher bit output is performed at twice the speed, except for the least significant bit, the counter 2 5 4 starts at twice the speed Up, while keeping the quantization step twice as thick as before. For example, Fig. 20 is an output diagram of each flip-flop 510 when the slopes of the count clock control signal ΤΗ00 and the reference signal Vsl 〇p are changed. At the point R_Iv(t21_Iv), the count clock control signal ΤΗ00 is switched to the operation Η so that the count clock CIN supplied to the least efficient flip-flop 510_00 is transferred to the second-stage flip-flop 5 1 0_0 1, so that the lower-order positive and negative The device 5 10 operates at high speed after switching. However, since the least significant bit output becomes invalid, the quantization step becomes thicker than before. For example, if the -92-200845735 cycle of the count output D00 of the first-stage flip-flop 510_00 is 100 MHz before the count clock control signal ΤΗ00 is switched, and the count output D01 of the second-stage flip-flop 510_01 is 50 MHz. Different from this, when the count clock control signal ΤΗ00 is switched to the Η level, and the count output D01 of the second stage flip-flop 510_01 is 100 Hz, the frequency division operation of the higher order bit flip-flop 5 1 0 is performed. It is operated at twice the speed. Furthermore, regarding the pixel signal voltage Vx_Iv, the low-resolution period Tsig_LlIv after the point R_Iv(tl2_IV), when the signal level Ssig__Iv and the reference signal Vslop match (t22_Iv), the counter 254 stops while keeping the count at the time of matching.値zO_Iv. At this time, the slope of the reference signal Vslop becomes twice the speed before the point R_Iv(t21_Iv), and the higher order bit flip-flop 5 1 0 in the counter 254 also performs the frequency dividing operation at twice the speed. Therefore, the relationship between the count 値 and the voltage 变成 becomes 2 Δ V / 2 Δ t = Δ V / Δ t, and the relationship between the count 値 and the voltage 値 Δ V / Δ t is stable, which results in maintaining the A/D conversion result relative to The sensor output is linear. The final count 値zO__Iv itself automatically changes to the digital data Dsig, which truly reflects the signal component Vsig, so no external circuit is required for correction. After the A/D conversion period of the column Iv is completed, it is not necessary to reset the counter 2, the read operation and the A/D conversion processing of the unit pixel 3 in the column Jv are sequentially performed, and the reading similar to the processing of the column Iv The out operation is repeated. At this time, the slope of the reference signal Vslop becomes the same as that of the column Iv. The data hold control pulse HLDC_00 and the count clock control signal ΤΗ — 00 are held as active Η. In this way, the ramp-93-200845735 rate of the reference signal Vsl〇p is the same as that of the column Iv, and the higher-order flip-flop 5 1 0 in the counter 254 performs the double-speed division operation so that the count is performed. The relationship between 値 and voltage 变成 becomes 2 Δ V / Δ t. Therefore, at the beginning of the processing of the column JV, the pixel signal voltage Vx_Jv is processed by twice the gain compared to the processing of the column Iv. While changing the slope of the reference signal Vslop to twice the slope of the point R(t21_Jv), the data holding control pulse HLDC01 to the data holding unit 5 1 2 __ 0 1 is switched to the counting clock of the operation Η and to the counting clock switch 516 Signal ΤΗ0 1 is switched to the active Η. At this time, the pixel signal voltage Vx_Jv in the column J is digitally converted into a count 値. The number of the actual number of the counter 254 is determined as the period between "t21 - Jv - t20jv" and the cycle of the count clock, and the count 値 mO_Jv at the point R_Jv (t21_Jv) is determined because the upper number is negative Start with Drst_Jv. Furthermore, at this time, since the data retention control pulses HLDC 00 and HLDC01 are the active Η, the least significant bit (in the 〇 bit) of the flip-flop 510_00 and the second-level (in the 1-bit) flip-flop 510_01 The information is kept. In fact, after the point R - Jv (tl2_h), the least significant bit (〇 bit) output and the second level (1 bit) output are invalidated. Since each output of the 〇 bit and the i bit is invalid after the point R_Jv(t21_Jv), the period after the point _"〇21_") becomes a lower resolution period §_1^11乂. Furthermore, at the same time, if the count clock control signal ΤΗ0 1 becomes active, the input clock of the 1-bit flip-flop 510_01 is transferred to the clock terminal of the third-stage (at 2-bit) flip-flop 510_02. Loop to the next -94-200845735 bit, except that the 0-bit and 1-bit output is executed twice as fast as the previous double-speed operation, that is, four times, the division of other higher-order bits The operation will output, so that the counter 254 starts the quadruple speed up and makes the quantization step thicker. Furthermore, regarding the pixel signal voltage Vx_Jv, the low resolution period Tsig_LlJv after the point R_Jv(t21_Jv), when the signal bit When the quasi-Ssig_Jv and the reference signal Vslop match (t22_Jv), the counter 254 stops while maintaining the count 値zO_Jv at the time of matching. At this time, the slope of the reference signal Vslop becomes twice the speed before the point R_Jv(t21_Jv), and Higher order bit in counter 254 The inverter 5 10 also performs the frequency division operation at four times speed. Therefore, the relationship between the count 値 and the voltage 变成 becomes 2 Δ V / 2 Δ t = Δ V / Δ t, and the count 値 and the voltage 値 Δ V / Δ The relationship between t is stable, which keeps the A/D conversion result linear with respect to the sensor output. The final count 値z 0 _ J v itself automatically becomes the digital data Dsig, which truly reflects the signal component Vsig, therefore, no external circuit is required for correction. After the A/D conversion cycle of the column Jv is completed, it is not necessary to reset the counter 2 54 'the reading operation of the unit pixel 3 in the column JV and the A/D conversion processing are sequentially performed, and the processing similar to the column J v The read operation is repeated. At this time, the slope of the reference signal Vslop becomes twice as large as that after the point R__Iv(t21JV) of the column Iv, and on the other hand, the higher order flip-flop 5 1 in the counter 254 0 performs the frequency division operation of the quadruple speed. Therefore, the relationship between the count 値 and the voltage 变成 becomes 4 Δ V / Δ t = 2 Δ V / Δ t, and the relationship between the count 値 and the voltage 系 is as before Stable, so that the pixel signal -95- 200845735 voltage Vx_Jv is compared to the column Iv The double gain processing of the processing. As a result, for example, if, for example, the number of bits is at the A/D conversion period Trst of the reset level Srst and the change point R in the A/D conversion period Tsig of the signal level Ssig The previous voltage 値 (conversion coefficient) is α [V/digit number], and the final count 値 held in the counter 254 is "Δν" §_Ιν + 2α xVsig_Jv", and the weighted addition is completed. For example, assume that the digits in parentheses on the line graph of the pixel signal voltage Vx of FIG. 19 are as shown, the signal components Vsig_Iv and Vsigjv in the column Iv and the column Jv are 60, and their reset levels Srst_Iv and If Srstjv is 10, a two-bit weighted addition is performed. The counts that are kept at each time order become similar to those shown in Fig. 9. More specifically, in the A/D conversion of the signal level Ssig_Iv (signal component Vsig_Iv) in the column Iv, by performing the A/D conversion by the reset level Srst_Iv, the count 値"_Drst_Iv" (= -10) As the starting point starts counting, the count held in the counter 254 becomes Μ-ΐ 0+70=60=Dsig_Iv,, after processing. Then in the A/D conversion of the column Jv, the number of the reset level Srst_Jv is executed as the start 値 "6〇 = Dsig_Iv", and the count is obtained by the A/D conversion in the column Iv. The count that is held in the counter 254 becomes "5 〇-2 X WMO". Furthermore, the number used for the signal level Ssigjv is executed by the count 値40 as the starting point, and the count 予以 held in the counter 254 becomes "4〇+ 2χ 7 0= 1 8 0 after processing. , this count 値 denotes "Dsig - Ιν + 2 · Dsigjv", which is obtained by adding the digit 値Dsig__Iv of the signal component Vsig_lv in the column Iv to the column -96-200845735

The digital component of the signal component Vsigjv in Jv is obtained by Dsig_Jv. It can be understood from the above description that even if the slope of the reference signal Vslop is changed at the A/D conversion processing of the column, if the frequency dividing speed is changed to compensate for the slope change, the final count 値z, that is, the digital data Dsig of the signal component Vsig is not Will be affected by the change in slope, and if the signal component Vsig is the same, the final count 値z (= Dsig) matches. This becomes unnecessary to correct the final count 値, of course, without a function unit to keep the count at the change point 値m. Since the slope of the reference signal Vsig does not become large after the change point R, the A/D conversion period can shorten the amount of difference so that the added image can be obtained at a relatively high speed. In the above description, it is explained that in the A/D conversion processing of a certain column, the slope of the reference signal Vslop is set to twice the slope and the frequency dividing operation of the counter 254 is increased to twice the speed. However, without being limited thereto, the slope of the reference signal Vslop may be changed in accordance with the rise of the sensor output level, and the stages and the flip-flops 5 10 are controlled to perform the counting operation (dividing operation) at a higher speed. At this time, the quantization step becomes thicker. For example, if the counting execution unit 504 is structured as shown in FIGS. 4 and 5, in the processing of the column Iv, the slope of the reference signal Vslop is set to be 4 times larger and the count clock control signal ΤΗ0 1 is set to be active Η, The frequency division operation after the counter of the 2-bit counter 2 5 4 is operated at 4 times is shown in FIG. 19 . Furthermore, if the slope of the reference signal Vslop is set to 8 times larger and the count clock control signal TH02 is set to be active, the operation is performed after the 3-bit counter 2 5 4 is operated at 8 times speed -97-200845735 After the crossover operation. Similarly, the slope of the reference signal Vs lop is set to 2 - S times (S is a positive integer, "~" is a power), and the count clock control signal TH0T (T = S-1) is set to be activated, thereby Completion of the frequency division operation after the counter 2 5 4 of the S bit is operated at 2 to S times. As described above, if the slope of the reference signal Vslop depends on the magnitude of the signal component V sig (in other words, the size of the photon shot noise), it undergoes several stages of change (gradual change to a steep slope), for example, J1 times (= 2 bits) ), J2 times (4 times), J3 times (8 times)... and so on, the period of the full swing of the reference signal Vslop is further shortened, thereby performing A/D conversion at a higher speed. Furthermore, the frequency division operation of the counter is changed to operate at a higher speed through several stages, depending on the slope of the reference signal Vslop, such as K1 times (2 times), K2 times (4 times), K3 times (8 times), And so on, and the lower order data becomes invalid, so that the exact count 对应 corresponding to the signal component Vsig is taken as the final output regardless of the count 値 at the point of changing the reference signal V s 1 ο p . Since more low-order bit data is invalidated, the quantization step is thicker and the resolution in A/D conversion is lower, but with regard to photon shot noise, the lower the accuracy will not be for A. The /D conversion result caused a problem. Since the time required for the comparison processing is shortened by setting the slope of the reference signal Vslop to be steeper (larger), the number of counter operations can be reduced, so that the high-speed A/D conversion, that is, the A/D conversion period is shortened. Conversely, if the A/D conversion period remains the same, the number of counting operations can be reduced, so that low power consumption is achieved. Furthermore, when the frequency division operation of the counter becomes faster through several stages, if the lower order bit output is sequentially invalidated and only the remaining higher order bits are divided, the operation is performed at a high speed to be thicker. When the quantization step is performed, the start count clock that controls the meta-output can be kept at the same speed as the count clock c IN . Although the resolution of the A/D conversion is lowered, the entire count is operated according to the original count clock C IN , and therefore, without increasing the power consumer, when the signal component Vsig becomes larger, the quantization step is performed by using photon information. Thicker to reduce A/D conversion accuracy, so A/D conversion accuracy does not seriously impair A/D conversion accuracy. The point R at which the slope of the reference signal Vslop changes is variable, and the mode is performed depending on whether or not the relationship between the photon shot noise and the quantized noise of higher accuracy or faster speed is required. Furthermore, in the former example, when the reference signal Vslop is inclined to 2 S times, it is displayed that when S is changed by 1 and, for example, 1, the present invention is not limited thereto, and any variation step may be , 2, 4, and so on. In this relationship, mode switching is performed based on the photon shot noise and the quantized miscellaneous relationship depending on the accuracy or faster purpose. When the weighted addition is performed by using photon shot noise, the number of operations can be reduced without seriously damaging the A/D conversion level so that high-speed A/D conversion can be performed at the time of weighted addition processing. The resulting A/D conversion cycle is the same, and the number of counter operations can be reduced to achieve lower power consumption. [Method for improving the resolution of the added image: Third Embodiment] Fig. 20 is a diagram showing the actual consumption of the same high-order bit in the vertical direction by the counter 254. The re-grain is actually switched and is set according to the rate, 2, 3, for example, the counter accuracy between the higher quasi-symbols, and, for example, the row digits -99-200845735 is added and processed by the digital arithmetic unit 29 The third embodiment of the method of solving the resolution degradation by the direction line digital addition processing. In the third embodiment, the weighted addition processing of two columns and two rows is not performed, but the weighted addition processing of three columns and three rows. A weighted addition process of three of the row directions is not necessary. When performing the addition processing of three pixels, for example, the weighting of three pixels may be different from each other or the weighting of only one pixel may be different from the weighting of the other two pixels. In the latter, the relationship between them is set to a ratio of 1: n : 1 (η is greater than 1). Preferably, η is a positive integer or any 値 greater than 2, for example, 2, unit pixels 3, 4, .., etc., preferably a power of 2, for example, 2, 4, 8, ... and so on. The method used to set these weights is similar to the weighted adders for two pixels. For example, as shown in FIGS. 22A and 22B, the weighted addition operation of three columns and three rows can be completed by combining the weighted addition processing in the vertical direction and the weighted addition processing in the horizontal direction, and the addition processing in the vertical direction. This is performed by the row A/D circuit 25 in units of three columns in the vertical direction, and in the horizontal direction, the addition processing is performed by the three-behavior unit as the digital arithmetic unit 29 in the horizontal direction. The application form of the weighted addition processing of three columns and three rows, for example, if the coefficients of all the processing target pixels are set to be the same, then the smoothing filtering process as shown in Fig. 20A will be performed, but if a weighting 値 is set so that the center The coefficient of the pixel is set to be larger than the coefficient of the peripheral pixel, and the weighted addition processing of the enhanced center pixel can be completed as shown in FIG. 20B. At this time, for example, when pixels are read out in an interlaced scan, they may be weighted by a ratio of -100-200845735 1 : 2 : 1 and emphasized at the position of the center of gravity after the addition to obtain a local resolution. Image. The relationship between the weighted addition of the ratio of the ratio 1: 2:1 and the spatial position after the addition is as follows. More specifically, in the weighted addition of the ratio 1: 2: 1, the spatial position after the addition does not change, similar to the weighted addition of the 丨:1:1 ratio, but the center position is emphasized after the addition. The high-resolution image can be completed in the process of changing the spatial position after the addition. [Camera device] Fig. 2 is an architecture diagram of an image pickup device, which is an example of a physical information acquisition device based on the above-described solid state imaging device 1. A camera device 8 is an imaging device for capturing visible light color images. The mechanism of the above-described solid-state image pickup device 1 is not only applied to a solid-state image pickup device but also to an image pickup apparatus. At this time, in the image pickup apparatus, it is possible to obtain high resolution by changing the spatial position after addition by weighted addition. At this time, the counting frequency of the counting becomes faster to control the setting of the weighting, or the slope control of the reference signal Vslop can be arbitrarily designated by setting the data to the external host controller, and the controller data indicates the switching mode to the communication/timing Controller 20. Specifically, the imaging device 8 includes: an imaging lens 802, an optical low-pass filter 804, a color filter group 812, a pixel array unit 1A, a drive controller 7, a line processor 26, a reference signal generator 27, and Camera signal processor 8 1 0. The photographic lens 082 guides the light L carrying the image of the illumination device, such as the fluorescent object Z, to the side of the imaging device and produces an image of the object Z - 101 - 200845735. The color filter group 812 has, for example, color filters arranged in a Bayer configuration. The drive controller 7 drives the pixel array unit 1 〇. 26 pairs of pixel signals output from the pixel array unit 10 are subjected to or A/D conversion processing. The reference signal generator 27 supplies Vslop to the line processor 26. The camera signal processor 810 performs processing on the incoming image signal. Optical low pass filter 804 is used to block higher than Nyquist rate components to avoid aliasing. Further, the infrared line cut filter 805 for lowering the infrared ray filter 804 can be provided in the same manner as a general image pickup device. The camera signal processor, the camera signal processor 820 and the camera controller 900, which are provided in the next stage of the line processor 26, are actuated to control the entire camera unit 8. The image pickup signal processor 820 has a signal separator 822 and a processor 803. The signal separator 822 has a main color separation function. When one color filter is used, the digital image signal supplied by the A/D conversion function unit is separated, and G (green), B ( Blue) three primary colors.

Furthermore, the image signal processor 820 has a brightness signal 840 for performing signal processing on the luminance signal Y according to the three primary colors ff and B separated by the signal separator 822, and an encoder for sensing the luminance signal Y/color signal. C Generating Video Image VD Although not shown, the color signal processor 830 has an example amplifier, a gamma correction unit, and a color difference matrix unit. White Balance R, G, B Line Processor C D S Processing The reference signal starts from the infrared of the frequency of the frequency of 1 2 6 . This system 810 has a main control color signal for the processor 26: R (red) processor! No. R, G 8 60, such as white balance amplifier root -102- 200845735 according to white since not displayed Balancing the gain signal supplied by the controller, adjusting (white balance adjustment) the gain of the three primary color signals supplied by the three primary color separation function units in the signal separator 822, and supplying the adjusted gain to the gamma correction unit and the luminance signal processor 840. The gamma correction (r) is performed to generate an accurate color according to the adjusted white balance primary color signal, and the gamma correction output signal for each color R, G, B is input to the color difference matrix unit . The color difference matrix unit performs color difference matrix processing and inputs the obtained color difference signals R-Y, B-Y to the encoder 860. Although not shown, the luminance signal processor 804 has, for example, a high frequency luminance signal generator, a low frequency luminance signal generator, and a luminance signal generator. The high frequency luminance signal generator generates a luminance signal YH containing a relatively high frequency component depending on the primary color signal supplied from the primary color separation function unit of the demultiplexer 822. The low frequency luminance signal generator depends on the white balance primary color signal supplied from the white balance amplifier to produce a luminance signal YL containing only low frequency components. The luminance signal generator generates a luminance signal Y depending on the two types of luminance signals YH, YL, and supplies the luminance signal Y to the encoder 860. The encoder 860 digitally adjusts the color difference signals RY, BY using digital signals corresponding to the sub-carriers of the color signals, and combines them to the luminance signal Y generated by the luminance signal processor 840, and converts them into digital bits. Video signal VD (= Y + S + C ; S is the sync signal; C is the chrominance signal). The digital video signal VD outputted from the encoder 860 is supplied to a camera signal output unit which is not displayed at the lower level, and then used as a monitor output or as data recorded in a recording medium. At this time, if it is necessary -103- 200845735, the digital video signal VD is converted into a video signal via D/A conversion. The camera controller 900 in this embodiment has a microprocessor 902, which is the core of the computer, and is represented as a central processing unit (CPU), which integrates the functions of operation and control performed by the computer and is Integrated on an ultra-small integrated circuit; a read-only memory (R〇M) 904 as a dedicated read-out memory; a random access memory (RAM) 906, which is a volatile memory Examples can be used to write and read as needed; and other peripheral components that are not visible. The microprocessor 902, the ROM 904, and the RAM 906 are collectively referred to as a microcomputer. In the above, "volatile memory" means a memory device that erases memory contents when the device is powered off. On the other hand, non-volatile memory is a memory device that retains memory contents even when the device's main computer is powered off. In the memory device, not only the non-volatile semiconductor memory device' but also any memory device can be used as long as they can hold the contents of the memory. Alternatively, it may be used as a non-volatile memory in addition to a non-volatile semiconductor memory. Furthermore, the memory is not limited to a semiconductor memory device, and a media architecture such as a magnetic disk or a compact disk can also be used. For example, a hard disk can also be used as a non-volatile memory. Furthermore, it is also possible to use an architecture as a non-volatile memory' in which information is read from a recording medium such as c D - R 〇 相机 The camera controller 900 controls the entire system. In particular, in the aforementioned processing for completing the high-speed A/D conversion processing, the camera controller 9 has an on/off function for adjusting various control pulses, and various pulses are used in the reference signal generator. Control of the slope change of the reference signal Vslop and control of the frequency division speed in the counter 254. In the ROM 9 04, a control program of the camera controller 9 is stored, and in particular, in this example, a program for controlling the on/off timing of various control pulses of the camera controller 900 is stored. In the RAM 906, various materials processed for the camera controller 9 are stored. Further, the camera controller 900 can insert or remove a recording medium 924, such as a memory card, and connect to a communication network such as the Internet. For example, in addition to the microprocessor 902, the ROM 904, and the RAM 906, the camera controller 900 has a memory reading unit 907 and a communication I/F (interface) 90 8 〇 recording medium 924 for storing data, such as program data, to The microprocessor 902 is caused to perform software processing according to the brightness system signal supplied from the brightness signal processor 840, and various settings, such as a flux range of the optical data DL and an exposure control process (including an electric shutter control), and The slope of the reference signal Vslop in the signal generator 27 changes the η/off timing of the various control pulses controlled by the divided frequency in the counter 254. The memory readout unit 907 stores (installs) the data read from the recording medium 924 to the RAM 906. The communication I/F 90 8 connects and transmits data between communication networks, such as the Internet. In this image pickup device 8, the drive controller 7 and the line processor 26 are displayed in a module separate from the pixel array unit 10. However, it is needless to say that, in the description of the solid-state image pickup device 1, it is possible to use the single crystal solid-state image pickup device 1, in which the drive controller 7 and the line processor 26 are integrated on the same semiconductor substrate, The pixel array unit 10 is also mounted therein, and the image pickup device 8 has an optical system, except for the pixel array unit 1 , the drive controller 7, the line processor 26, the reference signal generator 27, and the camera signal processor 810. Further, a photographic lens 082, an optical low-pass filter 804 or an infrared cut-off filter 805 are included, which are preferably formed into a module having an imaging function and including such components as a package. The solid-state imaging device 1 described above may be provided as a module having an imaging function, as shown, including a pixel array unit 1 (imaging unit) and a signal processor of the closely related pixel array unit 10 (except in the line processor) The side of the camera signal processing unit of the next stage includes a line processor 26 provided with an A/D conversion function and a credit (CDS) processing function as a package. The entire camera unit 8 can be provided as the other part of the signal processor of the next stage of the solid-state image pickup apparatus 1 in the form of a module by providing the camera signal processor 81. Alternatively, although not shown, the entire imaging device 8 can be integrated into the module-shaped solid-state imaging device 1 having an imaging function by the camera signal processor 81, wherein the pixel array unit 10 and the optical lens such as the imaging lens 802 The system is packaged together. Further, in the module of the solid-state image pickup device 1, a camera signal processor 810 corresponding to the camera signal processor 200 may be included. At this time, it is possible to think that the solid-state imaging device 1 and the imaging device 8 are identical. The camera device 8 is provided with a mobile device for performing, imaging, -106- 200845735 such as a camera or a mobile device having a camera function. In the present specification, "camera" is not only represented as a normal image captured by the camera, It can also be used for the detection of fingerprints. The imaging device 8 constructed as above includes the functions of all the aforementioned solid-state imaging devices 1, and the basic architecture and operation are made the same as those of the above-described solid-state imaging device 1. Therefore, in the imaging device 8, because of the weighting The addition can be performed to change the spatial position of the pixels after the addition. It is possible to complete a mechanism that achieves a higher resolution than performing simple addition on all uniform coefficients. For example, causing a computer to perform the above processing The program is distributed using a recording medium such as a flash memory, a 1C card, or a non-volatile semiconductor memory card such as a micro card. Further, the program can be downloaded or updated via a communication network such as an Internet routing server. It is possible to store part of the processing or all functions of the solid-state image pickup device 1 described in the embodiments ( There is a function for performing high-speed A/D conversion processing, in which the slope change control of the reference signal Vslop and the shift control of the counter frequency division operation are performed in cooperation with each other) in a 1C card or a semiconductor memory such as a micro card, An example of the recording medium 924. Therefore, it is possible to provide a program or a recording medium storing the program. Similar to the processing of the high-speed A/D conversion described in the description of the solid-state image pickup device 1, for example, "I implement high-speed A/D conversion" The program, that is, the software installed in the RAM9 06 has a control pulse setting function for implementing high-speed A/D conversion to software, in which the slope change control of the reference signal Vslop and the speed change control of the counter division operation are matched with each other. -107- 200845735 The soft system reads 1 for RAM 906 and is executed by microprocessor 902. For example, microprocessor 902 performs control pulse setting processing to control selection based on programs stored in, for example, ROM 904 and RAM 906 of the recording medium. The operation of adding the column or row, the adjustment of the crossover speed of the counter and the adjustment (change) of the slope of the reference signal Vslop Therefore, it is possible to complete a function as a software for changing the spatial position of the added pixels to obtain a high-resolution image compared to all of the coefficients performing simple addition. In the embodiment, since the weighting 値 can be set in accordance with the selection operation of selecting the addition target pixel, the added pixel position can be adjusted by setting an appropriate weight 値 to minimize the degradation of the resolution. As a result, it is possible to obtain High-resolution images. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and variations may occur depending on design requirements and other factors, which are within the scope of the accompanying claims or their equivalents. [Related Applications] This application contains Japanese patent applications JP2007-008 1 04 and JP20 07-2 9 1 467, respectively, which were filed on January 17, 2007 and November 9, 2007, respectively. . BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a CMOS solid-state imaging device according to an embodiment of the present invention; FIG. 2 is a structural example of a unit pixel used in the solid-state imaging device of FIG. 1 and a driving unit, a driving control line, and a pixel battery Line connection between crystals; -108- 200845735 Figure 3 is a diagram showing an example of a connection interface beside the voltage comparator and the counting section; Figure 4 is a diagram showing a first architecture example of a counting execution unit; A diagram showing a second architecture example of the counting execution unit; FIG. ό is a timing diagram showing the signal acquisition addition processing, which is the basic operation of the row A/D circuit of the solid-state image pickup device shown in FIG. 1; For a timing diagram, the addition processing in parallel in the vertical direction of the A/D conversion processing operation is shown; FIG. 8A-8D is a diagram showing the digital addition processing of the counter in the vertical direction and the digital arithmetic unit Disadvantages of the digital addition processing in the horizontal direction; FIG. 9 is a timing chart (first example) showing the weighted phase in parallel in the vertical direction of the A/D conversion processing operation in the improved resolution method of the first embodiment Add processing Figure 10 is a timing chart (second example) showing the weighted addition processing in parallel in the vertical direction of the A/D conversion processing operation in the improved resolution method of the first embodiment; Figure 11 is a diagram, The function of the count clock switch in the resolution improvement method of the first embodiment is shown; FIGS. 12A to 12F are diagrams (first example), which are shown in the vertical direction and the horizontal direction in the resolution improvement method of the first embodiment. The addition operation is performed from the spoon f pixel configuration; Fig. 1 3 A to 1 3 F is a diagram (second example), showing the vertical direction and the horizontal direction in the resolution improvement method of the first embodiment. _ 丨乍 丨乍 f 象 - 109 - 200845735 prime configuration; Figs. 14A to 14F are diagrams (third example), showing the addition operation in the vertical direction and the horizontal direction in the resolution improvement method of the first embodiment Pixel configuration; FIG. 15 is a diagram showing an example of a mechanism for setting a weighted 任意 of an arbitrary integer; FIGS. 16A to 16F are diagrams showing "addition of ratios 3 to 1 + addition of ratios 1 to 3", Wherein the weighting 値 is set to "3"; Figures 17A to 17F are diagrams showing " Addition of Examples 4 to 1 + Addition of Ratios 1 to 4, where the weighting 値 is set to "4"; Figures 18A to 18C are diagrams showing a comparison processing time for shortening the single-slope integral A/D conversion system The method of FIG. 9 is a *time sequence diagram 'additional processing in the vertical direction of the A / D conversion processing, which is used in parallel to explain the second embodiment; FIG. 20 is a diagram showing the timing clock The switch is operated in the resolution improvement method of the second embodiment; Fig. 21 is a diagram showing the relationship between the slope change control of the reference signal and the frequency division speed control of the counter; Fig. 22 A to 22B are diagrams a third embodiment of a method for solving the digital addition processing in the vertical direction and the resolution reduction of the digital addition processing in the horizontal direction by the counter; and FIG. 23 is a diagram showing An architecture of an image pickup apparatus similar to a solid-state image pickup device is utilized. -110- 200845735 [Description of main component symbols] 1: Solid-state imaging device 3: unit pixel 5a: terminal 5b: terminal 5c: terminal 1 0: pixel array unit 1 2: horizontal scanning circuit 12a: horizontal decoder 12b: horizontal Drive unit 12c: control line 14: vertical scan circuit 14a: vertical decoder 14b: vertical drive unit 15: column control line 18: horizontal signal line 1 9: vertical signal line 20: communication/timing controller 23: clock Converter 24: Read Current Supply 25: Row A/D Circuit 26: Line Processor 27: Reference Signal Generator 27a: Digital Analog Converter - 111 200845735 2 8 : Output Circuit 29: Digital Arithmetic Unit 7: Drive Controller 2 5 2 : Voltage comparator 2 5 4 : Counter 256 : Data storage unit 2 5 8 : Switch 3 2 : Charge generator 3 4 : Read selection transistor 3 6 : Reset transistor 3 8 : Floating diffusion 40 : Vertical selection transistor 42 : Source follower amplification transistor 5 2 : Vertical selection line 5 5 : Transmission line 5 6 : Reset line 5 : Pixel signal generator 5 1 : Pixel line 242 : NMOS transistor 244 : Reference current Source 246: Current Generator 248: Source Line 5 02: Gate 5 04: Counting Line unit 200845735 510: flip-flop 5 1 2 : data holding unit 5 1 4 : counting mode switch 5 1 6 : counting clock switch 5 1 7 : counting clock line 5 1 8 : clock stop unit 8 = camera 924 : recording Media 802: Photographic lens 8 04: Optical low-pass filter 8 05: Infrared cut filter 8 1 〇: Camera signal processor 8 1 2: Filter group 820: Camera signal processor 8 22: Signal separator 8 3 0 Color Signal Processor 840: Brightness Signal Processor 860: Encoder 900: Camera Controller 902: Microprocessor 904: Read Only Memory 906: Random Access Memory 907: Memory Read Unit 908: Communication interface

Claims (1)

200845735 X. Patent Application No. 1 · A solid-state imaging device comprising: a comparator for sequentially comparing a predetermined level of an analog pixel signal obtained from a plurality of pixels with a reference signal, the reference signal being gradually changed and used Converting the predetermined level into digital data; a counter for performing a counting process in parallel with the predetermined processing in the comparator, and maintaining a count 値 to obtain a digital bit when the comparing process is completed Data, which is obtained by adding the majority of the pixel signals; and an addition spatial position adjustment unit for controlling the selection operation and phase of the selected spatial position of the majority of pixels processed in the comparator The ratio of time-weighted 値 is adjusted to adjust the spatial position of the added pixels. 2. The solid-state image pickup device according to claim 1, wherein the addition spatial position adjusts the ratio of the weighted 在 at the time of addition such that the space of each pixel after the addition The position systems are arranged at equal intervals. 3. The solid-state image pickup device according to claim 2, wherein the pixel is provided with a color filter for generating a color image, and the position adjustment unit is controlled to process white in the comparator. Choosing a selection operation of the spatial position of the plurality of pixels such that the pixels having the same color are added, and controlling the weighting of the ratio at the time of the addition such that the spatial position of each pixel is Arranged to be equally spaced. The solid-state image pickup device according to claim 1, wherein the addition spatial position adjustment unit changes a slope of the reference signal used in the comparator to "1 / L2 times", The ratio of the weighted 设定 set at the time of addition is as fast as "L2". 5. The solid-state image pickup device of claim 1, wherein the addition space position adjustment unit changes a speed of the frequency division operation in the counter to "L1" times faster to set at the time of the addition. The ratio of the weighted 値 is greater than "L1". 6. The solid-state image pickup device of claim 4, wherein the addition space adjustment unit changes the reference before the comparison processing of the predetermined level of some pixels in the comparator is completed. The slope of the signal is greater than J times' and the speed of the frequency division operation in the counter is changed to J times faster to keep the weighting of a certain pixel constant. The solid-state image pickup device according to claim 6, wherein the addition spatial position adjustment unit simultaneously changes the slope of the reference signal by J times, and controls the output of each bit in the counter. The change in speed of the frequency division operation. 8. The solid-state image pickup device according to any one of claims 5, 6 or 7, wherein: the counter is an asynchronous counter and has a chronograph clock switch disposed between each bit level 'switching an input clock signal' and the addition space position adjusting unit controls the count clock switch 'to transmit a clock signal input to each bit as a high order bit when the speed of the frequency dividing operation is changed The solid-state image pickup device according to claim 1, wherein the counter is in a first predetermined level when processing a pixel signal of a certain pixel, the following number mode or number One of the modes, performing a counting process and maintaining a count 时 when the comparison process is completed in the comparator, and by using the held count when processing a second predetermined level of the pixel signal of the same pixel値 as a starting point, performing the counting process in the lower mode or another mode of the upper mode and maintaining the count when the comparison process is completed in the comparator値The solid-state image pickup device according to claim 9, wherein the counter maintains a count 値 at the completion of the comparison processing of the second predetermined level of the pixel signal of the certain pixel, and is the next pixel When the first predetermined level of the pixel signal is compared with the second predetermined level, the counter is held in the counter by using the same manner as the counting mode of the pixel signal of the certain pixel The count 値 is used as a starting point, and the counting process is performed to obtain digital data indicating one of the 値 obtained by adding the majority of the pixel signals. A solid-state image pickup device according to claim 1, wherein a plurality of the aforementioned comparators use the common reference signal, and the comparison processing is performed in parallel with the pixel signal to be processed for each comparator. 12. A camera device comprising: a comparator for sequentially comparing a predetermined level of an analog pixel signal obtained from a plurality of pixels with a reference signal, the reference signal being gradually changed and used to Pre-positioning is quasi-converted into digital data; a counter is used for parallel processing of the -116-200845735 comparison processing of the predetermined level in the comparator, performing a counting process 'and maintaining the count when the comparison processing is completed, Obtaining digital data indicating that the majority of the pixel signals are added; and an adding spatial position adjusting unit for controlling a selection operation of the spatial position of the majority of pixels processed in the comparator and The ratio of the weighted 値 of the time is added to adjust the spatial position of the added pixels; and a controller for controlling the generation of a control signal for controlling the added spatial position adjusting unit. -117-