200823582 九、發明說明： 【發明所屬之技術領域】 本發明涉及一種液晶顯示裝置，尤其涉及一種用於笼曰 、 從晶顯不（LCD) 裝置上的陣列基板以及製造此陣列基板的方法。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an array substrate for use in a cage, a crystal display (LCD) device, and a method of fabricating the same. [Prior Art]
液晶顯示（LCD)裝置基於液晶材料光學各向異性和的偏極化特性而 驅動。液晶分子具有-長形狀，並且此液晶分子在—對準方向中規 則地配置。光沿著此液晶分子的長而薄的形狀藉由LCD裝置。此液s八子 的對準取決祕加於此晶分子電場_度或方向。藉由酬此^場刀的 強度或方向，此液晶分子的配向改變，且顯示影像。絲矩陣式液晶顯示 (AMLCD)裝置，其包括用於複數個像素上的作為切換裝置的薄膜電晶 體’由於可以高解析度和具有顯示快速義影像輸力，這種液晶顯 示裝置已經被廣泛使用。 通常’ - LCD裝置包括兩撇此分離並韻基板，以及插入此兩 個基板之間的-液晶層。各基板包括一電極。來自各自基板上喊極彼此 ^對。精由在每-個電極上施加-電壓因此在電極之間感應—電場。液晶 分子的對準方向依據此電場的強度或方向的變化而改變。此電場方向垂直 =基板。此LCD裝置具有相對高的透射與—高的高寬比。然而，此lcd 裝置:以財-窄視角。為了增大該視角，已經提出各種模式。在這些廣 視角杈式中，以下參考圖式說明習知技術之一平面内切換（ips)模式^^^ 第1圖為習知技術中一 IPS模式LCD裝置之概要橫截面圖。如同第i f中所示，此根據習知技術中的ips模式LCD裝置包括：一下基板忉和 —上基板40，以及設置於下基板1〇和上基板4〇之間的一液晶層lc。—薄 膜電晶體τ 一共同電極30、以及一像素電極32形成在此下基板1〇上的 各像^内。此薄膜電晶體T包括··-閘極電極14、-半導體層18、以及 源極電極20和汲極電極22。此半導體f 18設置在此閘極電極14之上，而 具有-閘極絕緣層16在半導體層18和閘極電極14之間。此源極電極 200823582 和此没極電極22形成在此半導體層18上並彼此分離一段距離。各共同電 極30和此像素包極32包括複數個圖案。此共同電極3〇和此像素電極& 彼此交替的分開。 —雖然在第1圖甲並未顯*，一閘極線沿此像素p的一第一邊形成，而 -貧料線沿此像素的-第二邊形成，該第二邊完全與此第—邊垂直。一共 同線進-步在此下基板10上形成。此共同線將電壓提供給共同電極3〇。 此上基板40與此下基板1〇彼此分開。一黑色矩陣幻和一包含紅色濾 光片34a和綠色濾光片34b的濾色層，形成在此上基板4_一内表面上: 此濾色層更包括-藍色濾光片（未顯示）。此黑色矩陣42設置在：此間極Liquid crystal display (LCD) devices are driven based on the optical anisotropy and polarization characteristics of liquid crystal materials. The liquid crystal molecules have a - long shape, and the liquid crystal molecules are regularly arranged in the - alignment direction. The light is along the long and thin shape of the liquid crystal molecules by the LCD device. The alignment of this liquid s eight is determined by the electric field _ degree or direction of the crystal molecule. By adjusting the intensity or direction of the field knife, the alignment of the liquid crystal molecules changes and an image is displayed. A wire matrix liquid crystal display (AMLCD) device including a thin film transistor as a switching device for a plurality of pixels. This liquid crystal display device has been widely used because of its high resolution and display fast image transmission power. . Typically, the LCD device includes two separate substrates, and a liquid crystal layer interposed between the two substrates. Each substrate includes an electrode. Shouting from each other on the opposite substrate. The precision is applied by applying a voltage across each of the electrodes to induce an electric field between the electrodes. The alignment direction of the liquid crystal molecules changes depending on the intensity or direction of the electric field. This electric field direction is vertical = substrate. This LCD device has a relatively high transmission and a high aspect ratio. However, this lcd device: a rich-narrow perspective. In order to increase this angle of view, various modes have been proposed. In these wide viewing angles, an in-plane switching (ips) mode of the prior art is described below with reference to the drawings. Fig. 1 is a schematic cross-sectional view of an IPS mode LCD device in the prior art. As shown in the i f, the ips mode LCD device according to the prior art includes a lower substrate and an upper substrate 40, and a liquid crystal layer lc disposed between the lower substrate 1 and the upper substrate 4A. - Thin film transistor τ A common electrode 30, and a pixel electrode 32 are formed in the respective images on the lower substrate 1''. The thin film transistor T includes a gate electrode 14, a semiconductor layer 18, and a source electrode 20 and a drain electrode 22. The semiconductor f 18 is disposed over the gate electrode 14 and has a gate insulating layer 16 between the semiconductor layer 18 and the gate electrode 14. The source electrode 200823582 and the electrodeless electrode 22 are formed on the semiconductor layer 18 and separated from each other by a distance. Each common electrode 30 and the pixel envelope 32 comprise a plurality of patterns. This common electrode 3〇 and this pixel electrode & are alternately separated from each other. - although not shown in Figure 1, a gate line is formed along a first side of the pixel p, and a - lean line is formed along the second side of the pixel, the second side being completely identical to this - Side vertical. A common line advance step is formed on the lower substrate 10. This common line supplies a voltage to the common electrode 3〇. The upper substrate 40 and the lower substrate 1 are separated from each other. A black matrix phantom and a color filter layer including a red color filter 34a and a green color filter 34b are formed on the inner surface of the upper substrate 4: the color filter layer further includes a blue color filter (not shown) ). This black matrix 42 is set at: this pole
、、泉、此資料線和、此薄膜電晶體丁上。此濾色層3如和灿各設置在各自 像素P中。 . ϋ 此下基板10,包括：此薄膜電晶體τ、此共同電極30、以及此像素電 極32，該基板可以稱為一陣列基板。此液晶層LC驗晶分子被施加在此 共同電極30和此像素電極32之間所感應之一水平電場45而驅動。此包含 黑色矩陣=2和濾色層34a和3扑的上基板4〇可以稱為一遽色基板。 現=考第2圖說明習知技術中之用於—lps模式LCD裝置的陣列基 板。更特定而言，第2圖為習知技術中說明經由4群過程所製造一用於 IPS核式LCD裝置的-陣列基板的概要平面圖示。如第2圖所示，一間極 ，54沿一在一絕緣基板5〇上的方向形成。一資料線％與此間極線％相 父二因此界定出-像素區域P。一閘極墊56在此閘極線54的一端形成，而且 Z料塾94在此資料_的―端形成。—共同線58與此_線54彼此 刀開亚平行。此共同、線58設置在沿此像素區域p的一邊。—閑極塾端子 =开y成在此閑極墊56並接觸此陳墊56。—資料塾端子加形成在此資 料墊94上並與之接觸。 、 二薄膜電晶體τ形成在鄰近此閘極線54與此資料線％相交的位置。 此^膜電晶體τ包括：-閘極電極52、—主動層84、—歐姆接觸層（未顯 =)、以及源極電極88和沒極電極9〇。此閘極電極52與此閘極線％連接。 動層84和此區人姆接觸層依序設置在此閘極電極&上。此源極電極沾 4及極電極90設置在此歐姆接觸層上。此源極電極挞與此資料線％連 200823582 接本貝非晶發圖案72設置在此資料線92下面。此没極電極9〇與此源 極電極88分開。 一像素電極PXL和-制修VeGm形絲此像素輯p内。此像素 電極PXL與歧極電極％ ，並且此共同電㈣議與此頻線兄接 觸。此像素電極PXL和此共同電極Vcom彼此分開。 此根據習知技術用於-ips模式LCD裝置之陣列基板中，此源極電極 88和及極电極90，此貢料線92和此主動層84經由相同過程形成。因此， 此主動層84、此源極電極88、以及汲極電極9〇、此本質非晶石夕圖案72、 以及資料'線92依序形成層，其中，主動層μ和本質非晶石夕圖案72曝露於 源極電極88、汲極電極90、以及資料線92之側。 在此處，此主動層84和此本質非晶矽圖案72進行曝光，以致於在其 中可以產生光電流。主動層84中之光電流視為漏電電流，當薄膜電晶體丁 關閉_時可以流經，且導致薄膜電晶體T不正確操作。在本專質二二 案72内的光電流造成與其相鄰近的電極之間之耦合，由於此耦合液晶分子 (未顯示）不適當地配置。因此，在所顯示之影像中會產生一波浪雜訊。 此溥膜電晶體T内的擊穿電流和波浪雜訊的出現，都是Lcd裝置中典型性 發生的現象，其中LCD裝置中的源極電極，汲極電極和主動層經由相同過 程圖案化。 第3A至3H圖、第4A至4H圖、第5A至5H圖、以及第6A至6H[圖 說明習知技術中製造用於IPS模式LCD裝置的陣列基板的過程。第从至 3H圖為第2圖中沿線II-II的橫截面圖。第4A至4H圖為第2圖中沿線ΠΙ-ΙΙΙ 的橫截面圖。·第5A至5H圖為第2圖中沿線rv_iV的橫截面圖。第6A至 6H圖為第2圖中沿線V-V的橫截面圖。 第3A圖、第4A圖、第5A圖、以及第6A圖顯示一第一遮罩過程。如 同於第3A圖、第4A圖、第5A圖、以及第6A圖中所示，一切換區域s， 一像素區域P、一閘區域G、一資料區域D、以及一共同信號區域cs都界 定在一基板50上。第2圖的一閘極線54和一閘極電極52都形成在包含區 域S、P、G、D、以及CS的基板50上。此閘極線54設置在此間區域〇内 .並沿一第一方向延伸。此閘極線54包括在其一端的一閘極墊56。此閘極電 200823582 極52與此2極線54連接並設置在切換區域s中。同時，一共同線％形成 在此共同信號區域CS内。此共同線58與此閘極線54平行並分開。 此閘極線54、此閘極墊56、此閘極電極52、以及此共同線58都可以 藉由沉積-個或多個導電金屬材料而形成，該材料可以包括銘⑷） 、鈥化 鋁（AINd)、鎢（w)、鉻（Cr)、以及鉬（Mo)。此閘極線54，此閘極墊 56，此閘極電極52和此共同線58可以為上述金屬材料的一單一層或可以 為銘（A1) /鉻（c〇或鋁（A1) /銦（M〇)的雙層。 、第3B至3F圖、第4B至4F圖、第56至5?圖、以及第63至6卩圖 為一第二遮罩過程。如同在第3B至3F圖、第4B至4F圖、第5B至π圖、 以及第6B至证圖中所示，一閘極絕緣層6〇、一本質非晶石夕層（a··) 62、 ‘貝掺雜非晶矽層（n+或p+a-SkH) 64、以及一導電金屬層66都形 成在基板50的整個表面之上，包括此閘極線54、此閘極墊％、此閘極電 ； 極52、以及此共同線58。此閘極絕緣層60藉由沉積由無機絕緣材料組所 . 選出一個或多個材料形成，此組包含：氮化矽（SiNx)和氧化矽（Si〇2)。 • 此導電金屬層66藉由沉積一個或多個材料形成，該材料來自上述導電金屬 材料組。 一光阻層68藉由在基板5〇的整個表面塗佈而形成，包含具有光阻的 導電金屬層66。一遮罩M設置在此光阻層68之上。此遮罩μ包括：一光 透射部份Β1、一光阻擋部份Β2、以及一光半透射部份63。此光透射部份 • Β1完全將光透射。此光阻層68在此光透射部份31的下面整體地曝光因此 發生化學變化。此光阻擋部份犯完全將光遮罩。此光半透射部份Β3包括 狹縫或一半透明層，因此降低光的強度或光的透射。因此，此光阻層藉由 此光半透射部份Β3進行部分曝光。 曰 此光半透射部份Β3設置在切換區域S内的閘極電極52之上。此光阻 擋部伤Β2设置在切換區域§和資料區域d内的光阻層68之上。在切換區 域S内，此光阻擋部#Β2設置在此光半透射部份83的兩側。此光透射部 份Β1設置在除了切換區域§之外的其他區域内以及資料區域〇内。此光 阻層68藉由遮罩Μ進行曝露於光線然後顯影。 參考第3C圖、第4C圖、第5C圖、以及第6C圖，第一和第二光阻圖 200823582 木70a和70b都分別形成在切換區域§内和資料區 案=有與此_極52對應的+部分和與不包括二極= 刀換區域S相對應的—第二部分。此第二部分比第—部分要厚。、 6』==，66、此雜f摻雜_層64、和此本質非晶石夕層 k擇性地猎由將弟一和第二光阻圖案了加和了㈨ 除。此導電金屬層66根據此導電金屬層6材 二^科 同時去除。€者墓 州丁叶m與下層64和62 得叫本綱。錢，《«雜非晶 斤如=於第30、41)、5；〇、以及61)圖中所示， 17S ^ g 80 „ "匕弟一至屬圖案82下。各第一 … -本質非晶侧72和一雜質摻雜非晶石夕圖宰 1體圖木《 如同於第3E、4E、5E、以芬π㈤山 此第-光阻圖案7〇a的與此閘極電極^2董=二執仃一拋光過程因此去除 電極52對應的此第一金屬圖案7^應^-第—部分，並且與此閘極 和此第二光阻圖請的另外的部分亦;:去=第 ，^在此第一和第二光阻圖案7〇a和7刀%去的除^八一和•弟二金屬圖案 曝路的第一金屬圖案78與此第一丰導轉 …达"卩刀弘路。^後，將所 除。 ¥體層76的雜質摻雜非晶石夕圖案74去 參考第3F、第仲、第犴、以及 電極90和一資料線92。此資料線％ 固’★形成一源極電極88, 一汲極 -資料墊94形成在此資料線％的_端方向相交之第二方向中。 的本質非晶矽圖案72在此閘極電極&弟犯圖中的第一半導體圖案76 圖中的第一半導體圖案76的雜“= 乍用為層84，以及第3E 分，作為一歐姆接觸層86。當此第犯^曰夕圖案74，其現在被分成兩部 雜非晶矽圖案74被部分地去^時昂E圖%中的第一半導體圖案76的雜質摻 過度蝕刻，以致於此等粒子可以質非晶矽圖案、即此主動層84，被 去除此光阻圖案70a和70b。 刀保留在此主動層84的表面上。其次， 10 200823582 a G 5G以及6G圖為-第三遮罩過程。如同於第3G、4G、 化以=6G圖中所示，一鈍化層％實質上形成在基板5〇的整個表面上， ^鈍化1^祕雜％、以及包含雜墊94的簡線92。 緣材料^由'讀—錢絕騎料崎選擇之—而形成，該無麟 芦96可上^ (舰）和二氧化矽（Si〇2)。以替代方式，此鈍化 二:错由在基板5〇上塗佈一由有機絕緣材料組所選擇之—而形成， 該有機材料組包括苯環丁烯⑽）和丙烯酸樹脂。擇而減 ㈣’將純化層％圖案化’以形成：一汲極接觸孔98a、—共同線接 孔98c、以及一資料塾接觸孔98d。此及極接觸孔 此問。此共同線接觸孔娜部分曝露此共同線58。 此i料墊94 /撕部分曝露此閘極塾％。此資料塾接觸孔親部分曝露 5H、、以及6H醜示""第四遮罩過程。如同於第3H、册、 包含鈍❹96 —像錢極现和—朗電歸_藉由沉積在 、也化層％的基板65〇上的一透明導電金屬材料組所之 銦中形成該透明導電金屬材料組包括：氧化錫錮⑽）和氧化鋅 極90接觸’ 金屬材料圖案化。此像素電極PXL與此沒極電 和並同電ΐ Γ都勺Γ嶋與此共同線58接觸。每—個像素電極pxl 盘像素電極PxH 圖案與資料線92平行。此共同電極v_ isPYT ^ 父曰。一閘極墊端子GP#〇一資料塾端子Dp與此像辛電 電極VGGm同軸。此職墊端子GP與此瞧56接ς 此貝枓墊端子DP與此資料墊94接觸。 接觸 因為ΙίΠ模式仰|置的_基板可以藉由上述四個遮罩過程製成。 而此;二第二半導體圖案8。形成在此資料㈣下， 一千岭體圖案8〇的本質 h所^ ^ 貝井日日矽圖木72在此貧料線92之側曝露。如 = f非~_72受至細影響，導致所顯示在影像ΐ 此主騎84也柳了此藤電極a並曝露在光線。 200823582 因此 ，在主動I 84内發生的光電流’其造成薄膜電晶體不正確地操作 【發明内容】 ^此’本發_實_主要針_於平面内職模式液晶顯示裝置的 陣列基板以及製細車細賴雜，其實肚可以 與缺點所產生-個或更彡侧題。 不 本發明的實施例的-個目的是提供―種祕平面_換模 顯 以 裝置的陣聽板以及轉聽板賴造方法，賊可㈣電流最：、 及可以避免在所顯示影像上之波浪雜訊。 陣列目的是提供—觀於平面_換模式液晶顯示裝置的 陣歹^板^及此_基板㈣造方法，其可叫低製造成本和時間。 、皆於本發卿外的特性與優點將在以下說明中描述，1 ==所;=由:施本發明·。本發明的目 搆而實=7寫㈣，專_、似___出之结 t了貝現本法發明的這些或其他優點和目的，如 ==;:上的_、一動二的 接在此祕和ϋΓ 在此絲雜和制電極之間與直 上界定出-婦_、⑼顯稀置的方法，此基板 該方法包括··在切^㈣素區域、—資料區域、以及-共同信號區域， 信號區域内形成—共2内喊具有i極電極的閘極線，以及在此共同 至少-部分巾形二在切換區域與在像素區域中之綱極絕緣層之 乂 Ψ錢緣層，—麵層以及—歐姆接觸層，藉由產生 與以下詳細說明為岭=之間的—鈍化層。應瞭解’以上—般性說明， 在另-方面了 兄明’其用意在於提供所主張本發明進-步解 12 200823582 源極祕和祕電極，形成與此源極電性 .曰之上域 在源極電極祕極電極之間姑的此_絕緣層與 第-用於液晶顯示裝置的陣列基板的方法包括：藉由一 ;pm': 1板上械—閘極電極和—閘極線’在此具有閘極電極 板泉的基板上藉由一第二遮罩過程依序形成一閘極絕緣層、一主動 ί二Γ接觸f、以及—龍線，藉轉三遮罩過程在此基板上形成一 極、—共同電極、以及—像素電極，以及在此共同電 爲。D素電極之間與在祕雜和汲極雜之間的主騎上形成一純化 環0 立應瞭解，本發明以上一般性說明與以下詳細說明為典範與說明，其用 思在於提供所主張本發明實施例進一步解釋。 【實施方式】 此等所附圖式其包括於此以提供本發明進一步瞭解，且構成本說明書 之一部份、而用於其用於說明本發明之實施例，其與此說明一起用於解^ 本發明之原理。 現在詳細說明本發明之實施例，而在所附圖中說明其例。 本發明實施例中，藉由三個遮罩過程製造出陣列基板，其中，一島形 主動層形成在一閘極電極之上，因此此主動層的源極端和没極端並不曝霖 在背光下。因為此主動層的源極端和汲極端並不曝露於來自背光之光線， 所以在主動層中不會產生光電流。因此，就可以防止波浪雜訊。 第7圖為根據本發明第一實施例用於IPS模式LCD裝置的陣列基板的 平面圖。第8A至8D圖根據本發明第一實施例用於IPS模式LCD裝置的陣 列基板之橫截面圖。第8A圖與第7圖中的線VII-VII相對應，第8B圖與 第7圖中的線νιπ—νπ〗相對應，第8C圖與第7圖中的線DMX相對應，以 及第8D圖與第7圖中的線χ-χ相對應。 13 200823582 /如同第7圖和第SA至SD圖中所示，在一絕緣基板1〇〇上沿一第一方 向形^閘極線104，並且沿-第二方向形成一資料線143。此閘極線1〇4 和此貝料線143彼此相父因此界定出像素區域p。在此閘極線1〇4的一端形 閘極墊1G6，而在-資料覆蓋線142的_端形成—資料墊端子146，該 貝料復盍線142覆盍此貢料線143。一資料墊144在此資料線143的一端。 -共同線109和-共同電極連接部分刚與此閘極線1〇4彼此分開一段距 離。此共同線109和此共同.電極連接部分1〇8與此閘極線1〇4平行並設置 在此像素區域p的相對侧。-閘極墊端子152覆蓋此閘極墊1〇6。 在此閘極、線104與此資料線143相交的位置鄰近處形成一薄膜電晶體 τ。此薄膜電晶體τ包括：-閘極電極搬、一在此閘極電極1〇2上的閘極 絕緣層11〇、一在此閘極絕緣層110上的主動層124、在此主動層124上的 歐姆接觸層126、在此接觸層上的緩衝器金屬層128、—祕電極138、以 及在此緩衝益金屬層128上的沒極電極14{)。此閘極電極搬與此間極線 刚連接。此主動層I24為-島形並形成在一閘極電極之上，以致於該主動 層的源極端和錄端不會延伸超過下面閘極電極搬周圍所界定的邊界。 此歐姆接觸層⑶和此緩衝器金屬層⑶依序設置在此主動層124上。每 -個緩衝ϋ金屬層U8都與此歐姆接觸層120接觸，並且分別與源極電極 138和汲極電極140接觸。此源極電極138與資料覆蓋線142連接，而此汲 極包極140與此源極電極138分開。一閘極絕緣層η〇覆蓋此間極線刚、 此閘極電極102、以及此閘極墊1〇6。 在此處，此資料線143、此缓衝器金屬層128、此歐姆接觸層126、以 及此主動層I24藉由同-遮罩過程而形成，而在此資料線143和此資料塾 144下面存在一延伸部分β。此延伸部分Β包括:依序成層之圖案、且各設 置於與歐姆接觸層126和主動層124相同層上。因此，此延伸部分β 與歐姆接觸層126和主動層124實質上相同的結構。 /、 此緩衝器金屬層128、此資料線…以及此資料墊⑷可以具有至少 三層依序成層之多層結構，例如：鈦化翻（M〇Ti)合金、銅㈣和欽化 鉬（ΜοΤι)合金。此源極電極和汲極電極138和14〇 以及此資料_子146,由歸合金縣。 14 200823582 數m時’由於電線阻抗最小化而導致信號延遲。 象素區或P中形成一像素電極148和電帝 148與此没極電極140電性連 、』包才150此像素包極 接。每-個像素電極148和二茗;;==°與此共同線-電性連 杳枓綠143承一μ主…、门包極15〇都包括複數個圖案，這些電極與 辛恭i 148自二音〜電極148的圖案與共同極150的圖案交替。此像 二 接部分施延伸，並姐極電極138連接。此 共同電極連接部分⑽接觸。_在圖中並未顯示，此共 i二電極與共同線1〇9連接，並將來自共同線109的信號提供 二H、币” ’此共同_150與鄰近的一像素區域内的-共同電 不）雛連接。以替代方式，此共同電極150可喊接盘此t =09連接。此像素電極連接部分施與此共⑻重疊，咖开錢一 ==Γ。此像素電極148和共㈣極15G藉由與源極電極138和沒極 %極140相同的形成過程而形成。此像素 Μ〇Ή合金形成。 成此像素电極148和共同電極15〇可以由 主靜154形成於：源極電極138和汲極電極140之間所曝露的此 芦/ίο 電極148科同電極15G之間所的閘極絕緣 層層110上。因此，此鈍化層154直接在像素電極148和共同電極15〇之 間^鈍化層154圍繞此閘極塾端子152和龍墊端子146。此聽層154 可以藉由沉積和剝離(Lift-Off)過程形成而不用額外的遮罩過程。因為』主動 層124不曝光，因為主動層的源極端和沒極端都不延伸超過下面問極電極 界定的邊界外’可簡免由於漏電流所引起之細電晶體的波浪雜訊、或 不正確操作。 / 以下參考第9A至91圖、第10A至1〇1圖、第11A至m圖、以及第 12A至121圖說明：根據本發明第一實施例製造陣列基板之方法。第9八至 91圖為沿著第7圖中VII-VII線之横截面圖。第1〇A至1〇1圖為沿著第7圖 中Vm-VIII線之橫截面圖。第11A至111圖為沿著第7圖巾Ιχ_ιχ線之橫 截面圖。第12Α至121圖為沿著第7圖中Χ-Χ線之橫截面圖。 八 10A、11A、以及12A圖中所示，一切換區域S、一像素區域p、一閑區域 15 200823582 G、一資料區域D、以及一共同信號區域CS都界定在一基板100上。一第 一導電金屬層（未顯示）藉由沉積一導電金屬而形成在基板1〇〇上，在此 基板上界定S、P、G、D以及CS區域，此金屬材料由導電金屬組之一個或 多個材料之導電金屬所形成:鋁（A1)、鈥化鋁合金（AINd)、鉻（Cr).、鉬 (Mo)、鎢（W)、錫（Ti)、銅（〇〇、以及钽(^)。此第一導電金屬層藉 由一第一遮罩過程進行圖案化，因此形成一閘極電極1〇2、第7圖之一閘極 線104、以及一閘極墊106。此閘極電極1〇2設置在切換區域s内，而此閘 極線104和此閘極墊106設置在此閘區域G内。此閘極墊1〇6形成在此閘 極線104的一端。同時，第7圖的一共同線、與一共同電極連接部分108 形成在基板100上。此共同線109和共同電極連接部分1〇8與閘極線1〇4 平行並設置在像素區域P的相對側。 第9B至9F圖、第10B至10F圖、第11B至11F圖、以及第12B至 12F圖痛示一弟一遮罩過程。如同第9B至9F圖、第10B至i〇f圖、第UB 至11F圖、以及第12B至12F圖中所示，一閘極絕緣層11〇、一本質非晶 石夕層（a-Si.H) 112、一雜質摻雜非晶石夕層（例如，n+ n4、以及一 第二導電金屬層116，依序形成在基板1〇〇的表面上，此基板包括：此閘極 電極102、第7圖中的此閘極線104、此閘極墊1〇6、第7圖中的此共同線 109、以及此共同電極接觸部分108。藉由以光阻塗佈基板1〇〇，而在第二 導電金屬層II6上形成一光阻層118。 此閘極絶緣層110可以藉由沉積一無機絕緣材料而形成，該材料由無 機絕緣材料組之:或更多材料所構成，其包括：氮化秒（斷）和氧化石夕 (Sl〇2) °此第—$電金屬I 116可以為多層結構。例如，此第二導電金屬 層116可以包括：第-層的鈦化翻合金、第二層的銅、以及第三層的鈦化 鉬合金。此銅具有相對低的電阻絲，而一銅線可以信號延遲最小化。順 便提及，銅可以輕易地與石夕或氧化物起反應，因此增大了電線的電組。為 了避免這個問題，在銅層的上下各形成鈦化鉬合金層。 -遮罩Μ設置在光阻層118之上。此遮罩M為—半色調遮罩和一繞 射遮罩。此遮罩Μ包括：一光透射部份β1、一光阻擔部份b2、以及光半 透射部份B3。此光阻擋部份B2對應於此切換區域s和資料區域d。此光 16 200823582 透射部份B1對應於:用於閘極墊106之閘區域G，與共同信號區域cs。此 光半透射部份B3對應於:除了切換區域S、資料區域D、用於閘極墊1〇6的 閘區域G、和共同信號區域CS之外的其他區域。與切換區域s對應的此光 阻擋部份B2的尺寸並不比閘極電極102大。其次，此光阻層118藉由遮罩 Μ曝光以及然後顯影。 參考第9C、10C、11C、以及12C圖，在將第9Β、10Β、11Β、以及, spring, this data line and this thin film transistor. This color filter layer 3 is disposed in each pixel P as it is. The lower substrate 10 includes: the thin film transistor τ, the common electrode 30, and the pixel electrode 32, and the substrate may be referred to as an array substrate. This liquid crystal layer LC crystallized molecule is driven by a horizontal electric field 45 induced between the common electrode 30 and the pixel electrode 32. The upper substrate 4, which includes the black matrix = 2 and the color filter layers 34a and 3, may be referred to as a color substrate. Now, Fig. 2 illustrates an array substrate for an lps mode LCD device in the prior art. More specifically, Fig. 2 is a schematic plan view showing an array substrate for an IPS nuclear-type LCD device manufactured by a 4-group process in the prior art. As shown in Fig. 2, a pole 54 is formed along a direction on an insulating substrate 5''. A data line % is associated with this pole line %. The parent 2 thus defines the - pixel area P. A gate pad 56 is formed at one end of the gate line 54, and the Z magazine 94 is formed at the end of the data sheet. - The common line 58 and the _ line 54 are parallel to each other. This common line 58 is disposed along one side of this pixel area p. - Idle terminal = = y is formed here to contact the pad 56 and contact the pad 56. - Data 塾 terminals are added to and in contact with this data pad 94. The second thin film transistor τ is formed adjacent to the gate line 54 at a position intersecting the data line %. The film transistor τ includes: a gate electrode 52, an active layer 84, an ohmic contact layer (not shown), and a source electrode 88 and a gate electrode 9A. This gate electrode 52 is connected to this gate line %. The movable layer 84 and the contact layer of the region are sequentially disposed on the gate electrode & The source electrode 4 and the electrode electrode 90 are disposed on the ohmic contact layer. The source electrode 挞 is connected to the data line %. 200823582 The local amorphous pattern 72 is disposed under the data line 92. This electrodeless electrode 9 is separated from this source electrode 88. A pixel electrode PXL and a repaired VeGm-shaped wire are in this pixel series p. The pixel electrode PXL and the parapolar electrode %, and the common electric (4) is in contact with the frequency line brother. This pixel electrode PXL and this common electrode Vcom are separated from each other. This is used in an array substrate of an -ips mode LCD device according to the prior art, the source electrode 88 and the electrode electrode 90, and the tributary line 92 and the active layer 84 are formed through the same process. Therefore, the active layer 84, the source electrode 88, and the drain electrode 9〇, the intrinsic amorphous slab pattern 72, and the material 'line 92 are sequentially formed into layers, wherein the active layer μ and the amorphous austenite The pattern 72 is exposed on the side of the source electrode 88, the drain electrode 90, and the data line 92. Here, the active layer 84 and the intrinsic amorphous germanium pattern 72 are exposed so that a photocurrent can be generated therein. The photocurrent in the active layer 84 is considered to be a leakage current, which can flow when the thin film transistor is turned off, and causes the thin film transistor T to operate incorrectly. The photocurrent in this specialty 22 case causes a coupling between the electrodes adjacent thereto, since the coupled liquid crystal molecules (not shown) are improperly configured. Therefore, a wave of noise is generated in the displayed image. The breakdown current and the appearance of wave noise in the enamel transistor T are typical phenomena occurring in the Lcd device in which the source electrode, the drain electrode and the active layer in the LCD device are patterned via the same process. 3A to 3H, 4A to 4H, 5A to 5H, and 6A to 6H [Fig. illustrates a process of manufacturing an array substrate for an IPS mode LCD device in the prior art. The first to third figures are cross-sectional views along line II-II in Fig. 2. 4A to 4H are cross-sectional views along the line ΠΙ-ΙΙΙ in Fig. 2. - Figures 5A to 5H are cross-sectional views along line rv_iV in Fig. 2. 6A to 6H are cross-sectional views along line V-V in Fig. 2. 3A, 4A, 5A, and 6A show a first masking process. As shown in FIG. 3A, FIG. 4A, FIG. 5A, and FIG. 6A, a switching region s, a pixel region P, a gate region G, a data region D, and a common signal region cs are defined. On a substrate 50. A gate line 54 and a gate electrode 52 of Fig. 2 are formed on the substrate 50 including the regions S, P, G, D, and CS. The gate line 54 is disposed in the region 〇 and extends in a first direction. This gate line 54 includes a gate pad 56 at one end thereof. This gate pole 200823582 is connected to the pole line 54 and is disposed in the switching region s. At the same time, a common line % is formed in this common signal area CS. This common line 58 is parallel and separate from this gate line 54. The gate line 54, the gate pad 56, the gate electrode 52, and the common line 58 may be formed by depositing one or more conductive metal materials, which may include Ming (4)), aluminum telluride. (AINd), tungsten (w), chromium (Cr), and molybdenum (Mo). The gate line 54, the gate pad 56, the gate electrode 52 and the common line 58 may be a single layer of the above metal material or may be Ming (A1) / Chromium (c〇 or aluminum (A1) / indium The double layer of (M〇), the 3B to 3F, the 4B to 4F, the 56th to 5th, and the 63rd to 6th are a second mask process, as in the 3B to 3F 4B to 4F, 5B to π, and 6B to the figure, a gate insulating layer 6〇, an intrinsic amorphous layer (a··) 62, and a doped doping A germanium layer (n+ or p+a-SkH) 64 and a conductive metal layer 66 are formed over the entire surface of the substrate 50, including the gate line 54, the gate pad %, and the gate electrode; 52, and the common line 58. The gate insulating layer 60 is formed by depositing one or more materials selected from the group consisting of inorganic insulating materials, the group comprising: tantalum nitride (SiNx) and yttrium oxide (Si〇2) • The conductive metal layer 66 is formed by depositing one or more materials from the group of conductive metal materials described above. A photoresist layer 68 is formed by coating the entire surface of the substrate 5, including photoresist. A conductive metal layer 66. A mask M is disposed on the photoresist layer 68. The mask μ includes a light transmissive portion Β1, a light blocking portion Β2, and a light semi-transmissive portion 63. The transmissive portion • Β 1 completely transmits light. The photoresist layer 68 is integrally exposed under the light transmissive portion 31 so that a chemical change occurs. This light blocking portion completely shields the light. The crucible 3 includes a slit or a semi-transparent layer, thereby reducing the intensity of light or the transmission of light. Therefore, the photoresist layer is partially exposed by the semi-transmissive portion 3 of the light. The semi-transmissive portion of the light is disposed in the switching region. Above the gate electrode 52 in S. The light blocking portion 2 is disposed above the photoresist layer 68 in the switching region § and the data region d. In the switching region S, the light blocking portion #Β2 is disposed in the light Both sides of the semi-transmissive portion 83. The light transmitting portion Β1 is disposed in a region other than the switching region § and in the data region 。. The photoresist layer 68 is exposed to light by a mask 然后 and then developed. Referring to FIG. 3C, FIG. 4C, FIG. 5C, and FIG. 6C, first The second photoresist pattern 200823582 wood 70a and 70b are respectively formed in the switching region § and the data region = there is a + portion corresponding to the _ pole 52 and corresponds to a second pole = knife-changing region S - second Part. This second part is thicker than the first part., 6』==, 66, this hetero-f doping layer 64, and this essentially amorphous slab layer k is selectively hunted by the younger one and the second The photoresist pattern is added (9). The conductive metal layer 66 is simultaneously removed according to the conductive metal layer 6. The tomb of the tomb and the lower layers 64 and 62 are called the main. Amorphous jin = as shown in the 30th, 41), 5; 〇, and 61), 17S ^ g 80 „ " 匕一一至属图案82. Each of the first...-essentially amorphous side 72 and an impurity-doped amorphous stone 夕图宰1体图木" as in the 3E, 4E, 5E, fen π (5) mountain this first-resistance pattern 7〇a The gate electrode ^2 Dong = two is a polishing process so that the first metal pattern 7 corresponding to the electrode 52 is removed from the first portion, and the gate and the second photoresist pattern are additionally Partially;: go to the first, first, second photoresist pattern 7〇a and 7 knife% to remove the first metal pattern 78 of the first and second metal patterns exposed by the first and second photoresist patterns and the first Feng guide turns to ... up " sickle Hong Road. After ^, it will be removed. The impurity of the bulk layer 76 is doped with the amorphous zebra pattern 74 to refer to the 3F, the ninth, the second, and the electrode 90 and a data line 92. This data line % solid forms a source electrode 88, and a drain-data pad 94 is formed in the second direction in which the _ end direction of the data line % intersects. The intrinsic amorphous germanium pattern 72 in the first semiconductor pattern 76 in the gate electrode & the first semiconductor pattern 76 in the figure is used as the layer 84, and the third portion is used as an ohm. Contact layer 86. When this first ruin pattern 74, which is now divided into two hetero-amorphous ytterbium patterns 74, is partially etched, the impurity of the first semiconductor pattern 76 in the EE pattern % is over-etched, so that The particles may be in a crystalline amorphous pattern, i.e., the active layer 84, and the photoresist patterns 70a and 70b are removed. The knife remains on the surface of the active layer 84. Secondly, 10 200823582 a G 5G and 6G are - The third mask process. As shown in the 3G, 4G, and =6G diagrams, a passivation layer % is substantially formed on the entire surface of the substrate 5, ^ passivation 1%, and contains mats 94's simple line 92. The edge material ^ is formed by 'reading - money is chosen by Qiqiqiqi," and the Wululu 96 can be used on (ship) and cerium oxide (Si〇2). In an alternative way, this Passivation two: the error is formed by coating a substrate 5 on a layer selected from an organic insulating material group, and the organic material group includes a benzene ring (10)) and acrylic resin. Alternatively, minus (4) 'patterning the purification layer %' to form: a drain contact hole 98a, a common line contact hole 98c, and a data contact hole 98d. This and the contact hole of the contact hole This common line contact Konga partially exposes this common line 58. This i pad 94 / tear part exposes this gate 塾%. This information 塾 contact hole pro part exposed 5H, and 6H ugly "" fourth The masking process, as in the 3H, the book, contains the blunt ❹ 96 - like the money and the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Forming the transparent conductive metal material group includes: tin oxide bismuth (10)) and zinc oxide electrode 90 contact 'metal material patterning. The pixel electrode PXL is not electrically connected to the same and is the same as the common line 58 Contact: Each pixel electrode pxl The disk pixel electrode PxH pattern is parallel to the data line 92. The common electrode v_ isPYT ^ father 曰. A gate pad terminal GP# 〇 a data 塾 terminal Dp is coaxial with the image electro-electrode VGGm. This job pad terminal GP is connected to this 瞧56. The data pad 94 is in contact with the contact. The substrate can be formed by the above four mask processes. The second semiconductor pattern 8 is formed under the data (4), and the thousand ridge pattern 8 is formed. The essence of 〇h ^ ^ Beijing 矽 木 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 The vine electrode a is exposed to light. 200823582 Therefore, the photocurrent generated in the active I 84 'causes the thin film transistor to operate incorrectly. [Inventive content] ^This 'this hair _ real _ main needle _ in-plane mode liquid crystal The array substrate of the display device and the thin car are finely quarantined, and the belly can be produced with the disadvantages. The purpose of the embodiment of the present invention is to provide a sound-receiving board for the "special-secret plane-changing display device" and a method for manufacturing the audio-visual board. The thief can (4) have the most current: and can avoid the displayed image. Wave noise. The purpose of the array is to provide a method for forming a matrix of a liquid crystal display device and a method for manufacturing the substrate (four), which can be called low manufacturing cost and time. The characteristics and advantages of the present invention will be described in the following description, 1 ==;; by: application of the invention. The object of the present invention is as follows: 7 (4), special _, like ___ 结 结 了 现 现 现 现 现 现 现 现 现 现 现 现 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些In this method, a method of thinning between the wire and the electrode is defined directly, and the substrate is thinned. The method includes: in the cutting region, the data region, and the common a signal region, formed in the signal region, a gate line having an i-pole electrode, and a common edge layer in the switching region and the mirror insulating layer in the pixel region - the top layer and the - ohmic contact layer, by creating a passivation layer between 岭 = hereinafter detailed. It should be understood that the above-mentioned general description, in another aspect, the brother-in-law's intention is to provide the claimed invention to the first step solution 12 200823582 source secret and secret electrode, forming the source with this source. The method of using the insulating layer between the source electrode and the first electrode for the liquid crystal display device includes: by means of a ; pm': 1 on-board gate electrode and gate line 'On the substrate having the gate electrode plate spring, a gate insulating layer, an active Γ contact f, and a - dragon line are sequentially formed by a second mask process, and the process of transferring the three masks is performed here. A pole, a common electrode, and a pixel electrode are formed on the substrate, and are collectively electrically connected thereto. It should be understood that the above general description of the present invention and the following detailed description are exemplary and illustrative, and the idea is to provide a claim between the D-electrodes and the main ride between the miscellaneous and the enthalpy. The embodiment of the invention is further explained. BRIEF DESCRIPTION OF THE DRAWINGS These and the accompanying drawings are included to provide a further understanding of the invention The principle of the invention is solved. Embodiments of the present invention will now be described in detail, and examples thereof are illustrated in the accompanying drawings. In the embodiment of the present invention, the array substrate is fabricated by three mask processes, wherein an island-shaped active layer is formed on a gate electrode, so that the source terminal of the active layer is not exposed to the backlight. under. Since the source and drain terminals of this active layer are not exposed to light from the backlight, no photocurrent is generated in the active layer. Therefore, wave noise can be prevented. Fig. 7 is a plan view showing an array substrate for an IPS mode LCD device according to a first embodiment of the present invention. 8A to 8D are cross-sectional views of an array substrate for an IPS mode LCD device according to a first embodiment of the present invention. Fig. 8A corresponds to line VII-VII in Fig. 7, line 8B corresponds to line νιπ-νπ in Fig. 7, line 8C corresponds to line DMX in Fig. 7, and 8D The figure corresponds to the line χ-χ in Fig. 7. 13 200823582 / As shown in Fig. 7 and SA to SD, a gate line 104 is formed along a first direction on an insulating substrate 1 and a data line 143 is formed in the - second direction. This gate line 1〇4 and this batting line 143 are in the same relationship with each other thus defining a pixel area p. A gate pad 1G6 is formed at one end of the gate line 1〇4, and a data pad terminal 146 is formed at the _ end of the data cover line 142, and the hopper line 142 covers the tribute line 143. A data pad 144 is at one end of the data line 143. The common line 109 and the common electrode connecting portion are just separated from the gate line 1〇4 by a distance. This common line 109 and this common electrode connection portion 1〇8 are parallel to this gate line 1〇4 and are disposed on the opposite side of this pixel region p. The gate pad terminal 152 covers the gate pad 1〇6. A thin film transistor τ is formed adjacent to a position where the gate and line 104 intersect the data line 143. The thin film transistor τ includes: a gate electrode, a gate insulating layer 11 on the gate electrode 1〇2, an active layer 124 on the gate insulating layer 110, and an active layer 124 thereon. The upper ohmic contact layer 126, the buffer metal layer 128 on the contact layer, the secret electrode 138, and the electrodeless electrode 14{) on the buffer metal layer 128. This gate electrode is just connected to this pole line. The active layer I24 is island-shaped and formed over a gate electrode such that the source terminal and the recording end of the active layer do not extend beyond the boundary defined by the underlying gate electrode. The ohmic contact layer (3) and the buffer metal layer (3) are sequentially disposed on the active layer 124. Each of the buffered base metal layers U8 is in contact with the ohmic contact layer 120 and is in contact with the source electrode 138 and the drain electrode 140, respectively. The source electrode 138 is connected to the data cover line 142, and the drain pin 140 is separated from the source electrode 138. A gate insulating layer η 〇 covers the gate line, the gate electrode 102, and the gate pad 1〇6. Here, the data line 143, the buffer metal layer 128, the ohmic contact layer 126, and the active layer I24 are formed by a homo-mask process, and below the data line 143 and the data frame 144. There is an extension portion β. The extension portion Β includes a sequentially layered pattern and is disposed on the same layer as the ohmic contact layer 126 and the active layer 124. Therefore, this extension portion β has substantially the same structure as the ohmic contact layer 126 and the active layer 124. /, the buffer metal layer 128, the data line ... and the data pad (4) may have at least three layers of sequentially layered multi-layer structure, such as: titanium (M〇Ti) alloy, copper (four) and molybdenum (ΜοΤι )alloy. This source and drain electrodes 138 and 14 〇 and this data _ 146 are from the alloy county. 14 200823582 When the number is m, the signal delay is caused by the minimization of the wire impedance. A pixel electrode 148 and a dynasty 148 are electrically connected to the pixel electrode in the pixel region or P, and the package is connected to the pixel package 150. Each pixel electrode 148 and two turns;; == ° and the common line - electrical connection green 143 bearing a μ main ..., the door envelope 15 〇 includes a plurality of patterns, these electrodes and Xin Gong i 148 The pattern from the second to the electrode 148 alternates with the pattern of the common pole 150. This image is extended in two parts and connected to the electrode 138. This common electrode connection portion (10) is in contact. _ is not shown in the figure, the common i-electrode is connected to the common line 1〇9, and the signal from the common line 109 is provided with two H, coins, 'this common_150 is common with the adjacent one-pixel area- In an alternative manner, the common electrode 150 can be called to connect the t = 09. The pixel electrode connection portion is overlapped with the total (8), and the pixel electrode 148 and the total (four) The pole 15G is formed by the same forming process as the source electrode 138 and the gate electrode 140. This pixel germanium alloy is formed. The pixel electrode 148 and the common electrode 15 can be formed by the main static 154 at: source The reed electrode 148 exposed between the electrode electrode 138 and the drain electrode 140 is on the gate insulating layer 110 between the electrode 15G. Therefore, the passivation layer 154 is directly on the pixel electrode 148 and the common electrode 15. The passivation layer 154 surrounds the gate terminal 152 and the pad terminal 146. This layer 154 can be formed by a deposition and lift-off process without an additional masking process. No exposure, because the source and end of the active layer do not extend beyond The outer boundary defined by the surface electrode can be used to avoid wave noise or fine operation of the fine transistor caused by leakage current. / Refer to Figures 9A to 91, 10A to 1〇1, and 11A. The m-picture and the 12th to 121th drawings illustrate a method of manufacturing an array substrate according to the first embodiment of the present invention. Figs. 9 to 91 are cross-sectional views taken along line VII-VII of Fig. 7. A to 1〇1 is a cross-sectional view taken along line Vm-VIII in Fig. 7. Figures 11A to 111 are cross-sectional views along the line 第_ιχ of Fig. 7. Figs. 12 to 121 are along the line 7 is a cross-sectional view of the Χ-Χ line. As shown in Figs. 10A, 11A, and 12A, a switching area S, a pixel area p, a free area 15 200823582 G, a data area D, and a common signal The regions CS are all defined on a substrate 100. A first conductive metal layer (not shown) is formed on the substrate 1 by depositing a conductive metal on which the S, P, G, D, and CS regions are defined. The metal material is formed of a conductive metal of one or more materials of the conductive metal group: aluminum (A1), aluminum nitride (AINd), (Cr)., molybdenum (Mo), tungsten (W), tin (Ti), copper (〇〇, and 钽 (^). This first conductive metal layer is patterned by a first mask process, thus Forming a gate electrode 1〇2, a gate line 104 of FIG. 7, and a gate pad 106. The gate electrode 1〇2 is disposed in the switching region s, and the gate line 104 and the gate are The pad 106 is disposed in the gate region G. The gate pad 1 is formed at one end of the gate line 104. Meanwhile, a common line of Fig. 7 and a common electrode connection portion 108 are formed on the substrate 100. This common line 109 and the common electrode connection portion 1〇8 are parallel to the gate line 1〇4 and disposed on the opposite side of the pixel region P. Figures 9B to 9F, 10B to 10F, 11B to 11F, and 12B to 12F show a masking process. As shown in FIGS. 9B to 9F, 10B to i〇f, UB to 11F, and 12B to 12F, a gate insulating layer 11〇, an intrinsic amorphous layer (a-Si) . . . H) 112, an impurity doped amorphous layer (for example, n + n4, and a second conductive metal layer 116, sequentially formed on the surface of the substrate 1?, the substrate comprises: the gate electrode 102 The gate line 104 in FIG. 7, the gate pad 1〇6, the common line 109 in FIG. 7, and the common electrode contact portion 108. By coating the substrate 1〇〇 with a photoresist, A photoresist layer 118 is formed on the second conductive metal layer II6. The gate insulating layer 110 can be formed by depositing an inorganic insulating material composed of: or more materials of inorganic insulating materials. Including: nitriding second (break) and oxidized stone eve (Sl 〇 2) ° this first -$ electric metal I 116 may be a multi-layer structure. For example, the second conductive metal layer 116 may include: the first layer of titanium Alloy, second layer of copper, and third layer of molybdenum alloy. This copper has a relatively low resistance wire, while a copper wire can have minimal signal delay Incidentally, copper can easily react with the stone or oxide, thereby increasing the electric power of the wire. To avoid this problem, a layer of titanium molybdenum alloy is formed on the upper and lower sides of the copper layer. Above the photoresist layer 118. The mask M is a halftone mask and a diffraction mask. The mask includes: a light transmitting portion β1, a light blocking portion b2, and a semi-transmissive light. Part B3. The light blocking portion B2 corresponds to the switching area s and the data area d. The light 16 200823582 the transmitting portion B1 corresponds to: the gate region G for the gate pad 106, and the common signal region cs. The light semi-transmission portion B3 corresponds to: other regions than the switching region S, the data region D, the gate region G for the gate pad 1〇6, and the common signal region CS. This light corresponding to the switching region s The size of the blocking portion B2 is not larger than that of the gate electrode 102. Second, the photoresist layer 118 is exposed by the mask and then developed. Referring to Figures 9C, 10C, 11C, and 12C, the 9th, 10th, and 11Β, and
Β圖中的此光阻層118顯影後之後，形成一光阻圖案此光阻圖案no ，有·一第一厚度di的第一部分、與具有一第二厚度d2的第二部分。此 第一部分設置在切換區域S和資料區域D内。此第二部分設置在除了切換 區域S、資料區域D、用於閘極墊1ύ6的閘區域G、以及共同信號區域cS ^外的其他區域内。此光阻圖案12〇在用於間極墊應的閘區域G和共同 信號區域cs中被去除，因此曝露出此第二導電金屬層116。此第_厚度di 完全與第9B、10B、11B、以及通圖中此光阻層us的最初厚度實質1相 同。此第二厚度d2比第一厚度dl要薄。 、 如同第9D、10D、11D、以及12D圖中所示，此曝露的第二導電金屬 層116、此雜質掺雜非晶石夕層114、此本質非晶石夕層112、以及此閑極絕緣 層110，在用於閘極墊106的閘區域G與共同信號區域cs中被去除，以曝 露閘極塾1〇6和共同電極連接部分108。其次，進行一抛光過程因此去除^ 阻圖案120的第二部分。此光阻圖案12〇的第一部分亦部分地被去除。 如同第9E、10E、11E、以及版圖中所示，一光阻圖案⑵存留在 切換區域S和資料區域D内。此光阻圖案122具有比第9D、腸圖中的光 阻圖案120的第-部分更薄的厚度。當閘極墊鹰和共同電極連接部分· 保持部分曝糾’此第二導電金屬層110在除了 f料區域d和—部分切換 =s之外的其他區域中被曝露。此第二導電金屬層116、此雜歸雜非晶 =層1H、以及此本質非晶秒層112，藉由使用作為一侧遮罩的光阻圖案 122而去除。然後，去除此光阻圖案122。 如同第9F、10F、11F、以及12F圖中所示，一主動層124、一歐姆接 q 126、以及-緩衝$金屬層128依序形成在切換區域s巾，以致於此主 動層124的源極端和汲極端不會延伸超過下面閘極電極搬的周圍所界定 17 200823582 之故界。-貝料線143域在痛區邮内一資料墊i44設置在資 143的一端。一延伸部分B形成在資料線143和資料墊144下面。此延伸 B包括分別5又置在與主動層m和歐姆接觸層126同一層上的圖案。 ^就是說’此延伸部分B包括：—本質非晶糊案和-雜質摻雜非晶石夕圖 案。 第9G至9關、聰至麵圖、⑽至題圖、第咖至咖圖顯 示一第三遮罩過程。如同於第9G至9H圖、1〇G至1〇H圖、nG至簡圖、、 第12G至12H圖中所示，一第三導電金屬層（未顯示）和一光阻層（未顯 示）實質上形成在基板100的整個表面上，其包含此主動層以、此歐姆接 126、此缓衝器金屬層128 '以及此資料、線143。此第三導電金屬層可 霸以由MoTi合金組成。此光阻層曝露於光線，並藉由一第三遮罩過賴 因此形成-第-光阻圖案130、-第二光阻圖案132、一第三光阻圖案134、 - 以及一第四光阻圖案136。此第-光阻圖案130設置在切換區域S中，且包 2彼關隔的兩個部分。此第二細圖案132設置在f料區域D中，且與 • 第一光阻圖案130之一部份連接。此第三光阻圖案I34設置在像素區域p 中，且包括彼此交替的第一部分和第二部分。此第四光阻圖案136設置在 閘極塾106上。 此第二導電金屬層藉由使用第一、第二、第三、以及第四光阻圖案13〇、 132、134、以及136作為蝕刻遮罩而去除。形成一源極電極138、一汲極電 φ 極140、一資料覆蓋線142、一資料墊端子146、一像素電極148、一共同 電極150、以及一閘極墊端子152。在此時，亦形成與第7圖中的一像素電 極連接部分148a。此源極電極138和汲極電極140使用第一光阻圖案13〇 形成。此資料覆蓋線142和此資料墊端子146使用第二光阻圖案132形成。 此資料墊端子146設置在資料覆蓋線142的一端。資料覆蓋線142和資料 墊端子146覆蓋住延伸部分B。此像素電極連接部分148a、此像素電極148、 以及此共同電極150都使用第三光阻圖案134形成。此像素電極連接部分 148a與此汲極電極14〇接觸，而此像素電極148自像素電極連接部分14如 延伸。此共同電極150與此共同電極連接部分108接觸。各像素電極148 和共同電極150包括複數個圖案，且像素電極148的圖案舆共同電極15〇 18 200823582 的圖案交替。此閘極墊端子152使用第四光阻圖案136形成，且連接至間 極墊106 〇 甲After the photoresist layer 118 in the pattern is developed, a photoresist pattern resist pattern no is formed, a first portion having a first thickness di and a second portion having a second thickness d2. This first part is set in the switching area S and the data area D. This second portion is disposed in other regions than the switching region S, the data region D, the gate region G for the gate pad 1ύ6, and the common signal region cS^. This photoresist pattern 12 is removed in the gate region G and the common signal region cs for the interpole pads, thereby exposing the second conductive metal layer 116. This _th thickness di is completely the same as the initial thickness of the photoresist layer us in the 9B, 10B, 11B, and the pass graph. This second thickness d2 is thinner than the first thickness d1. As shown in the 9D, 10D, 11D, and 12D diagrams, the exposed second conductive metal layer 116, the impurity doped amorphous slab 114, the intrinsic amorphous slab 112, and the idler The insulating layer 110 is removed in the gate region G and the common signal region cs for the gate pad 106 to expose the gate 塾1〇6 and the common electrode connection portion 108. Next, a polishing process is performed to thereby remove the second portion of the resist pattern 120. The first portion of the photoresist pattern 12A is also partially removed. As shown in the 9E, 10E, 11E, and layout, a photoresist pattern (2) remains in the switching region S and the data region D. This photoresist pattern 122 has a thickness thinner than the first portion of the photoresist pattern 120 in the ninth and intestine drawings. When the gate pad eagle and the common electrode connection portion are held, the second conductive metal layer 110 is exposed in a region other than the f-material region d and the partial switch = s. The second conductive metal layer 116, the hetero-amorphous amorphous layer 1H, and the intrinsic amorphous second layer 112 are removed by using the photoresist pattern 122 as a side mask. Then, the photoresist pattern 122 is removed. As shown in FIGS. 9F, 10F, 11F, and 12F, an active layer 124, an ohmic junction 126, and a buffered metal layer 128 are sequentially formed in the switching region s so that the source of the active layer 124 is present. Extreme and 汲 extremes do not extend beyond the boundaries of the following gate electrode movements defined by 17 200823582. - The feed line 143 field is set at the end of the capital 143 in the pain zone. An extension portion B is formed under the data line 143 and the data pad 144. This extension B includes patterns which are respectively placed on the same layer as the active layer m and the ohmic contact layer 126. ^ That is to say, this extension portion B includes: - an intrinsic amorphous paste case and an impurity-doped amorphous stone pattern. The 9th to 9th, the Cong to the face, the (10) to the title, and the coffee to the coffee chart show a third mask process. As shown in the 9G to 9H, 1〇G to 1〇H, nG to simplified, and 12G to 12H, a third conductive metal layer (not shown) and a photoresist layer (not shown) Substantially formed on the entire surface of the substrate 100, which includes the active layer, the ohmic junction 126, the buffer metal layer 128', and the material, line 143. This third conductive metal layer can be composed of a MoTi alloy. The photoresist layer is exposed to light and is formed by a third mask to form a first-thresist pattern 130, a second photoresist pattern 132, a third photoresist pattern 134, and a fourth light. Resistance pattern 136. This first-resist pattern 130 is disposed in the switching region S, and the package 2 is separated by two portions. The second fine pattern 132 is disposed in the f-region D and is connected to a portion of the first photoresist pattern 130. This third photoresist pattern I34 is disposed in the pixel region p and includes a first portion and a second portion that alternate with each other. This fourth photoresist pattern 136 is disposed on the gate 塾 106. This second conductive metal layer is removed by using the first, second, third, and fourth photoresist patterns 13A, 132, 134, and 136 as etch masks. A source electrode 138, a drain electrode φ pole 140, a data cover line 142, a data pad terminal 146, a pixel electrode 148, a common electrode 150, and a gate pad terminal 152 are formed. At this time, a pixel electrode connecting portion 148a in Fig. 7 is also formed. This source electrode 138 and the drain electrode 140 are formed using the first photoresist pattern 13A. This data overlay line 142 and the data pad terminal 146 are formed using the second photoresist pattern 132. This data pad terminal 146 is disposed at one end of the data cover line 142. The data cover line 142 and the data pad terminal 146 cover the extended portion B. The pixel electrode connection portion 148a, the pixel electrode 148, and the common electrode 150 are all formed using the third photoresist pattern 134. The pixel electrode connecting portion 148a is in contact with the drain electrode 14A, and the pixel electrode 148 is extended from the pixel electrode connecting portion 14. This common electrode 150 is in contact with this common electrode connection portion 108. Each of the pixel electrodes 148 and the common electrode 150 includes a plurality of patterns, and the pattern of the pixel electrodes 148 alternates with the pattern of the common electrodes 15 〇 18 200823582. The gate pad terminal 152 is formed using the fourth photoresist pattern 136 and is connected to the pad 106.
其久，此緩衝金屬層128與歐姆接觸層126是介於第一光阻圖宰13〇 之此等部分之間，其在源極電極138和汲極電極14〇之間並被去除，因此 曝露主動層124。此主動層124和歐姆接觸層126設置在··閘極電極1〇2的 周圍所界定的邊界區域上且包括在其中，以致於由閘極電極1〇2所屏蔽。 此貧料覆蓋線142覆蓋延伸部分B，其包括形成在與主動層124和歐姆接 觸層126同時形成之圖案。因此，此主動層124並未曝露於光線。因為並 沒有由於光而在主動層124中之光電流，薄膜電晶體可以正確工作，並且 在所顯示的影像上不會發生波浪雜訊。 在第阳、10H、11H、以及腿圖中，藉由沉積一無機絕緣材料，將 一鈍化層154實質形成在基板則的整個表面上，其包括第一、第二、第 三、以及第四光阻圖案130、132、134、以及136，其藉由沉積此由無機絕 緣材料組之-錢歸料所構成之綫絕緣材料而軸。此織絕緣材料 組包括：氮化石夕（SiNx)和二氧化石夕（Si〇2)。此鈍化層154包括：在第一、 ^二、第三、以及第四光阻圖案130、132、134、以及136上的部分，在曝 露出的主動層124上、以及在像素電極148和共同電極15〇之間的閑極^ 緣層110上。其次，此第一、第二、第三、以及第四光阻圖案 134、以及136藉由一剝離方法去除。 如同於第91、101、111、以及121圖中所示，此鍊化層154直接覆蓋在 源極電極138柄及極電極140之間的主動層124、以及在像素電極148和共 同電極150之間的閘極絕緣層110。此鈍化層154曝露出間極塾端子^ 貨料塾端子146。 去除此第三導電金屬層，如同於第犯、1〇G、UG、以及如圖中所 示，因此可以使崎方的祕财第—、f二、第三、以及第四光阻 圖案130、132、134、以及136下面進行過餘刻。因此，第一、第二、第三、 以及第四光關案13G、132、134、以及136的下表面都會部分在其周^'部 份地曝露。此曝露的第-、第二、第三、以及第四光阻圖案i3G、i32、134、 以及136的下表面可以使分離器容易地進人第―、第二、第三、以及第四 19 200823582 光阻圖案130、132、134、以及136，因此在剝離過程期間徹底去除第一、 第二、第三、以及第四光阻圖案130、132、134、以及136。因此，令人想 要在第一、第二、第三、以及第四光阻圖案13〇、m、134、以及136之周 圍曝露下表面，以致於各圖案都具有範圍大約在2,〇〇〇至5,000A内的寬 度。與此相同，用於IPS模式LCD裝置的陣列基板可以藉由根據本發明包 括剝離過程之三個遮罩過程製成。 在第一實施例中，此共同電極150和像素電極148由一不透明金屬材 料^/成。在弟一貫施例中，此共同電極和像素電極由一透明導電性材料形 成。此第二實施例將參考第至dd圖說明。 第 13A、13B、13C、以及 13D 圖為沿著第 7 圖中 VII-VII、VIII-Vni、 IX-IX、以及χ-χ線之橫截面圖。如同在第13A、13B、13C、以及丨犯圖 中所不，一切換區域S、一像素區域P、一閘區域G、一資料區域ϋ、以及 共同“號區域CS都界定在基板1〇〇上。一薄膜電晶體形成在基板1〇〇上 的切換區域s内。此薄膜電晶體包括：一閘極電極搬、一在閘極電極1〇2 上的閘極絕緣層110、一在閘極絕緣層11〇上的主動層124、一在主動層Ο# 上的區人姆接觸層126、一在歐姆接觸層126上的緩衝器金屬層128、一透明 _電極138,、以及一透明沒極電極14〇，。此主動層124為一島形而形成 於一閘極電極上，以致於此主動層124 極端和没極端部會延伸超過下 面閘極電極搬的周圍所界定的邊界。此透明源極電極138，和透明沒極電 極140接觸此緩衝器金屬層eg。 中148’和一共同電極150,形成在基板100上的像素區域P 中各像素電極148,和共同電極包括複數個圖案，並且像素電極離 的圖案與共同電極150,的圖宰交替。此’、 連接。此像她降15==48 1胃生 ⑷ρ的一侧。一延伸部分Β、-資料線 貞_* 144、一透明資料覆蓋線142,、 D中。此延伸部分β包括與歐姆接觸層=動層二 此閘區域G和共_顧CS設__ 20 200823582 區域D接觸。第7圖中的一 _線1〇4和一閘極塾形成在閉區域g内。 此閘極塾106設置在閘極線的一端。一閘極墊端子⑸，覆蓋住閑極塾⑺6 且為透明的。-共同電極連接部分⑽形成在制信號區域cs内。此共 電極連接部分108與共同電極150,連接。 、 ”此緩衝态金屬層128可以包括M〇Ti合金、鋼、以及MoTi合金的三個 ^儘官源極電極138’、^及極電極14G，、以及資料覆蓋線142,都由一透明 導電材料形成，此材料具有相對高的阻抗係數，由於緩衝器金屬層128而 沒有信號延遲。 在第二實施例中，此像素電極148,和共同電極15〇，是透明的，因此裝 置的亮度增大。另外，因為此汲極電極140,是透明的，從背光發出的光^ 過透明汲極電極14G，。因此，進人主動層124之光線並沒有被錄電極14〇, 反射。 : 此根據本發明第二實施例之陣列基板可以藉由與第一實施例中相同過 - 程製成，除外的是此第三導電金屬層由一透明導電性材枓形成，例如IT〇 或 ΙΖΟ〇 在第一和第二實施例中，此鈍化層藉由一剝離方法形成。在本發明之 弟二貫施例中，藉由使用一陰影遮罩形成純化層。以下參考第14Α至mc 圖、第15Α至15C圖、第16Α至16C圖、以及第17Α至17C圖，以說明 根據弟二貫施例之陣列基板之製造方法。第三實施例之第一和第二遮罩過 _ 程與第一和第二實施例中的一樣。第14Α至14C圖、第15Α至15C圖、第 16Α至16C圖、以及第17Α至17C圖顯示本發明第三實施例中的一第三遮 罩過程圖。第14Α至14C圖為沿著第7圖乂11々11線之橫截面圖。第15八 至15C圖為沿著第7圖VIII-VIII線之橫截面圖。第1从至16C圖為沿著第 7圖IX-IX線之橫截面圖。第17A至17C圖為沿著第7圖X-X線之橫截面 圖。 在第14A、15A、16A、以及17A圖中，一切換區域S、一像素區域p、 一閘區域G、一資料區域D、以及一共同信號區域⑶都界定在基板綱上。 藉由一第一遮罩過程在基板100上形成一閘極電極1〇2、第7圖中的一閘極 線104、以及一閘極塾106。同時，在基板1〇〇上形成：第7圖中的一共同 21 200823582 線109’與一共同電極連接部分1〇8。此閘極電極1〇2設置在切換區域8中。 此閘極線104和此閘極墊1〇6都設置在閘區域g中，而此閘極墊1〇6設置 在閘極線104的一端。此閘極線1〇4與此閘極電極丨〇2連接。此共同線1〇9 和此共同線及共同電極連接部分108平行於閘極線1〇4。 一閘極纟巴緣層110形成在基板100的整個表面之上，其包括此閘極電 極102、此閘極線104、此閘極墊106、此共同線1〇9、以及此共同電極連 接部分108。此閘極墊1〇6和此共同電極連接部分1〇8部分地曝露，而藉由 一第二遮罩過程在閘極絕緣層11〇上形成一主動層124、此歐姆接觸層 126、以及一緩衝器金屬層128。藉由此第二遮罩過程亦形成一延伸部分B、 一資料線143、以及一資料墊144。此延伸部分B包括：設置在分別與歐姆 接觸層126和主動層no相同的層上的圖案。此延伸部分b設置在資料線 143和資料墊144下方。 一第三導電金屬層ML和一光阻層（未顯示）形成在基板1〇〇的整個 表面上，其包括此主動層124、歐姆接觸層126、資料線143、以及緩衝器 金屬層128。此光阻層曝露於光線，且藉由一第三遮罩過程顯影，因此形成 一第一光阻圖案130、一第二光阻圖案132、一第三光阻圖案134、以及一 第四光阻圖案136。此第一光阻圖案130設置在切換區域8中，並包括彼此 間隔的兩部分。此第二光阻圖案132設置在資料區域D中，且連帶至此第 一光阻圖案130之一部份。此第三光阻圖案134設置在像素區域p内，且 包括彼此交替之第一部分與第二部分。此第四光阻圖案136設置在閘極墊 106之上。 此第三導電金屬層ML藉由使用第一、第二、第三、以及第四光阻圖 案130、132、134、以及136作為蝕刻遮罩而去除，然後去除第一、第二、 第二、以及第四光阻圖案13〇、132、I34、以及I%。此第三導電金屬層 ML可以由MoTi合金或者一透明導電材料構成，例如IT〇或IZ〇。 在第14B、15B、16B、以及17B圖中，形成一源極電極138、一汲極 電極140、一資料覆蓋線142、一資料墊端子146、一像素電極148、一共 同電極150、和一閘極墊端子152。在此時，亦形成第7圖中的一像素電極 連接部分148a。此源極電極138和此汲極電極140都設置在切換區域s内 22 200823582 並彼此分離。此貧料覆蓋線142和此資料墊端子146設置在資料區内， 而此資料墊端子146設置在此觸覆蓋線142的—端。此倾覆蓋線142 和資料墊端子I46覆蓋延伸部分B。此像素電極M8和共同電極⑼都設 置在像素ϋ域p内。此像素電極⑽與祕電極⑽電性連接。共同電極 15〇與共同電極連接部分1〇8連接。各像素電極和共同電極⑽包括複 數個圖案，而像素電極148的圖案與共同電極15〇的圖案交替。此閘極墊 端子152與閘極塾1〇6接觸。 其次’去除此緩衝器金屬層128以及在源極電極138和沒極電極14〇 之間的歐姆接觸層126，因此曝露出主動層124。此緩衝器金屬層128和歐 姆接觸層I26可以藉由使用作為―蝴遮I的第—光關案⑽而去除。 如同於第14C、15C、16C、以及17C圖中所示，一陰影遮罩SM設置 =__子152和資端子146之上，然後藉由沉積由—無機絕緣 材^之-或更多材料所構成之無機絕緣材料，而錄板卿的整個表面 亡貫質上形成-鈍化層154，此無機絕緣材料組包括：氮化砍⑶叫和二 乳化石夕（Si〇2)。此鈍化層154曝露出閘極塾端子152和資料墊端子⑽。 在第三實施例中，藉由使用陰影遮罩，此鈍化層m幾乎形成在所有 的，域内，除了不用-額外遮罩過程的閘極塾端子152和資料塾端子⑽。 ft至^三實施例中，當延伸部分B的圖案與歐姆接觸層126和主動層 中呈伸部分B的圖案可能與它們連接。本個㈣一實施例 中^如㈣圖所示的類似結構。第18圖為根據本發明另—實施例中陣 列基板之橫截面圖。第18圖中的結構與第—至第三實施例中的 ::與二接觸層和主動層連接的延伸部分的圖案以外。如同“中 用—樣的部分具有相瓣考號碼，且可以省略 f苐18圖中’此資料線143和延伸部分B設置在資料區域D中。此 和歐姆接觸層m實質上相同的結構。這即是，此延伸部分 質非晶秒圖案和-雜質摻雜非晶梦圖案，形成 ^ I、主動層124和歐姆接觸層126—樣。此延伸部分B的本質非晶石夕圖案 23 200823582 與主動層m連接，而延伸部分b的雜質推雜非晶卵案與一個 層126連接。此資料覆蓋線142覆蓋延伸部分B，而此源極電極138自資 料覆蓋線142延伸。 ' 第闕中的陣列基板可以藉由與第_至第三實施例中的過程形成。以 此方式，錄據本發明實施例用於IPS模式LCD裝置的陣列基板可以使用 三個遮罩過程製成。這即是，此閘極電極、频極線、此閘極塾、此共同 線、以及此共同電極連接部分都使用第—鮮過程形成。此閘極絕緣層、 主動層、歐姆接觸層、緩衝器金屬層、資料線、以及資料墊都使用第二遮 罩過程在_電極之上形成，在此時’此閘極墊和制電極連接部分同時 經由閘極絕緣層進行曝露。此源極電極和汲極電極、像素電極、共同電極、 閘極墊^子、資料覆盍線、以及資料墊端子使用第三遮罩過程形成。开》成 此鈍化層，並使用剝離過程或陰影遮罩經過鈍化層曝露出閘極墊端子和資 料墊端子。 、 在本發明的實施例中，此主動層設置在閘極電極之中與之上，而來自 二光之光線被防止進入主動層。因此，不會產生出一光漏電電流，而且此 ^膜電晶體可以適當操作。可以顯示出高品質的影像。另外，因為本質非 曰曰石夕層不會曝露超出資料線，則不會產生波浪雜訊。此高寬比會增大，而 I置的亮度會改善。再者，使用三個遮罩過程可以製成陣列基板。製造成 本和時間都會降低，而產量會增加。此外，使用銅作為用於線之材料，以 防止信號延遲。 對於熟習此技術人士為明顯，可以對本發明之用於平面内切換模式液 晶顯示裝置的陣列基板、以及此陣列基板的製造方法，作各種修正與變化， 而不會偏離本發明之精神與範圍。因此，本發明之用意為，其包含在所附 申睛專利範圍與其等同物中之本發明之各種修正與變化。 24 200823582 _ 【圖式簡單說明】 第1圖為根據習知技術IPS模式LCD裝置之概要横截面圖； 第2圖為平面圖，其概要說明根據習知技術用於IPS模式LCD裝置的 陣列基板； 第3A至3H圖，第4A至4H圖，第5A至5H圖，以及第6A至6H圖 為根，習知技術製造用於IPS模式LCD裝置的陣列基板方法之橫截面圖； 第7圖為根據本發明第一實施例用於ips模式lcd裝置之陣列基板的 平面圖； 第8A至8D圖為根據本發明第一實施例用於IPS模式lcd裝 陳 基板之橫截面圖； 第9A至91圖，第i〇A至逝圖，第11A至m圖，以及第i2A至i2i 圖為橫截面圖，其說明本發明第一實施例製造陣列基板之方法； 第13A 13B、DC、以及1犯圖為根據本發明第二實施例陣列基板之 橫截面圖； 第MA至HC圖，第1SA至15C圖，第财至况圖以及第17入至 17C圖為橫截面圖，其說明本發明第二實施例製造陣列基板之方法；以及 第18圖為橫截面圖’其說明本發明第另一實施例之陣列基板。 【主要元件符號說明】 10 下基板 14 閘極電極 16 閘極絕緣層 18 半導體層 20 源極電極 22 汲極電極 30 共同電極 32 像素電極 34a 紅色濾光片/濾色層 34b 綠色濾光片/濾色層 25 200823582For a long time, the buffer metal layer 128 and the ohmic contact layer 126 are between the portions of the first photoresist pattern 13〇, which are removed between the source electrode 138 and the drain electrode 14〇, thus The active layer 124 is exposed. The active layer 124 and the ohmic contact layer 126 are disposed on a boundary region defined by the periphery of the gate electrode 1〇2 and are included therein so as to be shielded by the gate electrode 1〇2. This poor coverage line 142 covers the extended portion B, which includes a pattern formed at the same time as the active layer 124 and the ohmic contact layer 126. Therefore, this active layer 124 is not exposed to light. Since there is no photocurrent in the active layer 124 due to light, the thin film transistor can operate correctly and no wave noise will occur on the displayed image. In the anode, 10H, 11H, and leg diagrams, a passivation layer 154 is substantially formed on the entire surface of the substrate by depositing an inorganic insulating material, including first, second, third, and fourth The photoresist patterns 130, 132, 134, and 136 are axially formed by depositing the wire insulating material composed of the inorganic insulating material group. The woven insulation material group includes: Nitride Xi (XNx) and Sebolite Xi (Si〇2). The passivation layer 154 includes portions on the first, second, third, and fourth photoresist patterns 130, 132, 134, and 136, on the exposed active layer 124, and at the pixel electrode 148 and the common The electrode between the electrodes 15 is on the edge layer 110. Next, the first, second, third, and fourth photoresist patterns 134, and 136 are removed by a lift-off method. As shown in the figures 91, 101, 111, and 121, the chain layer 154 directly covers the active layer 124 between the handle of the source electrode 138 and the electrode 140, and the pixel electrode 148 and the common electrode 150. Inter-gate insulating layer 110. The passivation layer 154 exposes the inter-pole terminal ^ 塾 terminal 146. The third conductive metal layer is removed, as shown in the first sin, 1 〇 G, UG, and as shown in the figure, so that the secret money of the first side, the second, the third, and the fourth photoresist pattern 130 can be made. , 132, 134, and 136 have been left behind. Therefore, the lower surfaces of the first, second, third, and fourth light-closing cases 13G, 132, 134, and 136 are partially partially exposed at their circumferences. The lower surfaces of the exposed first, second, third, and fourth photoresist patterns i3G, i32, 134, and 136 can make the separator easily enter the first, second, third, and fourth portions. 200823582 Resistivity patterns 130, 132, 134, and 136, thus completely removing the first, second, third, and fourth photoresist patterns 130, 132, 134, and 136 during the stripping process. Therefore, it is desirable to expose the lower surface around the first, second, third, and fourth photoresist patterns 13A, m, 134, and 136, so that each pattern has a range of about 2, 〇〇 〇 to a width of 5,000A. Similarly, an array substrate for an IPS mode LCD device can be fabricated by three mask processes including a peeling process in accordance with the present invention. In the first embodiment, the common electrode 150 and the pixel electrode 148 are formed of an opaque metal material. In a conventional embodiment, the common electrode and the pixel electrode are formed of a transparent conductive material. This second embodiment will be explained with reference to the first to dd diagram. The 13A, 13B, 13C, and 13D drawings are cross-sectional views along the lines VII-VII, VIII-Vni, IX-IX, and χ-χ in Fig. 7. As in the 13A, 13B, 13C, and 丨 图 diagrams, a switching area S, a pixel area P, a gate area G, a data area ϋ, and a common "number area CS are defined on the substrate 1". A thin film transistor is formed in the switching region s of the substrate 1. The thin film transistor includes: a gate electrode, a gate insulating layer 110 on the gate electrode 1〇2, and a gate. An active layer 124 on the pole insulating layer 11 , a region contact layer 126 on the active layer Ο #, a buffer metal layer 128 on the ohmic contact layer 126, a transparent electrode 138, and a transparent The electrode layer 124 is formed in an island shape and formed on a gate electrode such that the extreme and non-extreme portions of the active layer 124 extend beyond the boundary defined by the periphery of the lower gate electrode. The transparent source electrode 138, and the transparent electrode electrode 140 are in contact with the buffer metal layer eg. The middle electrode 148' and a common electrode 150 are formed in each of the pixel electrodes 148 in the pixel region P on the substrate 100, and the common electrode includes a plurality of Patterns, and the patterns of the pixel electrodes are separated from the common 150, the figure is alternated. This ', connected. This is like she drops 15 == 48 1 stomach (4) ρ side. An extension part Β, - data line 贞 _ * 144, a transparent data cover line 142, D The extension portion β includes contact with the ohmic contact layer=moving layer 2 and the gate region G and the region D. The _line 1〇4 and a gate 塾 are formed in FIG. In the closed region g, the gate electrode 106 is disposed at one end of the gate line. A gate pad terminal (5) covers the idle electrode (7) 6 and is transparent. The common electrode connection portion (10) is formed in the signal signal region cs The common electrode connecting portion 108 is connected to the common electrode 150. The buffer metal layer 128 may include M〇Ti alloy, steel, and three metal source electrodes 138', and a pole electrode of the MoTi alloy. The 14G, and data overlay 142 are all formed of a transparent conductive material having a relatively high impedance coefficient with no signal delay due to the buffer metal layer 128. In the second embodiment, the pixel electrode 148, and the common electrode 15A, are transparent, so that the brightness of the device is increased. In addition, since the drain electrode 140 is transparent, light emitted from the backlight passes through the transparent drain electrode 14G. Therefore, the light entering the active layer 124 is not reflected by the recording electrode 14 . The array substrate according to the second embodiment of the present invention can be fabricated by the same process as in the first embodiment, except that the third conductive metal layer is formed of a transparent conductive material such as IT 〇 or ΙΖΟ〇. In the first and second embodiments, the passivation layer is formed by a lift-off method. In a second embodiment of the invention, the purification layer is formed by using a shadow mask. Reference is made to Figs. 14 to mc, 15 to 15C, 16 to 16C, and 17 to 17C for explaining the method of fabricating the array substrate according to the second embodiment. The first and second masks of the third embodiment are the same as those of the first and second embodiments. Figs. 14 to 14C, 15th to 15C, 16th to 16C, and 17th to 17C are views showing a third mask process in the third embodiment of the present invention. Figures 14 to 14C are cross-sectional views along the line of Fig. 7, Fig. 11々11. Figures 15 to 15C are cross-sectional views taken along line VIII-VIII of Figure 7. The first to 16C are cross-sectional views along the line IX-IX of Fig. 7. 17A to 17C are cross-sectional views taken along line X-X of Fig. 7. In FIGS. 14A, 15A, 16A, and 17A, a switching region S, a pixel region p, a gate region G, a data region D, and a common signal region (3) are all defined on the substrate. A gate electrode 1 〇 2, a gate line 104 in FIG. 7, and a gate 塾 106 are formed on the substrate 100 by a first mask process. At the same time, a common 21 200823582 line 109' and a common electrode connecting portion 1 〇 8 are formed on the substrate 1A. This gate electrode 1〇2 is disposed in the switching region 8. The gate line 104 and the gate pad 1〇6 are both disposed in the gate region g, and the gate pad 1〇6 is disposed at one end of the gate line 104. This gate line 1〇4 is connected to this gate electrode 丨〇2. This common line 1〇9 and the common line and common electrode connection portion 108 are parallel to the gate line 1〇4. A gate pad layer 110 is formed over the entire surface of the substrate 100, including the gate electrode 102, the gate line 104, the gate pad 106, the common line 1〇9, and the common electrode connection Part 108. The gate pad 1〇6 and the common electrode connection portion 1〇8 are partially exposed, and an active layer 124, the ohmic contact layer 126, and the gate insulating layer 11 are formed by a second mask process. A buffer metal layer 128. An extension portion B, a data line 143, and a data pad 144 are also formed by the second mask process. This extension portion B includes a pattern disposed on the same layer as the ohmic contact layer 126 and the active layer no, respectively. This extension portion b is disposed below the data line 143 and the data pad 144. A third conductive metal layer ML and a photoresist layer (not shown) are formed on the entire surface of the substrate 1B, including the active layer 124, the ohmic contact layer 126, the data line 143, and the buffer metal layer 128. The photoresist layer is exposed to light and developed by a third mask process, thereby forming a first photoresist pattern 130, a second photoresist pattern 132, a third photoresist pattern 134, and a fourth light. Resistance pattern 136. This first photoresist pattern 130 is disposed in the switching region 8 and includes two portions spaced apart from each other. The second photoresist pattern 132 is disposed in the data area D and is coupled to a portion of the first photoresist pattern 130. This third photoresist pattern 134 is disposed in the pixel region p and includes a first portion and a second portion which alternate with each other. This fourth photoresist pattern 136 is disposed over the gate pad 106. The third conductive metal layer ML is removed by using the first, second, third, and fourth photoresist patterns 130, 132, 134, and 136 as an etch mask, and then the first, second, and second portions are removed. And fourth photoresist patterns 13A, 132, I34, and 1%. This third conductive metal layer ML may be composed of a MoTi alloy or a transparent conductive material such as IT〇 or IZ〇. In FIGS. 14B, 15B, 16B, and 17B, a source electrode 138, a drain electrode 140, a data cover line 142, a data pad terminal 146, a pixel electrode 148, a common electrode 150, and a Gate pad terminal 152. At this time, a pixel electrode connecting portion 148a in Fig. 7 is also formed. The source electrode 138 and the drain electrode 140 are both disposed in the switching region s 22 200823582 and are separated from each other. The poor coverage line 142 and the data pad terminal 146 are disposed in the data area, and the data pad terminal 146 is disposed at the end of the touch coverage line 142. The tilt cover line 142 and the data pad terminal I46 cover the extended portion B. This pixel electrode M8 and the common electrode (9) are both disposed in the pixel region p. The pixel electrode (10) is electrically connected to the secret electrode (10). The common electrode 15A is connected to the common electrode connecting portion 1〇8. Each of the pixel electrodes and the common electrode (10) includes a plurality of patterns, and the pattern of the pixel electrodes 148 alternates with the pattern of the common electrode 15A. This gate pad terminal 152 is in contact with the gate 塾1〇6. Next, the buffer metal layer 128 and the ohmic contact layer 126 between the source electrode 138 and the electrodeless electrode 14A are removed, thereby exposing the active layer 124. The buffer metal layer 128 and the ohmic contact layer I26 can be removed by using the first light-off case (10) as a "mask". As shown in Figures 14C, 15C, 16C, and 17C, a shadow mask SM is set above the __ sub-152 and the terminal 146, and then deposited by - inorganic insulating material - or more The inorganic insulating material is formed, and the entire surface of the recording board is formed by a passivation layer 154. The inorganic insulating material group includes: a nitrided chopping (3) and a second emulsifying stone (Si〇2). This passivation layer 154 exposes the gate 塾 terminal 152 and the data pad terminal (10). In the third embodiment, by using a shadow mask, this passivation layer m is formed almost in all, except for the gate 塾 terminal 152 and the data 塾 terminal (10) which are not used for the additional mask process. In the ft to third embodiment, the pattern of the extended portion B and the ohmic contact layer 126 and the pattern of the stretched portion B in the active layer may be connected thereto. In the fourth embodiment of the present invention, a similar structure as shown in the figure (4) is shown. Figure 18 is a cross-sectional view of an array substrate in accordance with another embodiment of the present invention. The structure in Fig. 18 is outside the pattern of the extension of the :: to the second contact layer and the active layer in the third to third embodiments. As the "used-like portion has a phase-cut test number, and can be omitted, the data line 143 and the extended portion B are disposed in the data region D. This is substantially the same structure as the ohmic contact layer m. That is, the extended partial amorphous second pattern and the impurity-doped amorphous dream pattern form the active layer 124 and the ohmic contact layer 126. The amorphous portion of the extended portion B is 23 200823582 Connected to the active layer m, and the impurity-doped amorphous egg case of the extended portion b is connected to a layer 126. This data cover line 142 covers the extended portion B, and the source electrode 138 extends from the data cover line 142. The array substrate in the middle can be formed by the processes in the first to third embodiments. In this manner, the array substrate for the IPS mode LCD device according to the embodiment of the present invention can be fabricated using three mask processes. That is, the gate electrode, the frequency line, the gate 塾, the common line, and the common electrode connection portion are all formed using a first fresh process. The gate insulating layer, the active layer, the ohmic contact layer, and the buffer Metal layer, data line, And the data pad is formed on the _ electrode using a second mask process, at which time the gate pad and the electrode connection portion are simultaneously exposed via the gate insulating layer. The source electrode and the drain electrode and the pixel electrode The common electrode, the gate pad, the data overlay wire, and the data pad terminal are formed using a third mask process. The passivation layer is formed, and the gate pad is exposed through the passivation layer using a stripping process or a shadow mask. The terminal and the data pad terminal. In the embodiment of the invention, the active layer is disposed in and on the gate electrode, and the light from the two light is prevented from entering the active layer. Therefore, no light leakage is generated. The current, and the film transistor can be operated properly. It can display high-quality images. In addition, because the essence of the non-stone layer will not be exposed beyond the data line, no wave noise will be generated. Increase, and the brightness of I will be improved. Furthermore, the array substrate can be fabricated using three mask processes. The manufacturing cost and time will be reduced, and the yield will increase. In addition, copper is used as the line. The material is to prevent signal delay. It is obvious to those skilled in the art that various modifications and changes can be made to the array substrate for the in-plane switching mode liquid crystal display device of the present invention and the method for fabricating the array substrate without It is intended that the scope of the present invention be construed as being limited to the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a plan view schematically showing an array substrate for an IPS mode LCD device according to the prior art; FIGS. 3A to 3H, FIGS. 4A to 4H, 5A to 5H, and FIGS. 6A to 6H are roots, a cross-sectional view of a conventional method for fabricating an array substrate for an IPS mode LCD device; and FIG. 7 is a view for an ips mode lcd according to the first embodiment of the present invention. A plan view of an array substrate of the device; FIGS. 8A to 8D are cross-sectional views of the substrate for the IPS mode lcd mounting according to the first embodiment of the present invention; FIGS. 9A to 91, i 〇A to the end, 11A to m, and i2A to i2i are cross-sectional views illustrating a method of manufacturing an array substrate according to a first embodiment of the present invention; 13A 13B, DC, and 1 are diagrams according to a second embodiment of the present invention. a cross-sectional view of a substrate; a first to fifth, a first to a fifth, a first and a third, and a seventeenth to a seventh, a cross-sectional view illustrating a method of fabricating an array substrate in accordance with a second embodiment of the present invention; Figure 18 is a cross-sectional view showing an array substrate of a second embodiment of the present invention. [Main component symbol description] 10 lower substrate 14 gate electrode 16 gate insulating layer 18 semiconductor layer 20 source electrode 22 drain electrode 30 common electrode 32 pixel electrode 34a red filter / color filter layer 34b green filter / Color filter layer 25 200823582
40 上基板 42 黑色矩陣 45 水平電場 50 絕緣基板 52 閘極電極 54 閘極線 56 閘極塾 58 共同線 60 閘極絕緣層 62 本質非晶石夕層 64 雜質摻雜非晶矽層 66 導電金屬層 68 光阻層 70a 第一光阻圖案 70 b 第二光阻圖案 72 本質非晶矽圖案 74 雜質按雜非晶梦圖案 76 第一半導體圖案 78 第一金屬圖案 80 第二半導體圖案 82 第二金屬圖案 84 主動層 88 源極電極 86 歐姆接觸層 90 汲極電極 92 資料線 94 資料墊 96 14化層 98a 汲極接觸孔 20082358240 upper substrate 42 black matrix 45 horizontal electric field 50 insulating substrate 52 gate electrode 54 gate line 56 gate 塾 58 common line 60 gate insulating layer 62 amorphous amorphous layer 64 impurity doped amorphous layer 66 conductive metal Layer 68 photoresist layer 70a first photoresist pattern 70b second photoresist pattern 72 intrinsic amorphous pattern 74 impurity-doped amorphous dream pattern 76 first semiconductor pattern 78 first metal pattern 80 second semiconductor pattern 82 second Metal pattern 84 active layer 88 source electrode 86 ohmic contact layer 90 drain electrode 92 data line 94 data pad 96 14 layer 98a drain contact hole 200823582
98b 共同線接觸孔 98c 閘極墊接觸孔 98d 資料墊接觸孔 650 基板 100 基板 102 閘極電極 104 閘極線 106 閘極塾 108 共同電極連接部分 109 共同線 110 閘極絕緣層 112 本質非晶石夕層 114 雜質摻雜非晶矽層 116 第二導電金屬層 118 光阻層 120 光阻圖案 122 光阻圖案 124 主動層 126 歐姆接觸層 128 緩衝器金屬層 130 第一光阻圖案 132 第二光阻圖案 134 第三光阻圖案 136 第四光阻圖案 138 源極電極 1385 透明源極電極 140 沒極電極 140’ 透明汲極電極 142 資料覆盍線 20082358298b common line contact hole 98c gate pad contact hole 98d data pad contact hole 650 substrate 100 substrate 102 gate electrode 104 gate line 106 gate 塾 108 common electrode connection portion 109 common line 110 gate insulating layer 112 amorphous amorphous stone层层114 impurity doped amorphous germanium layer 116 second conductive metal layer 118 photoresist layer 120 photoresist pattern 122 photoresist pattern 124 active layer 126 ohmic contact layer 128 buffer metal layer 130 first photoresist pattern 132 second light Resistive pattern 134 Third photoresist pattern 136 Fourth photoresist pattern 138 Source electrode 1385 Transparent source electrode 140 No-pole electrode 140' Transparent drain electrode 142 Data overlay line 200823582
142， 資料覆蓋線 143 資料線 144 資料墊 146 資料墊端子 146， 資料墊端子 148 像素電極 148， 像素電極 148a 像素電極連接部分 150 共同電極 150， 共同電極 152 閘極塾端子 152， 閘極塾端子 154 鈍化層 B1 光透射部份 B2 光阻擋部份 B3 光半透射部份 dl 第一厚度 d2 第二厚度 B 延伸部分 ML 第三導電金屬層 SM 陰影遮罩 Cst 儲存電容 T 薄膜電晶體 P /像素 S 切換區域 P 像素區域 G 閘區域 D 資料區域 CS 共同信號區域 200823582 GP 閘極塾端子 DP 資料墊端子 M 遮罩142, data cover line 143 data line 144 data pad 146 data pad terminal 146, data pad terminal 148 pixel electrode 148, pixel electrode 148a pixel electrode connection portion 150 common electrode 150, common electrode 152 gate 塾 terminal 152, gate 塾 terminal 154 passivation layer B1 light transmission portion B2 light blocking portion B3 light semi-transmission portion dl first thickness d2 second thickness B extension portion ML third conductive metal layer SM shadow mask Cst storage capacitor T thin film transistor P / pixel S switching area P pixel area G gate area D data area CS common signal area 200823582 GP gate 塾 terminal DP data pad terminal M mask