200826540 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種匯流排驅動器，特別是關於一種具電 荷回收電路之低擺幅匯流排驅動器。 【先前技術】200826540 IX. Description of the Invention: [Technical Field] The present invention relates to a bus bar driver, and more particularly to a low-swing bus bar driver having a charge recovery circuit. [Prior Art]
習知技術中，以具電荷回收機制之全擺幅差動對傳送器 電路為例，如第一圖所示，係由I. Bouras等人於n A high speed low power CMOS clock driver using charge recycling technique/1 The 2000 IEEE International Symposium on Circuits and Systems (ISCAS 2000)，vol. 5，pp. 657-660, May 2000.中提出，其係由經過不同數目之反相器，產生 反相之全擺幅訊號，再利用反相器延遲，經由反或閘產生 控制訊號，導通NM101或NM102，使輸出雙端耦合，以回 收電荷，其為全擺幅訊號傳輸，將造成消耗功率較高，E. D. Kyriakis- Bitzaros 等人於"Design of low power CMOS drivers based on charge recycling，’’ The 1997 IEEE International Symposium on Circuits and Systems (ISCAS 1997)，vol. 3，pp· 1924-1927，June 1997·中亦提出類似之技 術。 藉由將訊號擺幅降低，可以有效降低功率的消耗與提升 速度。因此，先前技術中，由H. Zang等人於"Low-swing on-chip signaling techniques: effectiveness and robustness，’’ IEEE Trans, on Very Large Scale Integration，vol. 8，no. 3, pp. 264-273，June 2000·提出一種利用全N型電晶體拉降 113771.doc 200826540 對（NMOS-cmly push-pull)與一低準位電壓參考電壓來降低 輸出電壓準位。然而，其充電源為低準位電壓，將降低對 負載之電流驅動力，造成充電速度緩慢，且製作低準位電 壓參考電壓源將會佔用很大面積，並造成功率之消耗。 因此，有必要提供一種創新且具進步性的具電荷回收電 路之低擺幅匯流排驅動器，以解決上述問題。 【發明内容】 〇 本發明之目的在於提供一種具電荷回收電路之低擺幅匯 流排驅動器，其包括：一低電壓差動對傳送器、一電荷回 收控制訊號產生電路及一電荷回收耦合開關電路。該低電 壓差動對傳送器用以依據一輸入邏輯準位電壓，以產生一 對反相之低電壓差動訊號。該電荷回收控制訊號產生電路 用以依據該輸入邏輯準位電壓轉態情形，相對應地產生至 少二控制訊號。該電荷回收耦合開關電路具有二旁通路徑 電路連接於該對反相之低電壓差動訊號之間，依據該電 t / 荷回收控制訊號產生電路所產生之該等控制訊號，控制二 旁通路徑電路，使該對反相之低電壓差動訊號耦合，以回 收電荷。 本發明低擺幅匯流排驅動器可於電路轉態時回收電荷再 使用，以降低電路功率消耗，並且利用該低電壓差動對傳 送器以降低輸出電壓之準位。 【實施方式】 參考第二圖，其顯示本發明具電荷回收電路之低擺幅匯 Μ排驅動器之電路示意圖。本發明具電荷回收電路之低擺 113771.doc 200826540 幅匯流排驅動器20包括：一低電壓差動對傳送器201、一 電荷回收耦合開關202及一電荷回收控制訊號產生電路 203。該低電壓差動對傳送器201用以依據一輸入邏輯準位 電壓（INR)，以產生一對反相之低電壓差動訊號（OUTRa及 OUTRb)。當該輸入邏輯準位電壓（INR)為高態（邏輯1)時， 該低電壓差動對傳送器201之二輸出端（OUTRa及OUTRb) 將輸出一對低電壓差動訊號電壓準位，其分別為Vhigh與 p Vlow，其中輸出端訊號Vhigh約為500mV，輸出端訊號 Vlow為系統地訊號（邏輯0)。反之，當該輸入邏輯準位電 壓（INR)為低態（邏輯0)時，二輸出端（OUTRa及OUTRb)將 輸出一對低電壓差動訊號電壓準位，其分別為Vlow與 Vhigh。 該低電壓差動對傳送器201包括二低電壓傳送器及一第 一反相器206，該第一反相器206用以將該輸入邏輯準位電 壓（INR)反相為一反相之輸入邏輯準位電壓（INRB)，該輸 C 入邏輯準位電壓（INR)及該反相之輸入邏輯準位電壓 (INRB)輸入至二低電壓傳送器，二低電壓傳送器分別產生 該對反相之低電壓差動訊號（OUTRa及OUTRb)，該對反相 之低電壓差動訊號之電壓值低於該輸入邏輯準位電壓之電 壓值。其中一第一低電壓傳送器係包括：N型電晶體 NM201、NM202、NM203及一反相器204 ; —第二低電壓 傳送器係包括：N型電晶體NM204、NM205、NM206及一 反相器205。 •參考第三圖，其顯示本發明之第一低電壓傳送器之電路 113771.doc 200826540 示意圖。第一低電壓傳送器與第二低電壓傳送器之電路結 構相同，以第一低電壓傳送器為例說明，該第一低電壓傳 送器包括：一全N型電晶體拉降對、一第二反相器204及一 第三N型電晶體NM201。該全N型電晶體拉降對包括一第 一 N型電晶體NM202及一第二N型電晶體NM203，用以分 別接收該輸入邏輯準位電壓（INR)及經該第一反相器206反 相之該反相之輸入邏輯準位電壓（INRB)，在該輸入邏輯準 ζ, 位電壓（INR)為高態時，該第一 Ν型電晶體ΝΜ202導通（turn on)，且由於該反相之輸入邏輯準位電壓（INRB)為低態， 該第二N型電晶體NM203為關閉，故可產生一充電路徑， 對該輸出端（OUTRa)充電。直到輸出端（OUTRa)之電壓準 位，足以使該第二反相器204發生轉態產生低態電壓訊 號，以關閉該第三N型電晶體NM201，結束對輸出端 (OUTRa)充電，此時輸出端（OUTRa)之電壓為Vhigh。 在該輸入邏輯準位電壓（INR)為低態時，該反相之輸入 ly 邏輯準位電壓（INRB)為高態，該第二N型電晶體NM203導 通，以產生一放電路徑，輸出端（OUTRa)放電至地，此時 輸出端（OUTRa)之電壓為Vlow。 該第二反相器204用以接收該輸出端（OUTRa)之電壓， 以產生一反相之輸出端電壓訊號。該第三N型電晶體 NM201用以接收該反相之輸出端電壓訊號，在該輸入邏輯 準位電壓（INR)為高態時，第三N型電晶體NM201導通，以 使一電壓源（Vdd)與該N型電晶體拉降對導通，在該輸入邏 輯準位電壓（INR)為低態時，該第三N型電晶體NM201關 113771.doc 200826540 閉，以關閉該電壓源與該!^型電晶體拉降對之路徑。 士考第四圖，其顯示該第二反相器2〇4之電路示意圖。 該第二反相器204具有一中門檻電壓N型電晶體贝％^]，該 中門檻N型電晶體NM402具有一門檻電壓值係界於一正常 N型電晶體之門檻電壓與零伏之間，以降低轉態電壓，以 達到使遠第二反相器204能於較低輸入訊號電壓，即能發 生轉態使輸出訊號反相。第五圖為使用中門襤電壓n型電 C 晶體之反相器之轉換曲線圖，藉由使用中門檻電壓!^型電 晶體NM402取代一般N型電晶體，可以將轉態電壓（原 590mV)降至 405mV。 再參考第一圖，該電荷回收控制訊號產生電路2〇3用以 依據該輸入邏輯準位電壓（INR)轉態情形，相對應地產生 至少二控制訊號。該電荷回收控制訊號產生電路2〇3包括 該第一反相器206及一反或閘207，用以接收該輸入邏輯準 位電壓（INR)，當該輸入邏輯準位電壓（INr)由低態轉變至 咼態時，經由該第一反相器206，使該反相之輸入邏輯準 位電壓（INRB)由高態轉變至低態，並由該第一反相器2〇6 之延遲，使該輸入邏輯準位電壓（INR)與該反相之輸入邏 輯準位電壓（INRB)於一短暫時間内維持高態。 當該輸入邏輯準位電壓（INR)由高態轉變至低態時，經 由該第一反相器206，使該反相之輸入邏輯準位電壓 (INRB)由低態轉變至高態，並由該第一反相器206之延 遲，使該輪入邏輯準仅電壓（INR)與該反相之輪入邏輯準 位電壓（INRB)於一短暫時間内維持低態，該輸入邏輯準位 113771.doc -10- 200826540 電壓（INR)與該反相之輸入邏輯準位電壓（INRB)輸入至該 反或閘207，該反或閘207輸出一高態控制訊號（NET1)。 該電荷回收耦合開關電路202具有二旁通路徑電路，連 接於該對反相之低電壓差動訊號（OUTRa及OUTRb)之間， 依據該電荷回收控制訊號產生電路203所產生之二控制訊 號，控制二旁通路徑電路，使該對反相之低電壓差動訊號 (OUTRa及OUTRb)耦合，以回收電荷。 該電荷回收耦合開關電路202包括：一第一旁通路徑電 路及一第二旁通路徑電路。該第一旁通路徑電路包括一第 四N型電晶體MNM201及一第五N型電晶體MNM202，該第 四N型電晶體MNM201及該第五N型電晶體MNM202係串接 於該對反相之低電壓差動訊號（OUTRa及OUTRb)之間，用 以分別接收該輸入邏輯準位電壓（INR)與該反相之輸入邏 輯準位電壓（INRB)，在該輸入邏輯準位電壓與該反相之輸 入邏輯準位電壓於該短暫時間内維持高態時，導通該第四 N型電晶體MNM201及該第五N型電晶體MNM202，短暫耦 合該對反相之低電壓差動訊號（OUTRa及OUTRb)，以回收 電荷，重新分配儲存於負載電容C201與C202之電荷，使 放電端之電荷不放電至地，而回收至充電端，以達到電荷 回收動作。 該第二旁通路徑電路包括一第六N型電晶體MNM203， 連接於該對反相之低電壓差動訊號（OUTRa及OUTRb)之 間，並接收該高態控制訊號（NET1)，在該輪入邏輯準位電 壓（INR)與該反相之輸入邏輯準位電壓（INRB)於該短暫時 113771.doc 11 200826540 間内維持低態時，導通該第六N型電晶體mNM203，短暫 輕合該對反相之低電壓差動訊號（〇lJTRa及〇UTRb)，以回 收電荷’重新分配儲存於負載電容以…與以…之電荷， 使放電端之電荷不放電至地，而回收至充電端，以達到電 荷回收動作。 该第四N型電晶體MNM201、該第五N型電晶體MNM202 及該第六N型電晶體MNM203係為中門檻電壓N型電晶體。 由於低電壓差動對傳送器201所輸出之差動訊號為低電壓 訊號，故使用Ν型電晶體作為耦合開關，且爲能快速打開 耦合路徑，故使用中門檻電壓電晶體，原因是其門檻 電壓較低，能較快速導通電晶體，以達到輸出雙端耦合之 效果。 由於低電壓差動對傳送器2〇1在該輸入邏輯準位電壓 (INR)轉態時，其輸出訊號也隨之轉態，且該對反相之低 電壓差動訊號之二輸出端（〇UTRa及OUTRb)互為反相訊 〇 號，因此，一輸出端做充電動作時，另一輸出端則做放電 動作。藉由電荷回收控制訊號產生電路203，產生控制訊 號（INRB及NET1)，以短暫耦合該對反相之低電壓差動訊 號（OUTRa及OUTRb)，重新分配儲存於負載電容C2〇1與 C202之電何’使放電端之電荷不放電至地，而回收至充電 端，以達到電荷回收動作。 本發明低擺幅匯流排驅動器可於電路轉態時回收電荷再 使用，以降低電路功率消耗，並且利用該低電壓差動對傳 送器以降低輸出電壓之準位。另外，該低電壓差動對傳送 113771.doc -12· 200826540 器利用具有中門檻N型電晶體之反相器，來改變其轉換曲 線特性’降低轉態電壓，以達到降低輸出準位之功能。本 發明低擺幅匯流排驅動器可適用於：積體電路1(：中可用於 訊號長路徑傳輸電路，舉凡須降低功率消耗之長路徑傳輸 皆可適用，但不限於上述之應用範圍。 我們將具電荷回收電路之低電壓差動對傳送器所耗之功 率做一分析如下：In the prior art, the full swing width differential transmitter with a charge recovery mechanism is taken as an example, as shown in the first figure, by I. Bouras et al. at n A high speed low power CMOS clock driver using charge recycling Technique/1 The 2000 IEEE International Symposium on Circuits and Systems (ISCAS 2000), vol. 5, pp. 657-660, May 2000. It is proposed that a different number of inverters are used to generate an inverted pendulum. The amplitude signal, then using the inverter delay, generates a control signal via the inverse or gate, turns on the NM101 or NM102, and the output is double-ended coupled to recover the charge, which is a full swing signal transmission, which will result in higher power consumption, ED Kyriakis - Bitzaros et al., "Design of low power CMOS drivers based on charge recycling,'' The 1997 IEEE International Symposium on Circuits and Systems (ISCAS 1997), vol. 3, pp 1924-1927, June 1997. A similar technology. By reducing the signal swing, power consumption and speed can be effectively reduced. Therefore, in the prior art, by H. Zang et al. "Low-swing on-chip signaling techniques: effectiveness and robustness, ''IEEE Trans, on Very Large Scale Integration, vol. 8, no. 3, pp. 264 -273, June 2000. Proposed to reduce the output voltage level by using an all-N transistor pull-down 113771.doc 200826540 pair (NMOS-cmly push-pull) and a low-level voltage reference voltage. However, the charging source is a low-level voltage, which will reduce the current driving force to the load, resulting in a slow charging speed, and making a low-level voltage reference voltage source will occupy a large area and cause power consumption. Therefore, it is necessary to provide an innovative and progressive low-swing bus driver with a charge recovery circuit to solve the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a low swing bus driver with a charge recovery circuit, comprising: a low voltage differential pair transmitter, a charge recovery control signal generating circuit and a charge recovery coupled switch circuit . The low voltage differential pair transmitter is configured to generate a pair of inverted low voltage differential signals in accordance with an input logic level voltage. The charge recovery control signal generating circuit is configured to generate at least two control signals correspondingly according to the input logic level voltage transition condition. The charge recovery coupling switch circuit has two bypass path circuits connected between the pair of inverted low voltage differential signals, and the two bypass signals are controlled according to the control signals generated by the electric charge recovery control signal generating circuit. The path circuit couples the pair of inverted low voltage differential signals to recover charge. The low swing bus driver of the present invention recovers charge usage during circuit transitions to reduce circuit power consumption and utilizes the low voltage differential pair transmitter to reduce the level of the output voltage. [Embodiment] Referring to a second figure, there is shown a circuit diagram of a low swing busbar driver having a charge recovery circuit of the present invention. The low swing pendulum with charge recovery circuit of the present invention 113771.doc 200826540 The bus bar driver 20 includes a low voltage differential pair transmitter 201, a charge recovery coupling switch 202 and a charge recovery control signal generating circuit 203. The low voltage differential pair transmitter 201 is operative to generate a pair of inverted low voltage differential signals (OUTRa and OUTRb) in accordance with an input logic level voltage (INR). When the input logic level voltage (INR) is high (logic 1), the low voltage differential pair transmitter 201 output terminals (OUTRa and OUTRb) will output a pair of low voltage differential signal voltage levels. They are Vhigh and p Vlow, where the output signal Vhigh is about 500mV, and the output signal Vlow is the system signal (logic 0). Conversely, when the input logic level voltage (INR) is low (logic 0), the two outputs (OUTRa and OUTRb) will output a pair of low voltage differential signal voltage levels, which are Vlow and Vhigh, respectively. The low voltage differential pair transmitter 201 includes two low voltage transmitters and a first inverter 206 for inverting the input logic level voltage (INR) to an inverting phase. Inputting a logic level voltage (INRB), the input C logic level voltage (INR) and the inverted input logic level voltage (INRB) are input to the two low voltage transmitters, and the two low voltage transmitters respectively generate the pair The inverted low voltage differential signals (OUTRa and OUTRb), the voltage value of the inverted low voltage differential signal is lower than the voltage value of the input logic level voltage. The first low voltage transmitter includes: an N-type transistor NM201, an NM202, an NM203, and an inverter 204. The second low voltage transmitter includes: an N-type transistor NM204, an NM205, an NM206, and an inverting phase. 205. • Referring to the third figure, a schematic diagram of the circuit 113771.doc 200826540 of the first low voltage transmitter of the present invention is shown. The first low voltage transmitter has the same circuit structure as the second low voltage transmitter. Taking the first low voltage transmitter as an example, the first low voltage transmitter includes: an all N type transistor pull-down pair, a first The two inverters 204 and a third N-type transistor NM201. The all N-type transistor pull-down pair includes a first N-type transistor NM202 and a second N-type transistor NM203 for respectively receiving the input logic level voltage (INR) and passing through the first inverter 206. Inverting the inverted input logic level voltage (INRB), the first germanium transistor ΝΜ 202 is turned on when the input logic is accurate and the bit voltage (INR) is high, and The inverted input logic level voltage (INRB) is low, and the second N-type transistor NM203 is turned off, so that a charging path can be generated to charge the output terminal (OUTRa). Up to the voltage level of the output terminal (OUTRa), which is sufficient for the second inverter 204 to generate a low-state voltage signal to turn off the third N-type transistor NM201, and end charging the output terminal (OUTRa). The voltage at the output (OUTRa) is Vhigh. When the input logic level voltage (INR) is low, the inverted input ly logic level voltage (INRB) is high, and the second N-type transistor NM203 is turned on to generate a discharge path, the output end (OUTRa) is discharged to ground, at which time the voltage at the output (OUTRa) is Vlow. The second inverter 204 is configured to receive the voltage of the output terminal (OUTRa) to generate an inverted output terminal voltage signal. The third N-type transistor NM201 is configured to receive the inverted output terminal voltage signal. When the input logic level voltage (INR) is high, the third N-type transistor NM201 is turned on to enable a voltage source ( Vdd) is turned on with the N-type transistor pull-down pair. When the input logic level voltage (INR) is low, the third N-type transistor NM201 is closed 113771.doc 200826540 to close the voltage source and the !^ type transistor pulls down the path. The fourth diagram of the test, which shows the circuit diagram of the second inverter 2〇4. The second inverter 204 has a mid-threshold voltage N-type transistor N^, the threshold 槛N-type transistor NM402 has a threshold voltage value bounded by a normal N-type transistor threshold voltage and zero volts In order to reduce the transition voltage, so that the far second inverter 204 can be at a lower input signal voltage, the transition state can be reversed to invert the output signal. The fifth figure shows the conversion curve of the inverter using the n-gate voltage C-mode crystal. By using the medium-gate voltage NM402 instead of the general N-type transistor, the transition voltage (original 590mV) can be used. ) down to 405mV. Referring to the first figure, the charge recovery control signal generating circuit 2〇3 is configured to correspondingly generate at least two control signals according to the input logic level voltage (INR) transition state. The charge recovery control signal generating circuit 2〇3 includes the first inverter 206 and an inverse OR gate 207 for receiving the input logic level voltage (INR) when the input logic level voltage (INr) is low. When the state transitions to the state, the inverted input logic level voltage (INRB) is changed from a high state to a low state via the first inverter 206, and is delayed by the first inverter 2〇6 The input logic level voltage (INR) and the inverted input logic level voltage (INRB) are maintained high for a short period of time. When the input logic level voltage (INR) transitions from a high state to a low state, the inverted input logic level voltage (INRB) is changed from a low state to a high state via the first inverter 206, and The delay of the first inverter 206 maintains the round-robin logic-only voltage (INR) and the inverted clock-in logic level voltage (INRB) in a low state for a short period of time. The input logic level 113771 .doc -10- 200826540 The voltage (INR) and the inverted input logic level voltage (INRB) are input to the inverse OR gate 207, which outputs a high state control signal (NET1). The charge recovery coupling switch circuit 202 has two bypass path circuits connected between the pair of inverted low voltage differential signals (OUTRa and OUTRb), and according to the two control signals generated by the charge recovery control signal generating circuit 203, The two bypass path circuits are controlled to couple the pair of inverted low voltage differential signals (OUTRa and OUTRb) to recover the charge. The charge recovery coupled switch circuit 202 includes a first bypass path circuit and a second bypass path circuit. The first bypass path circuit includes a fourth N-type transistor MNM201 and a fifth N-type transistor MNM202. The fourth N-type transistor MNM201 and the fifth N-type transistor MNM202 are connected in series to the opposite pair. Between the low voltage differential signals (OUTRa and OUTRb), respectively, for receiving the input logic level voltage (INR) and the inverted input logic level voltage (INRB) at the input logic level voltage and When the inverted input logic level voltage is maintained in a high state for a short period of time, the fourth N-type transistor MNM201 and the fifth N-type transistor MNM202 are turned on, and the pair of inverted low-voltage differential signals are briefly coupled. (OUTRa and OUTRb), in order to recover the charge, redistribute the charge stored in the load capacitors C201 and C202, so that the charge at the discharge end is not discharged to the ground, and is recovered to the charging end to achieve the charge recovery operation. The second bypass path circuit includes a sixth N-type transistor MNM203 connected between the pair of inverted low voltage differential signals (OUTRa and OUTRb) and receiving the high state control signal (NET1). Turning on the logic level voltage (INR) and the inverted input logic level voltage (INRB) to maintain the low state during the short period of time 113771.doc 11 200826540, turning on the sixth N-type transistor mNM203, briefly light The pair of inverted low voltage differential signals (〇lJTRa and 〇UTRb) are recovered to redistribute the charge stored in the load capacitor with ... and the charge at the discharge end is not discharged to the ground, and is recovered Charge terminal to achieve charge recovery action. The fourth N-type transistor MNM201, the fifth N-type transistor MNM202, and the sixth N-type transistor MMN203 are N-gate voltage N-type transistors. Since the differential signal outputted by the low voltage differential to the transmitter 201 is a low voltage signal, the Ν type transistor is used as the coupling switch, and the middle gate voltage transistor is used because the coupling path can be quickly opened, because the threshold is The voltage is lower, and the crystal can be electrically connected faster to achieve the effect of output double-end coupling. Since the low voltage differential pair transmitter 2〇1 is in the state of the input logic level voltage (INR), the output signal thereof also changes state, and the pair of inverted low voltage differential signals are outputted at the second end ( 〇UTRa and OUTRb) are mutually inverted signals. Therefore, when one output is charging, the other output is discharging. The control signal (INRB and NET1) is generated by the charge recovery control signal generating circuit 203 to briefly couple the pair of inverted low voltage differential signals (OUTRa and OUTRb) and redistributed and stored in the load capacitors C2〇1 and C202. The electric charge does not discharge the charge at the discharge end to the ground, but is recovered to the charging end to achieve the charge recovery action. The low swing bus driver of the present invention recovers charge usage during circuit transitions to reduce circuit power consumption and utilizes the low voltage differential pair transmitter to reduce the level of the output voltage. In addition, the low-voltage differential pair transmits 113771.doc -12· 200826540 using an inverter with a mid-gate N-type transistor to change its conversion curve characteristics to reduce the transition voltage to achieve the function of reducing the output level. . The low-swing bus driver of the present invention can be applied to: integrated circuit 1 (: can be used for signal long-path transmission circuit, and long-path transmission with reduced power consumption can be applied, but is not limited to the above application range. A low voltage differential with a charge recovery circuit analyzes the power consumed by the transmitter as follows:
C pi〇ad = vdd · κ · (C201+C202) · fsC pi〇ad = vdd · κ · (C201+C202) · fs
Vs =Vhigh-Vl〇wVs =Vhigh-Vl〇w
Pa = K^C20l· vdd，vs K 一 C202 C201 + C202 C2012 C201 + C202Pa = K^C20l· vdd, vs K A C202 C201 + C202 C2012 C201 + C202
K C201 fs C201 + C202 'K\fs C2027 Ο C201 + C202 Λ…· (1) (2)⑶⑷ (5)⑹⑺ 功率節省比率=1 - =—C201；^2?. pi〇ad (C201 十 C202)2 .................................... 上述公式中Pi〇ad為不使用電荷回收電路之匯流排之消耗 功率’ Vs為電壓擺幅’ Pa為C201所耗之功率，扑為㈣ 所耗之功率。 低電壓差動對傳送器所消耗之功率如公式⑴所示，〜 為電路工作電壓，fs為電路操作頻率。 ^ . 用千加上電荷回收機制 谩，當該輪入邏輯準位電壓（INR)為高態轉變至低態時， 113771 .d〇c -13- 200826540 該對反相之低電壓差動訊號之一輸出端（〇UTRa)為放電 . 端，另一輸出端（0UTb)為充電端，利用雙端耦合後，電荷 平均分配後端點再分別充電至Vhigh與放電至vlow，理論 上之功率消耗Pa如公式（3)所示。反之，當該輸入邏輯準位 電壓（INR)為低恶轉變至高態時，其功率消耗抑如公式（4) 所示，由此推得具電荷回收電路之低擺幅匯流排驅動器， 理論上所能節省之功率消耗如公式（5)所示。當C2〇i等於 r C202時，理論上最大可節省50%功率消耗。但由於加上控 制電路會增加額外之功率消耗，因此實際電路中並無法達 到理想中最大功率節省。K C201 fs C201 + C202 'K\fs C2027 Ο C201 + C202 Λ...· (1) (2)(3)(4) (5)(6)(7) Power saving ratio=1 - =—C201;^2?. pi〇ad (C201 ten C202 ) 2 .................................... In the above formula, Pi〇ad is not using charge recovery circuit. The power consumption of the bus bar 'Vs is the voltage swing' Pa is the power consumed by the C201, and it is the power consumed by (4). The power consumed by the low voltage differential to the transmitter is as shown in equation (1), ~ is the circuit operating voltage, and fs is the circuit operating frequency. ^. With a charge plus recovery mechanism, when the turn-in logic level voltage (INR) is high and transitions to a low state, 113771 .d〇c -13- 200826540 the pair of inverted low voltage differential signals One output (〇UTRa) is the discharge terminal, and the other output terminal (0UTb) is the charging terminal. After the double-end coupling, the charge is evenly distributed and the terminals are respectively charged to Vhigh and discharged to vlow, theoretically. The consumption Pa is as shown in the formula (3). Conversely, when the input logic level voltage (INR) is low to high, the power consumption is as shown in equation (4), thereby deriving a low-swing bus driver with a charge recovery circuit. The power consumption that can be saved is shown in equation (5). When C2〇i is equal to r C202, theoretically, a maximum of 50% power consumption can be saved. However, due to the additional power consumption added by the control circuit, the ideal maximum power savings cannot be achieved in the actual circuit.
請參照第六圖，其顯示本實狀具電荷回收電路之低擺 幅匯流排驅動器以台灣積體電路公司之018 um 1P6M CMOS製程佈局後所作的模擬。第六圖係顯示了在三個不 同製程角W⑽er)下，具電荷回收電路之低擺幅匯流排 驅動器在輸入為150 MHz時的輸入與輸出波形。第七圖係 G 顯示當負載電容C201等於C202,大小由i pF至5 pF，具電 荷回收屯路之低擺幅匯流排驅動器，與未具有電荷回收機 制之低杬幅匯流排驅動器功率消耗，與所能節省功率消耗 百刀比，S大小為3.5 pF時前者功率消耗為0_85 mW， 後者為〇.98mW，節省功率達13·5%。 准上述貝施例僅為說明本發明之原理及其功效，而非限 J本毛月因此，習於此技術之人士對上述實施例進行修 改及&化仍不脫本發明之精神。本發明之權刹範圍應如後 •述之申請專利範圍所列。 113771.doc -14- 200826540 【圖式簡單說明】 圖1係習知具電荷回收機制之全擺幅差動對傳送器之電 路示意圖； 圖2係本發明具電荷回收電路之低擺幅匯流排驅動器之 電路示意圖； 圖3係本發明之低電壓差動對傳送器之電路示意圖； 圖4係本發明使用中門檻電壓N型電晶體之反相器之電路 示意圖； 圖5係本發明使用中門檻電壓N型電晶體之反相器之輸入 與輪出之轉換曲線圖； 圖6係本發明具電荷回收電路之低擺幅匯流排驅動器以 台灣積體電路公司之〇· 18 um 1P6M CMOS製程佈局後所作 的換擬不意圖；及 圖7係本發明具電荷回收電路之低擺幅匯流排驅動器與 未具電荷回收電路之低擺幅匯流排驅動器之功率消耗及功 〇 率節省比較示意圖。 【主要元件符號說明】 20 本發明之低擺幅匯流排驅動器 201 低電壓差動對傳送器 202 電荷回收耦合開關 203 電荷回收控制訊號產生電路 204 、 205 第二反相器 206 第一反相器 207 反或閘 113771.doc -15- 200826540 C201 、 C202 負載電容 NM201、NM204 第三N型電晶體 NM202、NM205 第一 N型電晶體 NM203、NM206 第二N型電晶體 MNM201 第四N型電晶體 MNM202 第五N型電晶體 MNM203 第六N型電晶體 NM402 中門檻電壓N型電晶體 113771.doc 16-Please refer to the sixth figure, which shows the simulation of the low-amplitude busbar driver with the charge recovery circuit in the 018 um 1P6M CMOS process layout of Taiwan Semiconductor Manufacturing Co., Ltd. The sixth figure shows the input and output waveforms of a low-swing bus with a charge recovery circuit at input 150 MHz at three different process angles W(10) er). Figure 7 shows the low-swing bus driver with a load-capacitor C201 equal to C202, the size from i pF to 5 pF, with a charge recovery loop, and the power consumption of a low-throttle bus driver without a charge recovery mechanism. Compared with the power consumption, the power consumption is 0_85 mW when the S size is 3.5 pF, and the latter is 98.98 mW, which saves 13.5%. The above-described embodiments of the present invention are merely illustrative of the principles and effects of the present invention, and are not limited to the present invention. Therefore, those skilled in the art will be able to modify and <RTIgt; The scope of the power brake of the present invention should be as set forth in the scope of the patent application described later. 113771.doc -14- 200826540 [Simplified Schematic] FIG. 1 is a schematic diagram of a circuit of a full swing differential pair transmitter with a charge recovery mechanism; FIG. 2 is a low swing bus with a charge recovery circuit of the present invention. FIG. 3 is a schematic circuit diagram of a low voltage differential pair transmitter of the present invention; FIG. 4 is a circuit diagram of an inverter using a threshold voltage N-type transistor of the present invention; FIG. 5 is in use of the present invention. FIG. 6 is a diagram of a low-swing bus driver with a charge recovery circuit according to the present invention. The 18 um 1P6M CMOS process is manufactured by Taiwan Semiconductor Co., Ltd. The replacement after the layout is not intended; and FIG. 7 is a schematic diagram comparing the power consumption and the power consumption of the low-swing bus driver with the charge recovery circuit and the low-swing bus driver without the charge recovery circuit. [Main component symbol description] 20 Low swing bus driver 201 of the present invention Low voltage differential pair transmitter 202 Charge recovery coupling switch 203 Charge recovery control signal generating circuit 204, 205 Second inverter 206 First inverter 207 NAND gate 113771.doc -15- 200826540 C201, C202 load capacitor NM201, NM204 third N-type transistor NM202, NM205 first N-type transistor NM203, NM206 second N-type transistor MNM201 fourth N-type transistor MNM202 fifth N-type transistor MNM203 sixth N-type transistor NM402 middle threshold voltage N-type transistor 113771.doc 16-