TW200811865A - Mixed-use memory array and method for use therewith - Google Patents

Abstract

A mixed-use memory array and a method for use therewith are disclosed. In one preferred embodiment, a memory array is provided comprising a first set of memory cells operating as one-time programmable memory cells and a second set of memory cells operating as rewritable memory cells. In another preferred embodiment, a memory array is provided comprising a first set of memory cells operating as memory cells that are programmed with a forward bias and a second set of memory cells operating as memory cells that are programmed with a reverse bias.

Description

200811865 IX. INSTRUCTIONS: [Prior Art] Non-volatile memory arrays maintain their data even when the unit is powered off. In a single-programmable memory array, each memory cell is shaped to be in an initial unprogrammed state and can be converted to a stylized state. This change is permanent and these memory units are

Cannot be erased. In other types of memory, the memory cells are erasable and rewritable multiple times. The swallowing unit can also be changed in several data states that can be achieved for each memory unit. A data state can be stored by changing a characteristic of the detectable memory cell, such as flowing through the memory cell under a predetermined applied voltage or a threshold voltage of a transistor in the memory cell Current. A data state is a distinct value of one of the memory cells, such as a data or a data '' 1π. Some solutions for achieving erasable or multi-state memory cells are complex. For example, the floating gate and the S〇N〇S memory cell operate by storing a charge, wherein the stored charge is present, absent, or the amount of charge changes by a transistor threshold voltage. These memory cells are three-terminal devices that are relatively difficult to manufacture and operate in very small sizes required for competitiveness in modern integrated circuits. Other memory cells operate by changing the electrical rate of relatively exotic materials such as chalcogen. In most semiconductor manufacturing facilities, chalcogenide is difficult to use and can be challenging. A substantial advantage is provided by having an erasable or multi-state memory cell column formed from a non-volatile memory matrix of conventional semiconductor material 121888.doc 200811865 in a structure that is easily scaled to a small size. SUMMARY OF THE INVENTION The present invention is defined by the following, and any content in this paragraph should be construed as limiting the claim.

The preferred embodiment of the invention described below provides a hybrid memory array and method of use thereof. In a preferred embodiment, a memory array is provided, comprising: m (four) cells operating as a single-programmed memory cell; and - a second set of memory operating as a rewritable memory Body unit. In another preferred embodiment, a memory material column is provided, comprising: a first group memory device that operates as a memory unit programmed with a forward bias; and a first group The memory unit is operated as a body block that is stylized with a reverse bias. Other specific embodiments are disclosed, and each specific embodiment can be utilized individually or in combination. Preferred embodiments will now be described with reference to the drawings. [Embodiment] It is known that the resistance of a resistor formed by doped polysilicon can be trimmed by applying an electric pulse to adjust between stable resistance states. These trimmable resistors have been used as components in an integrated circuit. However, it is not customary to use a trimtable polysilicon device in a non-volatile memory cell to store data. There is a difficulty in fabricating a memory array of a compound crystal shi resistor. If a resistor is used as a memory cell in a large cross-point (cr〇ss_p〇int) memory array, then when a voltage is applied to 121888.doc 200811865, a selected memory cell will be used throughout the memory array. There is a need to leak through the semi-selected and non-selected memory cells. For example, referring to FIG. 1, it is assumed that a voltage is applied between the bit line B and the word line A to set, reset, or sense the selected memory cell S. The current is intended to flow through the selected memory unit S. However, a leakage current may flow through the non-selected memory cells Ui, U2, and U3 over an alternate path (e.g., between bit line B and sub-line A). There are many such alternative paths that can exist. By forming each memory cell as a two-terminal device including a diode, the leakage current can be greatly reduced. The diode has a non-linear I-V (current-voltage) characteristic that allows a very small amount of current flow below the turn-on voltage and a higher current flow above the turn-on voltage. In general, the diode is also unidirectional, so that it is easier to travel in one direction than in the other. Therefore, as long as the selected biasing scheme ensures that only the selected memory cell is subjected to a forward current higher than the turn-on voltage, the non-predetermined path can be greatly reduced (such as U1-U2-U3 of FIG. 1 is abnormal). Path) leakage current. U.S. Patent Application Serial No. 10/955,549, filed on Sep. 29, 2004, to "Nonvolatile Memory Cell With 〇m a

Dielectric Antifuse Having High-and Low-Impedance States" (hereinafter referred to as the '549 application and incorporated herein by reference) describes a single-chip three-dimensional memory array in which a semiconductor junction diode is used as a polycrystalline semiconductor The resistivity state of the material to store the data state of the memory cell. This memory unit is a single-programmed memory unit with two data states. The diode is formed in a high resistivity state; applying a stylized voltage permanently transforms the diode into a low resistivity state. 121888.doc 200811865 In a specific embodiment of the invention φ, Α 由 由 由 由 适当 适当 适当 适当 适当 适当 适当 适当 适当 适当 适当 适当 适当 适当 适当 轭 _ _ _ _ 549 549 549 549 549 549 549 549 549 549 549 549 549 549 549 549 549 549 549 549 Half of the application - kind, four or more kinds of stable resistivity, in other specific embodiments, the semiconductor material can be converted from the initial resistivity state to the lower resistivity state; Under the electrical pulse, it can be returned to a higher resistivity state. The specific embodiments can be used individually or in combination to form two or more types of resources.

The material state can be a single-programmed or rewritable memory unit. As described above, the inclusion of a diode between the conductors of the body unit allows it to be formed in a highly dense interconnected memory array. In a preferred embodiment of the invention, the polycrystalline, amorphous or microcrystalline semiconductor memory component is formed to be connected in series with the diode, or more preferably, to form the diode itself. In this discussion, the transition from the higher resistivity state to the lower resistivity state will be referred to as the "set" transition, which is affected by the set current, set voltage, or set pulse; from the lower resistivity state to higher The reversal of the resistivity state will only be referred to as a "reset" transition, which is affected by reset current, reset voltage, or reset pulses. In a preferred single-programmed embodiment, a polycrystalline semiconductor The diode is paired with a dielectric rupture anti-solving filament, however, in other embodiments, the anti-solvent filament can be omitted. Figure 2 illustrates green memory cells formed in accordance with a preferred embodiment of the present invention. - Bottom conductor 12 Formed by a conductive material (for example, tungsten) and extending in a first direction. The barrier layer and the adhesive layer may be included in the bottom conductor 12. 121888.doc 200811865 The retort half body-pole body 2 has a bottom remix a hetero-n-type region 4; an intrinsic region 6, ... is undoped; and a top heavily doped region 8, however, the orientation of the dipole can be reversed. Without the orientation of the diode, it will be called Is a p small η diode. In some embodiments 'Contains dielectric rupture antifuse 14. The top V body 16 can be formed in the same manner and material as the bottom conductor 12 and 4 is different from the first direction - the second direction extends. The polycrystalline semiconductor diode 2 is vertically arranged Between the bottom conductor 12 and the top conductor 16. The polycrystalline semiconductor diode 2 is formed in a high resistivity state. The memory can be formed on the substrate, for example, a single crystal silicon wafer. The figure is shown in a portion of the memory level of the intersection memory array in which the diode 2 is disposed between the bottom conductor 12 and the top conductor 16 (the reverse solution is omitted in this figure) Multiple memory levels are stacked on a substrate to form a high density monolithic three dimensional memory array. In this discussion, the undoped semiconductor material region is described as an essential region. However, those skilled in the art should It is understood that, in fact, the intrinsic region may include - a low concentration of yttrium-type or n-type dopants. The dopant may diffuse from the adjacent region into the intrinsic region' or may be attributed to deposition from earlier deposition during deposition. Dyeing and present in the deposition chamber, m understands that the semiconductor material (such as 7) can be included in the defect (4) to cause it to be slightly η-doped. Use the word "essence" to describe (4), 锗1 wrong The alloy or some other semiconductor material is not intended to imply that this region does not contain any dopants, nor is it intended to imply that the region is fully electrically neutral. The doped polycrystalline or microcrystalline semiconductor can be made by applying an appropriate electrical pulse. .doc 200811865 The resistivity of a material (e.g., helium) changes between steady states. It has been found that in a preferred embodiment, it is advantageous to cooperate with the diode to perform a set transition under forward bias, with a dipole The body is easier to achieve and control the reset transition under reverse bias. However, in some cases, the diode can be reverse biased to achieve a set transition, and the diode is forward biased to achieve reset. change. Semiconductor switching behavior is complex. For diodes, the mating diodes have achieved both set transitions and reset transitions under forward bias. In general, the amplitude of the reset pulse applied by the diode under forward bias (which is sufficient to switch the polycrystalline semiconductor material constituting the diode from a predetermined resistivity state to a higher resistivity state) is low. The corresponding set pulse (which switches the same polycrystalline semiconductor material from the same resistivity state to a lower resistivity state) and has a longer pulse width. Switching under reverse bias presents a different behavior. It is assumed that the polycrystalline p_i-n diode (such as the diode shown in Fig. 2) is subjected to a relatively long switching pulse under reverse bias. After the switching pulse is applied, a smaller read pulse (e.g., 2 volts) is applied and the measurement flows through the current at the read voltage (referred to as the read current). As the voltage of the switching pulse under reverse bias increases in subsequent pulses, the subsequent read current changes by two volts, as shown in FIG. It will be understood that initially, as the electrical voltage of the reverse voltage and the switching pulse increases, when a read voltage is applied after each switching pulse, the read current increases, that is, in the set direction, the semiconductor material (here In the case, the initial transformation of the semiconductor material system is toward a lower resistivity. Once the switching pulse reaches a certain reverse bias voltage (the point in Figure 4, in this example is 121888.doc 200811865 about _14.6 volts), the read current suddenly begins to drop, due to the reset and the increase in the Shih-hs resistivity. Big. When the reverse bias switching pulse is applied, the switching voltage (at which the set trend is reversed and the turns of the diodes begin to reset) depends on, for example, the resistivity state of the diodes that constitute the diode. Variety. Next, it will be understood that the setting or weight of the semiconductor material constituting the diode can be achieved under the reverse bias by the appropriate voltage, and the dissimilar data state of the dimming unit of the present invention corresponds to The resistivity state of the polycrystalline or microcrystalline semiconductor material constituting the diode is detected by flowing a current through the memory cell (between the top conductor 16 and the bottom conductor 12) when a read voltage is applied Identify it. Preferably, the current flowing between any of the distinct data states and any of the different data states is at least 2 factors to allow for differences between states to be easily detectable. The memory unit can be used as a single-programmable memory unit or a rewritable memory unit, and can have two, three, four or more different data states. Under forward bias and reverse bias, the memory cells can be converted from any of their data states to any other data state in any order. Several examples of preferred embodiments will be provided. However, it should be understood that their examples are not intended to be limiting. Those skilled in the art will appreciate that other methods for programming a two-terminal device, including a diode and a polycrystalline or microcrystalline semiconductor material, will be within the scope of the present invention. Single-programmed multi-level memory unit 121888.doc 200811865 In a preferred embodiment of the invention, a -β scale λ is formed by a polycrystalline semiconductor material to dielectrically rupture the anti-solving filament system, Arranged and arranged between the top and bottom conductors. The two devices are used as a single/quasi-memory, and in the preferred embodiment m there are - or four data states. FIG. 2 illustrates a preferred memory device, which is preferably formed by a polycrystalline or micro-conductor conductor material, for example, 7 人Or one and/or one

White to. A more preferred method is the 'diode 2 series polycrystalline stone. In this example, the bottom heavily doped region 4 is n-type and top heavily doped regions, type, however the polarity of the dipoles can be reversed. The memory unit includes a portion of the top conductor, a portion of the bottom conductor, and a diode. The diode is disposed between the conductors. When formed, the diode 2 of the polysilicon is in a high resistivity state, and the dielectric rupture antifuse 14 is intact. Fig. 5 is a graph showing the probability of current of a memory cell in various states (4). Referring to FIG. 5, #apply a read voltage (for example, 2 volts) between the top conductor 16 and the bottom conductor 12 (with the body 2 being forward biased), between the top conductor 16 and the bottom conductor 12 The read current flowing between is preferably in the range of naamper, for example, less than about 5 nanoamperes. The area ¥ on the graph of Fig. 5 corresponds to a first data state of the memory unit. For some memory cells in the memory array, the memory cell will not be pulsed or reset, and this state will be read as one of the data states of the memory cell. This first data state will be referred to as the V state. A first electrical pulse is applied (preferably with the diode 2 under forward bias) between 121888.doc -12 200811865 top conductor 16 and bottom conductor 12. This pulse is, for example, between about 8 volts and about 12 volts, for example, about 1 volt. The current system is, for example, between (10) microamperes and about 200 microamperes. The pulse width is preferably between about _ nanoseconds and about 500 nanoseconds. The first electrical pulse causes the dielectric rupture antifuse (10) to split and switches the semiconductor material of the diode 2 from the -first resistivity state to: the second resistivity state 'the second resistivity state is lower than the first resistivity The state ^second data state will be referred to as the P state' and this transition is not labeled as ν·>ρ" in FIG. The current flowing between the top conductor μ and the bottom conductor 12 at a read voltage of 纟 2 volts is about 1 G microamperes or more. Composition: The resistivity of the semiconductor material of the polar body 2 is reduced by a factor of about 1 ga to about 2 _. In other embodiments, the 'resistivity change is small, but between any data state and other poor state, it will be at least 2, preferably at least 3 or a factor of ' and more typical. A factor of 1〇〇 or more. Some of the memory cells in the memory array will be read with this data state and will not have an additional set pulse pulse. This second data state will be referred to as p-top: an electrical pulse (preferably with diode 2 under reverse bias) between the two-part conductors 12. This pulse is, for example, between about -8 and 14 volts, preferably between about rhyme and about seven volts. The current system (for example) is between about 80 microamperes and about a :: pulse width system (for example) between about just nanoseconds and nanoseconds and about 1 microsecond. Second electricity: =. The second electrical pulse switches the semiconductor 4 of the diode 2 to a third resistivity state, and the third electrical state returns to the second resistivity state. The current flowing between the top 4 conductor 16 and the bottom conductor 12 at a read voltage of 2 volts is between about 10 nanoamperes and amps, preferably between about 100 nanoamperes and about 5 (10) nanoamperes. Some of the memory cells in the two memory arrays will be in this data state: two = f, and will not be pulsed or reset by additional settings. This data will be referred to as the R state, and in Figure 5 this transition is denoted by f, P-> Rft 〇, _ for the fourth data state, a third electrical pulse is applied (preferably with diode 2) Under forward biasing) between the top conductor 16 and the bottom conductor 12. The pulse 2 is, for example, between about 8 volts and about 12 volts (e.g., a job), and the motor system is between about 5 microamperes and about 2 microliters. The third electrical pulse causes the semiconductor material of the one body 2 to switch from the third resistivity state to a fourth resistivity state, the fourth resistivity state is lower than the third resistivity state, and the ruthenium good resistivity is higher than Second resistivity state. The current between the flow-side V body 16 and the bottom conductor 12 at a read voltage of 2 volts is between about 15 microamps and about 4.5 amps. Some of the memory cells in the memory array will be read by this data state (which will be referred to as the s state), and this transition is labeled "R+S" in Figure 5. Μ 任何 任何 任何 任何 任何 任何The current at the read voltage (for example, 2 volts) is a factor of at least 2. For example, the buy current in the data state of the U body unit is preferably at least twice as large as the data value. The read current of any memory cell; the read current of any ~ early element in the data state s is preferably at least twice the read current of the body unit in the data state R; and the data state Any of the 121888.doc -14- 200811865 memory cells preferably have at least twice the read current of any memory cell in the data state Si. For example, the read current in the data state R can be Is twice the read current in the data state V; the read current in the data state S can be twice the read current in the data state R; and the read current in the data state P can be Twice the reading power in the data state S Flow. If their range is defined as small, the difference may be quite large; for example, if the highest current V state memory cell can have 5 nanoamps of read current and the lowest current R state of memory The cell can have a read current of 100 nanoamperes, and the current difference will be a factor of 20. By choosing other limits, it is ensured that the difference in read current between adjacent memory states will be at least a factor of 3. It will be described. A repetitive read-verify-write process can be applied to ensure that the memory cells are in one of the defined data states after a set pulse or reset pulse, and are not in their data. Between states. So far, the difference between the highest current in a data state and the lowest current in the second highest adjacent data state has been discussed. The read current of most memory cells in adjacent data states The difference is still large; for example, the memory cell in the V state can have a read current of 1 nanoamperes; the memory cell in the R state can have 100 nanoamperes The current is read; the memory cell in the S state can have a read current of 2 microamperes (2000 nanoamperes); and the memory cells in the P state can have a read current of 20 microamps. The currents in the state can differ by a factor of 10 or more. Memory cells with four distinct data states have been described. To aid in the identification of data states, select three data states (instead of four data states). For example, a three-state memory unit can be formed in the data state v, set to the data state P, and then reset to the data state R. The memory cell does not have the fourth. Data status s. In this case, the difference between adjacent data states (eg, between the ruler and the !> data state) may be significantly larger. As programmed, a single-program φ memory array containing the memory cells as described, each memory cell being programmed to one of three distinct data traits (in a specific embodiment) Medium) or one of four distinct data states (in an alternate embodiment). These are merely examples; obviously, there may be three or more identical resistivity states and corresponding data states. However, in a memory array containing a single-programmable memory cell, the memory cells can be programmed in a variety of ways. For example, referring to FIG. 6, the memory unit of FIG. 2 can be formed to be in a first state (v|like). a first electrical pulse (preferably under forward bias) causes the rupture antifuse to break 4 and switch the monolayer of the polar body from a first resistivity state to a second resistivity state (second The resistivity state is lower than the first resistivity state; the germanium stealth cell is placed in the p state, and in this example, the p state is the lowest resistivity. a second electrical pulse (preferably under reverse bias) switches the polysilicon of the diode from a first resistivity state to a third resistivity state (the third resistivity is the same as the second resistivity state) ), the memory unit is in the s state. The third electrical pulse (preferably under reverse bias) switches the polysilicon of the diode from the first resistivity state to a fourth resistivity state (third resistivity state 121888.doc -16-200811865 high) In the second resistivity state, the memory cell is in the R state. For any given memory unit, any data state (V state, R state, S state, and P state) can be read as one of the data states of the memory cell. Each transition is labeled in Figure 6. The four different states are shown in the figure; there may be three or more states as needed. In other embodiments, each successive electrical pulse can switch the semiconductor material of the diode to a successive lower resistivity state. As shown in Figure 7,

For example, the 'memory cell can progress from the initial V state to the R state, from the R-like progress to the S state, and from the S state to the P state. For each sorrow, the read current is at least twice the previous one. The state of the read current, each corresponding to a different data state. This scheme is more advantageous when the memory unit does not contain any antifuse. In this example, a pulse is applied under forward bias or reverse bias. In alternative embodiments, there may be three data states or more than four data states. In a specific embodiment, the memory cell comprises a polycrystalline or microcrystalline diode 2' as shown in FIG. 8 and the dipole comprises a bottom heavily doped p-type region 4, an intermediate or lightly doped region 6 and top heavily doped n-type region 8. As in the previous specific embodiment, the diode 2 is electrically rupturable and arranged in a series arrangement between the top and bottom electrodes. The bottom heavily doped p-type region 4 can be doped in situ, that is, the doping method ^ ^ straw due to the "children's product", such as the gas supply of the dopant (such as (4) (four) is incorporated into the formation The thinner of the dopant. * Refer to Figure 9, for the dopant atom, where the memory cell is formed at a voltage of 2 volts and is formed in the shape of a ¥, between the top conductor 16 and the bottom conductor 121888.doc The current between -17 and 200811865 is less than about 80 nanoamperes. A first electrical pulse (preferably applied under positive bias) causes the dielectric rupture antifusing filament 14 (if present) to rupture and cause The bimorph of the polar body 2 switches from a first resistivity state to a second two resistivity state (the second resistivity state is lower than the first resistivity state); and the memory cell is in the data state P. In state p, the current between the top conductor 16 and the bottom body 12 under reading the ink is between about 1 microamperes and about 4 microamperes. A second electrical pulse (preferably under reverse bias) Applying (applying) to switch the polysilicon of the diode 2 from the second resistivity state to a third resistivity state, The second resistivity state is lower than the first resistivity state. The third resistivity state corresponds to the data state M. In the data state "the current between the top conductor 16 and the bottom conductor 12 at the read voltage is about 1 In the specific embodiment of the first 4, between any memory cells in the adjacent data state (between the highest current memory cell in the V state and the lowest current memory cell in the p state) The current | difference between the highest current memory cell in the p state and the lowest current memory cell in the Μ state is preferably a factor of at least 2, preferably a factor of 3 or more. Any data state (V) , Ρ or Μ) can be detected as one of the data states of the memory cell. Figure 4 shows that when the semiconductor diode is subjected to reverse bias, generally the semiconductor material initially passes to a lower resistivity. The transition is set, followed by 'reset transition to higher resistivity as the voltage increases. For this particular diode, the top heavily doped n-type region 8 is used, and preferably by doping with p-type In situ doping The bottom heavily doped region 4, switching from the set transition to the reset transition with increasing reverse bias, does not resemble the diode of the other embodiments as in the case of 121888.doc -18-200811865 This occurs sharply. This means that it is easier to control the set transition under reverse bias using the diode. Rewritable Memory Unit In a specific embodiment, the memory unit acts as a rewritable memory unit. , which can be repeatedly switched between two or three data states. Figure 1A shows a memory unit that can be used as a 彳 rewrite memory unit. This memory unit is the same as the memory unit shown in Figure 2, but Except for dielectric breaks (4), most rewritable embodiments do not include an antifuse in the memory unit, but may include an antifuse if desired. Referring to FIG. 11, in the first preferred embodiment, the stealth unit is formed in a high resistivity state V, and the current at 2 volts is about 5 nanoamperes or less. In an embodiment, the initial v state is not used as one of the data states of the memory unit. A first electrical pulse (preferably with the diode 2 under forward bias) is applied between the top conductor 16 and the bottom conductor 12. This pulse is, for example, between about 8 volts and about 12 volts, preferably about 1 Torr. The first electrical pulse causes the semiconductor material of the diode 2 to switch from a first resistivity state to a second resistivity state, the second resistivity state being lower than the first resistivity state. In a more specific embodiment, the p-state is also not used as a data state for one of the five-cell units. In other embodiments, the p-bear will be used as a data state for one of the memory cells. A second electrical pulse is applied (preferably with the diode 2 under reverse bias) between the top conductor 16 and the bottom conductor 12. The pulse is, for example, between about 彳V and about -14 volts, preferably between about -9 volts and about _13 volts, more preferably about -10 volts or -11 volts. The required voltage will vary with the thickness of the nature zone. The second electric pulse causes the +conductor material of the diode bungee body 2 to switch from the second resistivity to a third resistivity, and the dry resistive state is higher than the first resistance. Rate status. In the preferred embodiment, the R state corresponds to one of the memory states of the memory soap. > A third electrical pulse can be applied between the top conductor 16 and the bottom conductor 12, preferably under forward bias. This pulse is, for example, between about 5.5 volts and about 9 volts 乂 U 6.5 volts and the current system is between about 1 G microamperes and about micro

Preferably, the amperage is about 5. Between the micro-material and about just micro-amperes. This second electrical pulse causes the diode 2 of the diode 2 & dry V coffin to self-苐 three resistivity state R switch - the fourth resistivity state 'the fourth resistivity state is lower than the third resistivity . In the preferred embodiment the 's state corresponds to a data state of one of the memory cells. In this rewritable, two-state embodiment, the r state and the S state are sensed or read as the data state. The memory unit can be repeatedly switched between the two forms L. For example, a fourth electrical pulse (preferably with diode 2 under reverse bias) causes the semiconductor material of the diode to be substantially the same from the fourth resistivity state S (four) to the fifth resistivity state R At a third resistivity, a fifth electrical pulse (preferably with the diode 2 under forward bias) causes the semiconductor of the diode (4) to read from the fifth resistivity state to the third resistivity state S. (which is substantially the same as the fourth resistivity s), and so on. It may be more difficult to return the memory cell to the initial chirp state and the second p state; therefore, in the rewritable memory cell, the states may not Used as a data state. It may be preferable to perform a first electrical pulse (for example, to make the memory cell from \121888.doc -20) before the memory array reaches the user (for example, in a factory or test facility) - 200811865 initial V state switching to P state) and a second electrical pulse (which causes the memory cell to switch from the P state to the R state). In other embodiments, it may be preferred to arrive at the memory array Before the user, only the first electrical pulse is implemented (its The memory unit switches from the initial v state to the p state. As shown in FIG. 11 'in the provided example, any memory cell in a data state is in a neighboring data state (in this case, Any memory unit of R 敕 状 ( 介于 (between about 10 nanoamperes and 5 〇〇 nai ampere) and the ruler state _ (between about 1.25 microamperes and 4.5 microamperes) The difference between the current flowing between the top conductor 16 and the bottom conductor 12 at a read voltage (eg, 2 volts) is a factor of at least 3. Depending on the range selected for a data state, The difference may be a factor of 2, 3, 5 or above. In an alternative embodiment, a rewritable memory unit may be switched between three or more data states in any order. Performing a set transition or resetting a bias or reverse bias. In the described single programmable embodiment and the rewritable embodiment, the data state is indicated to correspond to a complex of diodes. Crystal or microcrystalline semiconductor material The state of the resistivity. The data state does not correspond to the resistivity switching metal oxide or nitride resistivity state, as described in U.S. Patent Application Serial No. 11/395,995, filed on March 31, 2006. Latile Memory Cell c〇mpHsing, Sichuan Heart _ &

The description in the Resistance-Switching Material, which is owned by the assignee of the present invention and incorporated herein by reference in its entirety herein. In the memory cell array formed and programmed in the embodiment, any step of the memory cell subjected to a large voltage in the reverse bias has reduced the leakage current compared to the reverse bias M step. Referring to FIG. 12, assume a cross The selected memory unit 8 applies a forward bias of 1 〇 y. The actual voltage to be used will depend on a number of factors, including the memory 7L configuration, (4) volume, and the nature of the material; Bit 70 line B0 is set to 10 volts, and the word line is set to ground A to ensure that the half-selected memory unit F (which shares the bit line B0 with the selected memory unit S) remains below the pole The turn-on voltage of the body, the word line is set to a voltage lower than but relatively close to the bit line; for example, the word line W1 can be set to 9.3 volts, so that 〇7 volts is applied across the memory unit F ( Only one note is shown in the figure Body unit F, but there may be hundreds, thousands or more. Similarly, in order to ensure that the half-selected memory unit H (which shares the word line W0 with the selected memory unit S) remains below the opening of the diode The voltage, the bit line B i is δ 疋 to the voltage that is still close to the word line w 丨. For example, the bit line Β 1 can be set to 〇·7 volts, so that 跨 is applied across the memory unit 〇 7 volts (again, there may be thousands of memory cells Η). The unselected memory cell u (which does not share the word line w〇 with the selected memory cell S, nor the common bit line Β0) is subjected to - 8.6 volts. There are millions of unselected memory cells U' that result in significant leakage currents in the array. Figure 13 illustrates the application of large reverse bias across memory cells (eg, as A favorable biasing scheme for resetting the pulse. The bit line is set to _5 volts, and the word line W0 is set to 5 volts, so that 1 volt is applied across the selected memory cell s; In the reverse bias, it is not enough to make the non-deliberate setting of 121888.doc -22- 200811865 or reset the half of the selected memory cells F and η Reverse bias, set word line W1 and bit line Β1 to ground, so that half-selected memory cells f and η are subjected to _5 volts. Generally, setting or resetting with reverse bias seems to occur at or near The diode is converted to a reverse breakdown voltage (which is generally higher than _5 volts). Using this scheme, the voltage across the unselected memory unit U is caused, resulting in no reverse & erroneous leakage. Results, such as (for example The ''Dual Data-Dependent Busses for Coupling Read/Write Circuits to a Memory Array'' of the US Patent Application Serial No. 11/461,352, filed by the same application and hereby incorporated by reference. Further description in Agent Slot Number No. 023-0051 can significantly increase the bandwidth. The biasing scheme of Figure 13 is merely an example; obviously, many other schemes can be used. For example, bit line B0 can be set to 〇, word line 〇 can be set to _1 〇, and bit line B1 and word line W1 can be set to _5 volts. In the scheme of Fig. 13, the voltage across the selected memory cell s, the half-selected memory cells Η and F, and the unselected memory cell u will be the same. In another example, bit line Β0 can be set to ground, word line w 〇 can be set to 10 volts, and bit line B1 and word line W1 can be set to 5 volts. Overriding and resetting So far, this discussion has described the application of an appropriate electrical pulse to switch the semiconductor material of the diode from a resistivity state to a different resistivity, thus switching the § memory cell Between two different data states. In practice, their setup and reset steps can be repeated procedures. As noted, the difference between the currents 121888.doc -23-200811865 flowing during the reading in the adjacent data state is preferably a factor of at least 2; in many embodiments, a preferred approach may be , set the current range of each data state, and the factor of 3, 5, 1 or more. Referring to FIG. 14, as described, the voltage is read at 2 volts, and the data state V can be defined as a read current of 5 nanoamperes or less. The data state R can be defined as about 1 nanoamperes and about 500 nanoamperes. Between the data states S can be defined as between about 1.5 microamperes and about 4.5 microamps, and the data state P can be defined as greater than about 10 microamperes. Those skilled in the art should understand that they are merely examples. In another embodiment, for example, the data state V can be defined in a smaller range, wherein the voltage is read at 2 volts and the read current is 5 nanoamperes or less. The actual read current will vary with the characteristics of the memory cell, the configuration of the memory array, the selected read voltage, and many other factors. It is assumed that the single-programmed memory cell is in the data state P. A reverse biased electrical pulse is applied to the memory cell to switch the memory cell to the data state S. However, in some cases, the read current may not be in the desired range after the application of the electrical pulse; that is, the resistivity state of the semiconductor material of the diode is above or below the desired state. For example, assume that after applying an electrical pulse, the read current of the memory cell is at the Q point shown on the graph, between the S state and the P state current range. After an electrical pulse is applied to switch the memory cell to the desired data state, the memory cell can be read to determine if the desired data state is reached. An additional pulse is applied if the desired data status is reached. For example, when the current Q is measured, an additional reset pulse is applied to increase the resistivity of the semiconductor material and reduce the read current into a range corresponding to the S data state. As described above, this set pulse can be applied under forward or reverse bias as described above. The pulse width (voltage or current) of the extra pulse may be longer or shorter than the original pulse. After the additional set pulse, the memory cell is read again, and then the set pulse or reset pulse is applied as appropriate until the read current is in the desired range. In a two-terminal device, such as a memory unit including the described diodes, this would be particularly advantageous for reading to verify settings or resets and adjustments if needed. Applying a large reverse bias across the diode can damage the diode; therefore, it is advantageous to minimize the reverse bias voltage when the mating diode is set or reset in reverse bias. Manufacturing considerations

U.S. Patent Application Serial No. 11/148,530, entitled "Nonvolatile Memory Cell Operating by Increasing Order in Polycrystalline Semiconductor Material", and U.S. Patent Application, filed on Sep. 29, 2004. No. 10/954,510 "Memory Cell Comprising a Semiconductor Junction Diode Crystallized Adjacent to a Silicide" (all of which are owned by the assignee of the present invention and hereby incorporated herein by reference) The crystallization of the complex crystal enthalpy affects the properties of the polycrystalline germanium. The lattice structure of some metal halides (such as cobalt telluride and titanium telluride) is very close to the lattice structure of germanium. When amorphous or microcrystalline germanium is crystallized When it is contacted with one of the tellurides, during the crystallization, the lattice structure of the telluride provides a stencil for the ruthenium. The resulting ruthenium ruthenium will be highly ordered and the defects are rather low. When the material is doped, the high quality polycrystalline germanium is relatively highly conductive when formed. In contrast, The amorphous or microcrystalline germanium material is crystallized to be in contact with germanium having a germanide (the crystal lattice of the germanide is well matched to germanium), for example, 'only in contact with, for example, ceria and titanium nitride (two If the lattice of yttrium oxide and titanium nitride is significantly mismatched to 矽), the resulting ruthenium ruthenium will have many more defects, and the doped ruthenium crystallized in this way will be very low in formation. Conductivity. In the aspect of the invention, the semiconductor material forming the diode is switched between two or more resistivity states, and the current flowing through the diode is changed at a predetermined read voltage, and different currents are Corresponding to the state of the data in the resistivity state. It has been found that highly defective germanium (or other suitable semiconductor material such as germanium or germanium) has not been crystallized by a similar material adjacent to the material or providing a crystallized template. The bismuth formed by bismuth-tellurium alloy exhibits a more favorable switching behavior. Without wishing to be bound by any particular theory, it is believed that the mechanism that supports the observed resistivity change is that it is above the threshold. The set pulse of amplitude causes the dopant atoms to move out of the grain boundary (where the dopant atoms are inactive) into the crystal body (where the dopant atoms will increase the conductivity and reduce the resistance of the semiconductor material). Resetting the pulse may cause the dopant atoms to move back to the grain boundary to reduce the transmission rate and increase the resistance. ❻*, there may be other mechanisms to operate or as an alternative, such as increasing or decreasing the degree of sequencing of the polycrystalline material. It was found that the electrical P-rate L of the crystallized very low defect 相邻 adjacent to the appropriate bismuth compound did not have the same ease as when the semiconductor material had a higher degree of defects. 121888.doc -26 - 200811865 Easy to switch. The presence of defects or the presence of a large number of grain boundaries may allow for easier switching. In a preferred embodiment, then the polycrystalline or microcrystalline material forming the diode is not crystallized adjacent to the material having a small lattice mismatch. A small lattice mismatch system (for example) does not match a lattice of about 3 percent or less. Evidence has suggested that switching behavior can focus on changes in the essential area. Switching behavior has been observed in resistors and p-i-n diodes and is not limited to p-i-n diodes, but the use of p-i-n diodes may be particularly advantageous. Specific embodiments described so far include p-i-n diodes. However, in other embodiments, the diodes may alternatively be p-n diodes and have negligible or no intrinsic regions. Detailed examples describing the fabrication of preferred embodiments of the invention will be provided. U.S. Patent Application Serial No. 10/320,470, entitled "An Improved Method for Making High Density Nonvolatile Memory" (also incorporated herein by reference). The details of the manufacture will help to form the diodes of the specific embodiments of the invention from the '549 application. U.S. Patent Application Serial No. 11/015,824, filed on December 17, 2004, to Hemer et al. ''Nonvolatile Memory Cell Comprising a Reduced Height Vertical Diode" (which is owned by the assignee of the present invention and hereby incorporated by reference herein in its entirety in its entirety in its entirety in the entireties in the entireties in All details of the case, but it should be understood that it is not intended to exclude information from their applications. Example 121888.doc -27- 200811865=Review, order-memory level. Stackable additional memory level, mother early The chip mode is formed above the memory level below it. In this embodiment, the polycrystalline semiconductor diode will be used as a cuttable Memory element. Figure 15a, § The formation of the memory begins with substrate i. This substrate (10) can be any semi-conductive substrate well known in the art, such as a single crystal iv iv compound (such as 矽 锗 or矽_锗_Carb compound, I. • = IHb mouthpiece, epitaxial layer on any of these substrates or any other semiconductive material. The substrate may include an integrated circuit fabricated therein. Forming an insulating layer 〇2. The insulating layer can be yttrium oxide, tantalum nitride, high dielectric film, Si_c_〇 rhyme or any other suitable insulating material. The first conductor 200 is formed over the substrate and the insulator. Between the insulating layer 102: the conductive layer 1〇6, an adhesive layer 1〇4 is included to assist the conductive layer 1〇6 to adhere to the insulating layer 102. If the upper conductive layer is a crane, it is preferably titanium nitride. Adhesive layer 1 〇 4. Next to the layer to be deposited is conductive layer 1 〇 6. Conductive layer 106 may comprise any conductive layer material well known in the art, such as cranes or other materials, including giant, titanium, copper, cobalt or Any of its alloys. All the layers will form all the layers of the conductor track and will use any The mask and etch process are used to pattern and etch the layers to form a substantially parallel scalloped coplanar conductor 2〇〇 as shown in the cross-sectional view of FIG. 15 & In the column, $ is redundant, and the photoresist is patterned by lithography and their remaining layers, and then the standard process technique is used to remove the photoresist from 121888.doc -28-200811865. The conductor 2〇〇 can alternatively be formed by a damascene method. Next, a dielectric material 1 〇 8 is deposited over and between the conductor holders 200. Dielectric material 108 can be any known electrically insulating material, such as, for example, oxidized stone, nitrided, and/or nitrous oxide. In a preferred embodiment, cerium oxide can be used as the dielectric material i 〇8. Finally, the excess dielectric material 1 〇 8 on the top of the conductor track 200 is removed, exposing the top 10 of the conductors separated by the dielectric material 1 〇 8 and leaving substantially flat The surface is 1〇9. Figure 15a depicts the resulting structure. Excessive dielectric removal is performed by any process well known in the art, such as chemical mechanical polishing (cMp) or etch back to form a planar surface 〇9. A technique that can be advantageously used for eclipse is described in U.S. Patent Application Serial No. 1/883,417 issued by Raghuram et al., June 3, 2014, N〇nSelective Unpattemed Etchback to Expose Buried Patterned Features' and This is hereby incorporated by reference. At this stage, a plurality of substantially parallel first I conductors have been formed on the substrate 1 at a first height. - Referring next to Figure 15b, a "straight column will be formed over the finished conductor 2 (in order to save space, the substrate is not shown in Figure 15b; there will be: two substrates present). Preferably, A barrier layer is deposited as the first layer after Z flattening the conductor track. Any suitable material may be used in the barrier layer 'including tungsten nitride, nitride button, titanium nitride or a combination of materials thereof: In a preferred embodiment, titanium nitride is used as the barrier layer. If the barrier layer is titanium nitride, the barrier layer can be deposited in the same manner as described above for depositing the adhesion layer. 121888.doc -29· 200811865 Next, a semiconductor material to be patterned into a pillar is deposited. The semiconductor material may be a stone, a bismuth, a bismuth alloy, or other suitable semiconductor or metal conductor. For the sake of simplicity, the specification refers to semiconductor materials. For the sake of blemishes, those skilled in the art will appreciate that any other suitable material may be selected as an alternative. In a preferred embodiment, the post includes a semiconductor junction: a polar body. The term " Polar body " to refer to a semiconductor device having a non-ohmic conduction property and having a two-terminal electrode and a semiconductor material (the electrode portion (four): the other electrode portion is n-type). Examples include a dipole And η-p diodes (having a contact p-type semiconductor material and an n-type semiconductor material such as a Zener diode) and a diode (wherein an intrinsic (undoped) semiconductor material is inserted in ρ The type of semiconductor material is between the type 11 and the half. Bamboo can be formed by any deposition doping method well known in the art to form heavily doped regions 112. It can be deposited and then doped with Shi Xi, but preferably by deposition of Shi Xi The donor gas flow providing the n-type dopant atoms (for example, lining) is doped in situ during the period. The thickness of the heavily doped region m is preferably between about (10) and about 800 angstroms. The intrinsic layer 114 is formed by any method known to the art. The layer 114 may be a tantalum, niobium or any alloy of niobium or tantalum between about angstroms and about angstroms, preferably about a degree system. Referring back to Figure 15 b, the rigid, bamboo pull, and * just 114 and the same underlying barrier layer 110 - R will be patterned and etched to form a pillar 300. The pillar 300 should have a pitch and width approximately the same as the conductor 2 (9) below, such that each pole is 121888.doc 200811865 300 is formed at the very top of the conductor 200. Some misalignment can be tolerated. The pillar 300 can be formed using a suitable masking and etching process. For example, photoresist can be deposited, patterned using standard lithography techniques, and etched. And then removing the photoresist. Alternatively, a hard mask of some other material (eg, cerium oxide) may be formed on the topmost layer of the semiconductor layer stack (with a bottom anti-reflective coating (BARC) on top), It is then patterned and etched. Likewise, a dielectric anti-reflective coating (DARC) can be used as the hard mask. U.S. Patent Application Serial No. 10/728,436, filed on Jan. 5, 2003, the disclosure of which is incorporated herein by reference in its entirety, the entire entire entire entire entire entire entire entire entire entire content The lithography technique described in 10/8153 12 "Photomask Features with Chromeless Nonprinting Phase Shifting Window" (both of which are owned by the assignee of the present invention and incorporated herein by reference) Any lithographic step used in forming a memory array in accordance with the present invention. A dielectric material 108 is deposited over and between the semiconductor pillars 300 to fill the gaps between the pillars. The dielectric material 108 can be any known electrical power. Insulating material, for example, hafnium oxide, tantalum nitride, and/or hafnium oxynitride. In a preferred embodiment, ceria is used as the insulating material. Next, the dielectric material on the topmost portion of the pillar 300 is removed. Exposing the topmost portion of the pillar 300 separated by the dielectric material 108 and leaving a substantially flat surface. Any of those well known in the art The process (such as CMP or etch back) is used to perform the removal of the over-dielectric. After CMP or etch back, 121888.doc -31 - 200811865 ion implantation is performed to form the top heavily doped P-type region i 16. p-type The dopant is preferably boron or BCI 3. This implantation step completes the formation of the diode U1. Figure i5b shows the resulting structure. In the diode just formed, the bottom heavily doped region 1 i 2 is η-type' And the top heavily doped region 116 is p-type; obviously, the polarity can be reversed. Referring to Figure 15c, next, a dielectric rupture antifuse layer 118 is formed on top of each heavily doped p-type region U6. The wire 118 is preferably a layer of ruthenium dioxide formed by oxidizing the underlying ruthenium in a rapid thermal annealing (e.g., about 600 degrees). The thickness of the antifuse U8 may be about 20 angstroms. Alternatively, the deposition may be reversed. Fuse 11 8. The top conductor 4 can be formed in the same manner as the bottom conductor 2〇〇, for example, by depositing an adhesive layer 12 (preferably made of titanium nitride) and a conductive layer 122 ( Preferably made of tungsten.) Next, the conductive layer 12 is patterned and etched using any suitable masking and etching process. 2 and the adhesive layer 12〇 to form a substantially parallel, substantially coplanar conductor 4〇〇, as shown in FIG. 15. The left-to-right cross-page K is in a preferred embodiment, depositing photoresist, and borrow

The photoresist is patterned by lithography and their layers (4), and then the photoresist is removed using standard process techniques. Connect: A dielectric material (not shown) is deposited over and between the conductors. The dielectric material can be any known electrically insulating material, for example, hafnium oxide, tantalum nitride, and/or nitrogen oxide A IU / / in particular embodiments - can be used as the dielectric material. It has been described to form a first recording layer L, a body level. An additional three-replica level can be formed on the first memory level, since the first two-in-one seven-in-one two-dimensional memory array. In some embodiments, the conductors may be shared between J levels in the memory layer; 121888.doc -32- 200811865 That is, the top conductor 400 will serve as the bottom conductor of the next memory level. In other embodiments, an inter-layer dielectric (not shown) is formed over the first memory level of FIG. 15c, the surface of which is planarized, and the construction of a second memory level begins here. The layers are dielectrically and have no shared conductors. The monolithic three-dimensional memory array is in a memory array φ column in which a plurality of memory levels are formed over a single substrate (such as a crystal-circle) and without an interposer. The layers forming a memory level are deposited or grown directly over an existing layer or layers of multiple levels. In contrast, stacked memory has been constructed by forming memory levels on separate substrates and affixing their memory levels to each other, as in Lee (Jy's U.S. Patent No. 5,915,167, ' Three dimensional structure memory. It is suggested that their substrates can be thinned or removed from their memory levels before bonding. But when these memory layers are initially formed on separate substrates, these memories are not real. a single-chip three-dimensional memory array. _ A single-chip three-dimensional memory array formed over the substrate includes at least a first fe fe body level (which is formed at a higher level than the first height of the substrate) and a first memory A level (which is formed at a second height different from the first height). In this multi-level memory array, three, four, eight or even any number of memory levels can be formed over the substrate. A method described in Radian et al., US Patent Application Serial No. 11/444,936, entitled "Conductive Hard Mask to Protect Patterned Features During Trench Etch", filed May 31, 2005. An alternative method of forming a similar array of memory, in which a mosaic is used to form a conductor, is owned by the assignee of the present invention and is hereby incorporated by reference herein in its entirety. Method of forming a memory array in accordance with the present invention. Alternative Embodiments In addition to the specific embodiments that have been described, many of the memory cells that store their data states in the resistivity state of the polycrystalline or microcrystalline semiconductor material Alternative embodiments are also possible and are within the scope of the invention. A few other possible embodiments will be mentioned, but this list is not intended to be exhaustive and enumerated. Figure 16 illustrates a switchable form formed in series with a diode 1 η. Memory element 117. The switchable $ ** element 117 is formed by a semiconductor material that is switched between resistive states using electrical pulses as described above. As described above, the 'diode is preferably adjacent to The telluride (such as cobalt telluride, which provides a crystallization template) is crystallized, resulting in a semiconductor material defect of the diode that is extremely low and exhibits Insignificant or no switching behavior. Preferably, the switchable memory element 117 is doped and should be doped to the same conductivity type as the top heavily doped region 116. The fabrication of the device is described in the '167 application. Methods. Detailed fabrication methods have been described herein, but any other method of forming the same structure can be used, with the results falling within the scope of the present invention. Exemplary Applications The specific examples of how to use memory cells as two poor materials are described. State memory cells, two or more data state memory cells, single-programmed memory cells, or rewritable memory cells. This multi-purpose 121888.doc -34 - 200811865 uses the common record system to provide the commemorative products. The versatility of memory cells and their implications are discussed below: "The potential of memory arrays"

The memory unit described above has a memory 70 member comprising a switchable resistive material, such as a semiconductor material configurable to one of at least three resistivity states. The memory component"" to-resistivity state (e.g., the initial, unprogrammed, sigma component has an initial resistivity state) may be formed during formation of the memory component, or by subsequent The memory component is subjected to a set pulse or reset pulse to "configure" the memory component to a resistivity state. Because of this feature, a single memory cell can operate in two different ways: as a single-programmable memory cell or as a rewritable memory cell. Furthermore, because of this characteristic, a single memory unit can use two data states or two or more data states. Accordingly, any predetermined memory cell has the potential to operate as a single-programmed memory cell or rewritable memory cell having two or more data states as shown and as above As described above, when the memory unit operates as a single-programmed memory unit, a resistivity state is used to represent the memory of the memory unit, but when the memory unit operates as a rewritable memory unit, This resistivity state is used to represent a profile of the memory cell. In other words, when the memory unit is used as a single-programmable memory single 7L, there may be an "extra" state in the memory unit. For example, as described above and in conjunction with Figures 5 and u The described memory unit ' δ hex memory unit is fabricated to be in an initial resistivity state (V state), 121888.doc -35- 200811865 t and when the memory unit operates as a single-programmed memory unit, ^Initial resistivity state; but when the memory single (4) is used as a rewritable memory early element, the initial resistivity state is not used. When the memory unit operates as a rewritable memory single (10), two other materials are used. The status ((10) and 8 states) indicates the data status of the memory unit. (As shown in the following figure, the data can also be used in a single-programmed memory unit~) by changing the switchable resistance material. Resistors are used to achieve the status of their data. Again, their other data states do not include the information used to represent the status of the data only when the memory unit operates as a single-person memory unit.

Materialy evil. Additional data states (e.g., ''R2'' state between the r state and the s state) may be used to allow the rewritable memory cells to achieve three or more than three distinct data states. In a preferred embodiment, the memory component includes a switched resistive material (eg, a semiconductor material) connected in series with the antifuse, and the V state is only a single operation when the memory cell operates The resistivity state that is used when staging memory cells. The reason is that once the antifuse is blown, the memory element cannot return to the V state. However, even when no antifuse is used, a resistivity state can be designated as a state to be used only when the memory cell operates as a single-programmable memory cell. It should also be noted that the P state can also be a resistivity state that is used when the memory cell operates as a single-programmable memory cell but is not used when the memory cell operates as a rewritable memory cell. However, in some embodiments, instead of or in addition to the P state, one or both of the R state and the S state are used to represent a data state of the single-programmable memory cell, the -36 - 121888.doc 200811865 When the three-dimensional stylized memory unit stores three or four data states. In this case, the single-programming and rewritable uses of the three-remembered unit will have a resistivity state in common. For example, instead of having a unique state state, a single-programmed memory cell and a rewritable memory cell (eg, V-state and state-of-state are used for a single-programmed memory cell, and R-state and S The state is for a rewritable memory unit), and the single-programmed memory unit and the rewritable memory unit can have a state together (for example, there is no difference between the s state and the ρ state). However, when the memory unit operates as a single-programmable memory unit, at least one resistivity state (eg, ν state) will still be used to represent a data state of the memory cell; however, when the memory cell operates as This is not the case when overwriting the memory unit. One advantage of this versatility is that a single integrated circuit with such memory cells can be designated as a single-programmable memory array or as a rewritable memory array. This provides manufacturing flexibility and yield improvement. To determine if an e-memory array is applied as a single-programmable memory array or as a rewritable memory array, a set of test memory cells in the memory array can be tested during (or after) manufacturing. For example, the test memory cells can be utilized by repeating the stylization, duplication, and setting of their test memory cells. A suitable test technique is described in U.S. Patent No. 6,407,953, the disclosure of which is hereby incorporated by reference in its entirety in its entirety in its entirety herein in Based on the test results, it is predicted whether the memory array will be properly programmed to act as a rewritable memory array. For example, if the test shows that it is difficult to distinguish between the R state and the s state (these states are used when the memory array is operated as a rewritable memory array), then the component will be very Month b is not properly programmed to act as a rewritable memory array. However, because the memory cells in the body array can operate as a single-programmable memory matrix or as a rewritable matrix, instead of being discarded because the component does not provide the expected rewritable results. This part can be specified as a single-pass degenerate z L-body array. Accordingly, the common backbone memory cell architecture provides manufacturing flexibility and yield improvement. _ At this point, there may be manufacturing differences. The tested memory array can continue to be further formatted (eg, stylized all memory cells from the ¥ state to the p state, then applied between the ruler state and the s state as a final qualification test), and then Shipped to a warehouse or user as a rewritable memory array (eg, a memory card for a digital camera). Memory arrays that fail the test can be loaded and sent to different parts of the manufacturing facility to program the single-person private content. Alternatively, the part can be sent to the warehouse to be programmed in the field by the Kaiku staff or the user to program the content _ (for example, using kiosk). Unprogrammed parts can also be sold to users for use as archive memory. Preferably, a flag is used to send a signal to a device for reading and writing to the memory array (for example, a controller on a memory device including a memory array or a hardware/software in the host device). The memory array is told to be a single-programmed memory array or a rewritable memory array. "flag" can be stored in one or more bits in a memory array. For example, a flag can be set in a special address location (e.g., address (10) (10)) in the L-body array. When the host device detects the flag, it can adapt to the single-programmability of the memory array by not attempting to re-program the memory array and instead use the entire memory array as a flag. The memory array can be a "multi-purpose product array" in a single program or as a rewritable memory array. In this embodiment, since the memory cells in the memory array are Can be used as a single-programmed memory unit or as: a rewritable long-range unit, so the _th-group memory unit operates as a single-programmed memory unit' and a second group of memory units operate as A rewritable memory cell. In this mode, the memory cell and the rewritable memory cell can be programmed once on the same integrated circuit. As described above, a test can be performed to determine - a predetermined set of memory Whether the unit should be designated as a single-programmable memory unit or a rewritable memory unit. Figure 17 is a diagram showing a preferred embodiment of a mixed-use memory array 2A. A first set of memory cells twenty one The operation is a single-programmed memory unit, and a second set of memory units 22 operates as a rewritable memory single 7G. In this embodiment, the two sets of memory in 21〇, 22〇 The units all contain the same number of data states per memory unit, however the number of changes in the memory unit data status is feasible, as described below. In an /, the first set of memory unit storage is considered Permanent and relevant to the operation of the memory array. Examples of this information include (but are not limited to) one or more of the following: content management bits, trim bits, manufacturer data, and formatted data. Bits refer to information related to the management of stylized content. The trim bit is a custom message that sets various options in the circuit on the wafer. The on-wafer circuit reads the first set of memory cells 210. 121888.doc -39- 200811865

Dressing the 7L 'and the 蹲 术 + + / 夂 、 、 、 、 、 、 、 、 、 、 、 进一步 进一步 进一步 进一步 进一步 进一步 进一步 进一步 进一步 进一步 进一步 进一步 进一步 进一步 进一步 进一步 进一步 进一步 进一步 进一步 ' ' ' ' ' ' ' ' ' ' ' ' ' '乂>[The history of soil write/read values (current or voltage). "Manufacturer's material T includes the manufacturer's name and serial number. "formatted data" indicates: a bad part of the memory array; specifically, t, one of the memory arrays and/or defective and redundant Remaining and 'or row location. For more information on redundancy, see US Patent Application Nos. ι〇/4〇2,385 and 10/024,646遽, all of which have been filed in their patents. The assignee of the present invention is hereby incorporated by reference in its entirety to the extent that it is hereby incorporated by reference in its entirety in the the the the the the the the the the the the the A set of memory units 21A may include game content material (ie, a computer program code of the game), and the second set of memory units 220 may include game state data (ie, when the user requests to save the game, in the game) Further, the data in the first set of memory units 220 can be programmed at the manufacturer or by a subsequent user. The group memory unit 210 or the second is in FIG. Secondary stylized memory unit only Only one m of the segments and the re-storable memory cells are in the $-specific embodiment, and at least the intervening memory cells operate as a single-programmable memory cell or a rewritable memory cell. 18 illustrates a specific embodiment in which two singularly stylized sections 230, 250 are interleaved with two rewritable sections 24, 260 (ie, two adjacent sets of memory cells are not available) Single stylized or rewritable. As mentioned above, any data can be stored in any section. For example, game content data can be stored in a single pass 121888.doc -40- 200811865 In the segments 230, 250, the game state data may be stored in the rewritable sections 240, 260. It should be noted that although Figures 17 and 18 illustrate the orientation of the groups of memory cells in a horizontal manner, In a specific embodiment, one or more sets of memory cells can be oriented in a vertical manner. For example, instead of having formatted data in a horizontal column of memory cells (as shown in FIG. 17), the formatted data can be vertically Column memory unit. In this way, Redundant data will span many pages. Mixed-use horizontal orientation and vertical orientation information can also be used. For example, 'manufacturing data can be used for water and money, and formatted data can be oriented vertically. As shown in Figure 18, each page of information Included may be - or a plurality of flag bits 270 indicating whether the page is either single-programmable or rewritable. In Figure 18, the "1" flag indicates a single stylization, and, The "〇" flag indicates rewritable. Preferably, the flag is stored in a single-programmable memory unit (even if the memory unit is in a rewritable section). Moreover, the preferred method is to optimize the preset read conditions for the single-program & data (so the single-programmable flag bit stored in the single-programizable section can be successfully read. And trimming bits, manufacturing materials, etc.), and if the flag indicates rewritable data, modify their reading conditions. The advantage of using a flag bit is that it is actually impossible to use a single-programmed memory cell as a rewritable memory cell, and vice versa. The original, the source is interpreted by a write circuit on the chip. The write-once circuit on the wafer is programmed to use a flag bit to indicate that a memory unit can be single-programmed to prevent more than: writes to the memory unit. 121888.doc -41- 200811865 As an alternative to using the flag 'location' address space calculation and write control can be moved out of the chip, for example, to hardware/software in the host device. For example, if a memory device is used as the game E, the software in the host device can use a pre-designated address for storing game state data (the host device knows the address space, but the memory is not available). Know the address space). The alternative is 'can be stored in the game in the memory array. The wipes, the memory list m a single stylized part (for example, the #-body array - special address location (for example, address GGGG) Or information in the device controller in the memory device that is separate from the memory array to inform the host device of the address space for the game state data. / In the specific embodiment of FIGS. 17 and 18, the memory array is a memory cell unit in which the memory unit can be programmed twice and the other is a rewritable memory unit. "Mixing use". In other specific examples, the "mixed use" memory array contains other "hybrid" features, as described above, in lieu of or in addition to a single stylized/i-writable feature. , can use _ flag private bit or its mechanism to determine - the nature of a given set of memory cells ^. For example, the first set of memory cells in the same memory array can be more than the second set of memory cells Reliable and wider temperature and voltage range. As another real <column, using the preferred memory cell structure described above' - a given memory cell can be: (i) programmed with forward bias (for example, (d) one can be a single stylized memory unit or rewritable memory early element); or (ii) be stylized with a reverse bias (eg, as the same rewritable memory unit, but different Two-state single-programmed memory single 12 1888.doc -42- 200811865 yuan). In other words, the single-programmed memory unit can only accept forward bias programming, while the rewritable memory unit can accept forward bias programming and reverse bias programming. Both are shown in the circuit diagrams of Figures 19 and 20. For a detailed description of the forward bias write, see U.S. Patent No. 6,618,295; and a detailed description of the reverse bias write, See U.S. Patent Application Serial No. 11/461,339 (Attorney Docket No. 023-0048) entitled "Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders" and U.S. Patent Application Serial No. 11/ 461,364 (Attorney Profile Number No. 023-0054) entitled "Method for Using a Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders", all of which have been assigned to the transfer of the present invention This is hereby incorporated by reference. Accordingly, the "hybrid" memory array can include: a first set of memory cells that are programmed with forward bias; and a second set of memory cells that are reverse biased. Stylized. A memory cell that is programmed with a reverse bias can also be erased with a forward bias. In an erase operation (compared to a write operation), individual data bits in a page are not variables because all bits are erased during the erase operation. For a detailed description of the erase operation, see U.S. Patent Application Serial No. 11/461,339 (Attorney Docket No. 023-0048) entitled ''Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders&quot And U.S. Patent Application Serial No. 11/461,364 (Attorney Docket No. 023-0054) entitled "Method for Using a Passive Element Memory Array 121888.doc •43- 200811865

Incorporating Reversible Polarity Word Line and Bit Line Decoders", each of which has been assigned to the assignee of the present application, is hereby incorporated by reference. The discussion so far has been on the use of memory cells as a single-programmable memory cell or as a rewritable memory cell, and the memory array has a single-programmable memory cell and a rewritable memory cell. mixing. However, as described above, another preferred embodiment of the memory unit is that the memory unit (whether a single-programmed memory unit or a rewritable memory unit) can store two types of data. Status or two or more data states. Multiple test memory cells can be tested for each possible data state to determine how much data state can be stored in a memory array. For example, the test memory cells can be tested in the V, P, and 8 data states to infer whether the memory cells are desirably functioning as a four-dimensional, one-shot programmable memory cell. If the memory array fails the measurement, it can be used as a two-state memory array in which the appropriate flags are stored. A hybrid memory array can be used in conjunction with a set of memory cells using X resistivity states to represent X data states, and used in conjunction with a second set of memory cells using gamma resistivity states to represent Y species. Data status, where X矣Y. In this manner, the number of data states stored in a memory cell in the memory array can vary between groups of memory cells. The various versatile and mixed versatility described above can be combined. For example, the first set of memory cells and the second set of memory cells in the memory array can use different numbers of data states, and both can be single time 121888.doc -44- 200811865: formula: two two Can be rewritten, or can be a single stylized 舆 rewritable mix: body single: 2, multiple parts of the memory array can be single-programmed fe, body early 7G and can be 4 k Save any combination of X-insert-heart early, where - part of the X-type bedding state (for example, the state of the data (10), such as two _ _ _ and another - part of the storage of the state of the material). For example, the memory array can have: _ flute "w, a set of memory cells, which can be single-programmed, and eight or more data states (for example, for stylized data); and

A second set of memory cells that are rewritable and have more than two types of data (e.g., for use as a scratchpad memory). There can be more than two parts. As described above, the selection of the state of use of the smugglers in any group of memory cells can be determined by testing. For example, a four-state single-programmable memory cell fails the test if the V, p, and R states cannot be discerned because of the read circuit. The memory array portion containing their test memory cells can then be used as a two-state rewritable portion. In this case, the write circuit can be verified using a repetitive write stylization (as described above) and then re-programmed again to push the R state, push " to the V state and to the 8 state, push,, To the P state. In other words, the repeated feedback mechanism is "open" "space" between the R state and the S state. Multi-purpose memory arrays with different data states: In fact, although each memory cell has the potential to store more than two data states, the most efficient use of memory cells in memory arrays occurs in memory arrays. When all memory units are stored in more than two states. For example, in a preferred embodiment, a first set of memory cells is 121888.doc •45-200811865 as a single-programmed memory cell, and a second set of memory cells is available. Overwrite the memory unit. Figure 2U shows this particular embodiment. In this embodiment, the optimal circuit configuration settings for reading the four state memory cells are stored in the two state memory cells. For example, as shown in FIG. 21, the configuration bit in the page indicates a page that is read with respect to each memory cell four-state read circuit operation with each memory cell two-state read circuit operation. . These configuration bits also determine the limits of the available bits in each memory cell φ ten-state page. When writing to the page. When configuring the part of the wafer for the two-state data and the four-state data. For a single-table memory cell usage, the page can be written several times to include additional configuration bits indicating the extra portion of the two-state data because the configuration bits are set to logic &quot ;i", so that all pages except page 0 are read as four-state data (ie, the default configuration reads only page 0 = state data). Native one-time stylized memory The body unit state (V-like evil) is the logic "1". The default configuration and interpretation of the configuration bits is performed by memory-based logic coding on the wafer. The number of columns is not necessarily equal to the number of pages, but is preferably a simple multiple (for example, four pages to one column). ^ Gossip configuration is feasible. For example, another application may have, as a third portion of the two-state data per memory unit, based on indicating the next best memory bank 70 in the third portion of the memory array. In still another application, the memory array has a single-programmable memory unit in the first portion and two or more state-of-the-art rewritable memory units (e.g., using R, S, and R1 states). The optimal circuit configuration is better stored in a two-state, single-programmable memory unit. In addition, 121888.doc -46 - 200811865 $Memory array: has two state rewritable memory in the first part and two or more stateful rewritable memory cells in the second part. FIG. 22 is a diagram of a memory array of a preferred embodiment: 'where the flag bit on each physical page indicates the portion of each memory that is early and second. Part of the four states of each memory unit. The flag bit is preferably two state data per memory unit. An even number of pages Φ i are associated with the parent column. If the item is taken as '’ Γ, the flag bit for the odd page indicates that the page is not available. Unusable pages are also stored in the logic or software outside the memory chip and can be reassigned by known redundant/bad block mechanisms. Alternatively, each column of shared flag bits can be used, the flags in f are associated with multiple pages and indicate the number of states per memory and the unavailability of several pages. Preferably, the page in the number of even pairs of J is used. For several adjacent columns, the block used for the bad block table is preferably defined as one-half of the column. ® 23 shows an illustration of a memory array of a preferred embodiment in which a portion of each state of each memory cell and a portion of each state of the memory cell are indicated by a translation table stored in the delta recall array. . The translation table has a correspondence between logical page addresses and entity columns in the memory array. The translation table also contains flag bits ° for the number of bits stored in a physical column. Optionally, the translation table also has a flag indicating that certain pages are single-programmable or rewritable. The flag bit preferably controls the read and write circuits for the optimal setting of the type of information used for the indication. FIG. 24 is a diagram showing a memory array of a preferred embodiment, wherein a symbol of each memory cell is indicated by a flag bit on each physical page by 121888.doc -47-200811865 The transcribed portion, the two-state rewritable portion of each memory unit, and the four-state single-programmed portion of each memory unit. In this embodiment the 'flag bit is stored as two state data per memory unit. An even number of pages are associated with each column. The off-chip controller scans the flag information to create a bad block table. A flag bit for some pages indicates that the page is not available. The flag bit also preferably controls the read and write circuits on the wafer to provide _ for the two-state operation of the parent suffix unit and the optimizable configuration of the rewritable operation with respect to the single under-programming operation . In this case, the flag bit indicated in FIG. 24 includes at least one bit for indicating the number of states per memory unit and a bit for indicating that it can be single-programmed or rewritable. In some embodiments, more than two bits can be used. Figure 25 depicts a flow diagram of a preferred embodiment using a wafer flag and an off-chip bad block mechanism. Provide a logical page address (step 3〇〇). A bad block table in the controller chip of the memory device is associated with the translation logic to determine a preliminary physical address associated with the logical page address (step 31A). Next, the flag bit located at the preliminary physical address is read with a preset of two states per memory unit (step 320). If the page is not available, a feedback mechanism is used to update the write status for the unavailable page (step 33A), which causes the controller wafer to update the bad block table. Otherwise, the read or write circuit is set to two state modes or two or more state modes (step 34()). The page material is then read or written (step 350). Although any suitable embodiment can be used to use any suitable memory unit, the memory unit includes passive memory. 121888.doc -48- 200811865

A component (which includes a switchable resistive material, preferably a semiconductor), specifically a polycrystalline diode. Other switchable resistive materials include, but are not limited to, binary (-) metal oxides, phase change materials (as shown in U.S. Patent No. 5,751 '. 012 and U.S. Patent No. 4,646,266) and organic material I5. And a memory cell comprising a plurality of organic material layers comprising at least one layer having conductivity-like conductivity and at least an organic material applying an electric field to change conductivity. U.S. Patent No. M55, i8 nicknames an array of organic passive components. The other varistor material is doped with V, Co Ni Pd, Fe or Mn, as described more fully in U.S. Patent No. 5,541,869. Another class of materials is taught in U.S. Patent No. 6,473,332. These materials are perovskite materials such as PruCaxMnOs (PCM0), Lai.xCaxMn〇3 (LCMO), LaSrMn03 (LSMO) or GdBaC〇x〇Y (GBCO). Another option for this variable resistance material is a carbon polymer film comprising, for example, carbon black particles or graphite mixed in a plastic polymer, as taught in U.S. Patent No. 6,072,716. Another switchable resistive material is taught in U.S. Patent Application Serial No. 9/943, the entire disclosure of which is incorporated herein by reference. This material is a chalcogenide glass of the doped molecular formula ΑχΒ γ, where a contains at least one of the following elements of the periodic table: Group IIIA (B, Al, Ga, In, Ti), Group IVA (C, Si, Ge) , Sn, Pb), Group VA (N, P, As, Sb, Bi) or Group VIIA (F, Cl, Br, I, At); wherein the B is selected from the group consisting of S, Se and Te, and mixtures thereof. The dopant is selected from the group consisting of noble metals and transition metals, including Ag, Au, Pt, Cu, Cd, Ir, Ru,

Co, Cr, Mn or Ni. This chalcogenide glass (amorphous chalcogenide, not crystalline) is formed in a column adjacent to a moving metal ion reservoir. Ketian Gan # aa

One uses a certain eight-turn solid electrolyte material to replace the chalcogenide glass. In a preferred embodiment of the invention, the component comprises a reverse: wire in series with the semiconductor material. In a further preferred embodiment, the memory component comprises a reverse fused, 糸70 metal oxide and a polycrystalline germanium diode isolation device. The memory unit can be a component of the two-dimensional memory array, but the more common method is the 'memory unit is a component of a single-chip three-dimensional memory array, wherein the memory unit is arranged in a plurality of layers of memory, each _ The memory level is formed over the - single substrate and without any interposer. Preferably, the memory component is non-volatile. However, in an alternate embodiment, the memory component can be volatile in the state of the data used when the memory component operates as a rewritable memory cell. For example, a memory element may allow the V state and the P state to be permanent, but may allow the R state and the S state to slowly fade. With this _memory component, the R state and the S state will be refreshed over time. The foregoing detailed description describes only a few of the many forms in which the invention may be employed. For the sake of this reason, the detailed description is intended to be illustrative, and not to limit the invention. Only the following claims (including all equivalents) are intended to define the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram showing the electrical isolation between memory cells in a memory array. 2 is a cross-sectional view of a multi-state or rewritable memory cell formed in accordance with a preferred embodiment of the present invention. 121888.doc -50- 200811865 FIG. 3 is a cross-sectional view showing a portion of a memory hierarchy including the memory cell shown in FIG. 2. Fig. 4 is a graph showing changes in the read current of the memory cell of the present invention as the reverse bias voltage across the diode increases. • Figure 5 illustrates the probability edge map of the memory cell transitioning from the V state to the P state, from the p state to the R state, and from the R state to the S state. - Figure 6 illustrates the probability plot of the memory unit transitioning from the V state to the P state, from the p state to the S state, and from the S state to the R state. Figure 7 is a graph showing the probability of a memory cell transitioning from a V state to an R state, from a r state to an S state, and from a S state to a P state. Figure 8 is a cross-sectional view of a vertically oriented diode that can be used in a particular embodiment of the invention. Figure 9 shows the memory cell changing from ν state to ? The state and the probability plot from the ρ state to the Μ state. Figure 10 is a cross-sectional view of a multi-state or rewritable memory cell formed in accordance with a preferred embodiment of the present invention. Figure 11 is a graph showing the probability of the memory cell transitioning from the V state to the ρ state, from the ρ state to the R state, and from the R state to the S state, and then repeatable between the S state and the R state. * Figure 12 is a circuit diagram showing the biasing scheme for biasing the S memory cell with a forward bias. Figure 13 is a circuit diagram showing the biasing scheme for biasing the S memory cell with a reverse bias. Figure 14 illustrates a repetitive read-verify-write cycle to move the memory cells into the data state. 15a through 15C are cross-sectional views showing stages in the formation of a memory level formed in accordance with an embodiment of the present invention. Figure 16 is a cross-sectional view of a diode and a resistive switching element that can be used in an alternate embodiment of the present invention. Figure m shows a diagram of a mixed-use memory array of a preferred embodiment. The memory unit operates as a single-programmed memory as early as 70' and - the two-group memory unit operates as a rewritable memory. unit. Figure = will be: a preferred embodiment of the mixed-use memory array diagram parental error group can be a single stylized memory unit and rewritable memory map 19, will be a preferred embodiment of the circuit bias Stylized-group memory unit. The display of a preferred embodiment of the circuit is not shown in Figure 2, and a bias voltage is used to program a set of memory cells. ', 圯向_ Illustrates the memory of the preferred embodiment. , 4 body array - the first part (four) save each record (four) single off state. #部(四)存母记赖 unit four data Figure 22 edge read good implementation of the memory array diagram, which is from the parent body page The flag bit indicates the portion of each memory cell and the four states of each memory cell. The heart of Figure 2 shows a better specific donor mode of the memory array of the embodiment, and the memory array The stored translation table indicates the portion of each memory bank 121888, doc-52-200811865 and the four states of each memory cell. Figure 24 is a diagram illustrating a memory array of a preferred embodiment, wherein The flag bit on the parent-physical page indicates that the two-character bear-only stylized portion of each memory unit, the two-state rewritable portion of each memory unit, and the four-state per memory unit can be single-programmed Part 25. Figure 25 depicts the use of wafer flags and poor wafers. Flowchart block preferred specific embodiment of the mechanism.

[Main component symbol description] 2 Polycrystalline semiconductor diode 4 Bottom heavily doped n-type region (Fig. 2) 4 Bottom heavily doped Ρ-type region (Fig. 8) 6 Essential region 8 Top heavily doped region (Fig. 2) 8 Top heavily doped n-type region (Fig. 8) 12 Bottom conductor 14 Dielectric rupture antifuse 16 Top conductor 100 Substrate 102 Insulation layer 104 Adhesive layer 106 Conductive layer 108 Dielectric material 109 Flat surface 110 Barrier layer 121888. Doc -53. 200811865 111 Diode 112 Bottom heavily doped region 114 Essential layer 116 Top heavily doped P-type region 117 Switchable memory device 118 Dielectric ruptured anti-fuse layer 120 Adhesive layer 122 Conductive layer 200 Conductor ( First conductor; conductor; bottom conductor) (Figs. 15a to 15c) 200 memory array (Fig. 17) 210 first group of memory units 220 second group of memory units 230, 250 may be programmed in a single block 240 260 rewritable section 270 flag bit 300 column 400 conductor (conductor rail; top conductor) A, A0, A1 word line B, BO, B1 bit line F, H semi-selected memory unit U not selected Memory unit M, P, R, S, V memory Ul unit of state information, U2, U3 non-selection of the memory cell 121888.doc -54 -

Claims (1)

200811865 X. Patent Application Range: !· A memory array comprising: a plurality of memory units operable as a single-programmed memory unit or a rewritable memory unit, each memory The unit includes a memory component including a semiconductor material configurable to one of at least three resistivity states, wherein when the memory cell operates as a single-programmable memory cell, the memory component is used a first resistivity state indicating a data state of the memory cell; but when the memory cell operates as a rewritable memory cell, the first resistivity state is not used to represent one of the memory cells Data state; wherein the plurality of memory cells comprise: a set of § hex elements, which operate as a single-programmed memory unit; and a second set of memory units that operate as rewritable memory unit. 2. The memory array of claim 1, wherein the first set of memory cells stores one or more of the following: content management bit, trim bit, manufacturer data, or formatted material. 3. A memory array as claimed, wherein the first set of memory cells is for programmatic data&apos; wherein the second set of memory cells is for user data. 4. The array of special rice of claim 1, wherein the first set of memory cells uses X resistivity states to represent respective data states, wherein the second 70 uses gamma resistivity states to represent gamma species The respective data is 121888.doc 200811865 state 'and where χ = γ. 5. The memory array of claim i, wherein the first set of memory cells uses x resistivity states to represent X respective data states, wherein the second set of memory cells uses gamma resistivity states Represents the respective data states of the gamma species' and where X矣γ. 6 · The array of the memory of the item 5, wherein the X system is 3 or more, and the γ system is 2. 7. The memory array of claim 5, wherein the lanthanide system is 3 or more, and the lanthanide system is 3 or more. The memory array of claim 1, wherein the plurality of memory cells comprise at least one of the following: an additional set of memory cells operating in a single-person private memory cell, Or an additional set of memory cells that operate as rewritable memory cells, wherein the first set of memory cells, the second set of memory cells, and the additional set of memory cells are interleaved such that two adjacent groups Memory cells are not both stylized or both rewritable. 9. The § </ RTI> array of claim 1, wherein the plurality of memory cells are organized in a plurality of pages, and wherein each page of the page includes at least one flag bit indicating whether the page is compliant Single stylized or rewritable. 1) The memory array of claim 9, wherein the at least one flag bit is stored as a single stylized data. 11. The memory array of claim 1 wherein the memory component comprises an antifuse in series with one of the semiconductor materials. 12. The memory array of claim 11, wherein the semiconductor material comprises a polycrystalline germanium diode. 121888.doc 200811865 13. The memory array of claim i, wherein the memory component comprises an antifuse, a binary metal oxide, and a polysilicon germanium isolation device. 14. The memory array of claim i, wherein the memory array comprises a single-chip three-dimensional memory array, wherein the plurality of memory cells are arranged in a plurality of memory levels, each memory level being formed Above a single substrate and without any interposer. 15·If requested! The memory array, wherein the single-programmed memory unit can only accept forward bias programming, and wherein the rewritable memory unit can accept both forward bias programming and reverse bias programming. 16. A memory array comprising: a plurality of memory cells, each memory cell operating as a memory cell programmed with a forward bias, or operating to be stylized with a reverse bias a memory unit; wherein the plurality of memory units include A first set of memory cells operable to program the memory cells; and a forward biased to a second set of memory cells to program the memory cells. It can operate as a reverse bias to two sets of memory cells. 17. The memory array of claim 16, wherein the first operation is to erase with a forward bias. Memory cell storage unit, trimming unit, 18. The memory array of claim 16, wherein the first one or more of the following items: content management bit manufacturer data or formatted poor material. The memory array of claim 16, wherein the first set of memory cells is for stylized data, wherein the second set of memory cells is for user data. 2. The memory array of claim 16, wherein the plurality of memory cells are organized in a plurality of pages, and wherein each page of data includes at least one flag bit indicating whether the page includes the first A group of memory cells or the second group of memory cells. 21. The memory array of claim 16, wherein each memory cell comprises a memory component comprising a semiconductor material of one of a configurable rate state, and wherein the := state is The first set of memory cells are used, but are not used by the second set of memory cells. The memory array of claim 16, wherein the memory array comprises a slice of a two-dimensional memory array, wherein the plurality of memory cells are arranged in a plurality of memory levels, each memory level being formed on a single substrate Above and without any interposer. 23. A method of using a memory array, the method comprising: 〇) providing a memory array, riding a field... A flat a L self-hidden array comprising a plurality of records, a body early memory, a mother memory file As a pre-programmed 4, early or rewritable memory, the memory component package includes a semiconductor element, a semiconductor h~, and a second resistivity state. Memory single; the early operation of the body is a memory state of the memory unit - the state of the resistivity state; but when the memory unit operates 121888.doc 200811865 is a rewritable memory unit When, - does not use the brother-resistivity state to indicate a memory of the memory element, (b) use - the first group of memory single (four) is a single-programmed memory unit; and 24. C) Use - the second set of memory cells as rewritable memory cells. The method of claim 23 is included in steps __ before: (8) and (4): testing a set of test memory cells in the memory array; Predicting that the first set of memory cells in the memory array will not be properly programmed as rewritable memory cells; and predicting that the second set of memory cells in the memory array will be properly programmed as rewritable Memory unit. 25. The method of claim 23, further comprising: stylizing one or more of the following items in the first set of memory units: content official bits, trim bits, manufacturer data, or formatting information. The method of claim 23, wherein the plurality of memory cells are organized in a plurality of pages, and wherein the method further comprises: staging at least one flag bit in each of the pages, It indicates whether a given page can be single-programmed or rewritable. 27. The method of claim 23, wherein the at least one flag bit is stored as a single stylized data. The method of claim 23, further comprising: in a memory device including the memory array, using a controller to determine the first group of memory cells and one of the second group of memory cells 121888. Doc 200811865 Address space. The method of claim 23, further comprising: a host of communication of a memory device of the memory array: determining an address space of the first group of memory cells and the second group of memory cells. 30. The method of claim 23, further comprising: ^Transport can be single-cut reduction element _ extra group memory - early 7G 'or operate as a rewritable memory unit - additional group memory unit' where two adjacent groups of memory cells are not both Can be single-programmed or both can be rewritten. The method of claim 23, wherein the memory array comprises a single-chip three-dimensional memory array, wherein the plurality of memory cells are arranged in a plurality of layers of the memory layer, each memory level being formed in a Above a single substrate and without any interposer. 32. The method of claim 23, wherein the single-programmed memory unit can only accept forward bias programming, and wherein the rewritable memory unit can accept forward bias programming and reverse bias programming Both. 121888.doc