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TW200818691A - An integrated quartz oscillator on an active electronic substrate - Google Patents

An integrated quartz oscillator on an active electronic substrate Download PDF

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Publication number
TW200818691A
TW200818691A TW96129187A TW96129187A TW200818691A TW 200818691 A TW200818691 A TW 200818691A TW 96129187 A TW96129187 A TW 96129187A TW 96129187 A TW96129187 A TW 96129187A TW 200818691 A TW200818691 A TW 200818691A
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TW
Taiwan
Prior art keywords
substrate
quartz
entire entire
electrode
oscillator
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Application number
TW96129187A
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Chinese (zh)
Inventor
David T Chang
Randall L Kubena
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Hrl Lab Llc
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Publication of TW200818691A publication Critical patent/TW200818691A/en

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  • Oscillators With Electromechanical Resonators (AREA)

Abstract

An oscillator having a quartz resonator, and a base wafer containing active electronics, wherein the quartz resonator is bonded directly to the base wafer.

Description

200818691 九、發明說明: I:發明所>»之技術領域3 關於聯合資助研究或開發之說明 本發明於美國國防部先進計劃署(DARA)授予之核可 5 編號DAAB07-02-C-P613下,受美國政府支援而完成。美國 政府對本發明具有特定權利。 相關申請案之交互參照 本申請案係有關2003年4月30日申請之美國專利申請 案第1〇/426,931號,其完整内容合併於本文中以供參考。 10 發明領域 本發明係有關一種振盪為。更特別是,本發明係有關 種石英谐振為,其直接與於一晶圓上形成之主動電子電 路黏合以形成一振盪器。 【先前技術3 15 發明背景200818691 IX. INSTRUCTIONS: I: TECHNICAL FIELD OF THE INSTITUTIONS>» Notes on Co-funded Research or Development The present invention was approved by the US Department of Defense Advanced Program (DARA) under the number 5 DAAB07-02-C-P613 Next, it was completed with the support of the US government. The U.S. Government has certain rights in the invention. CROSS-REFERENCE TO RELATED APPLICATIONS This application is hereby incorporated by reference in its entirety in its entirety in its entirety in the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire 10 FIELD OF THE INVENTION The present invention relates to an oscillation. More particularly, the present invention relates to quartz resonances that are directly bonded to an active electronic circuit formed on a wafer to form an oscillator. [Prior Art 3 15 Background of the Invention]

針對若干GPS、無線電、及雷達系統,其f要小型、低 功率、與高效能(低震動靈敏度、低溫漂移與低相位雜訊) 振盛器。此外’行動電話及電腦主機板針對類比及數位處 理,亦需要高度穩定的時鐘及計時參考點。當電話及電腦 2〇祕延伸進入多頻操作模式時,會增加對具有低功率要求 ^,時鐘頻率之需求。此依次增加可取代較高功率頻率 0成裔之一小排低功率振盪器的利益。 可使用混合技術來建構。 同^氧基,該等石英諧振 典型情況是,石英式振盪器 亦即使用包含傳導材料之各種不 5 200818691 =]片早石央(典型約1平方英°t)上製造、測試、以 一表面絲電針來钱於—喊㈣巾。較用之傳導 %乳基以低張力提供機械與電氣連接至該譜振器。因為益 處置晶圓使用於該等製造程序中,故該等諧振器需夠厚才 5 在處置及製造程序期間破裂。因為該頻率根據裁剪 吴式裝置之厚度而反向,此表示高於約100 MHz (或石英厚 度低於約10微米)之頻率證實很難以此方法來製造。此外= 針對^HF操作,該等譜振器、之維度顯著小於較大的裳置。 此減少该谐振器之等效電路參數並增加該電路對偏離電容 1〇之敏感度。典型情況是,UHF諧振器之該電容為〇」微微法 拉範圍内,而此需要寄生電容低於約〇.〇1微微法拉使其不 影響該振盪器之操作。因此,有必要降低該等偏離信號至 可管理之準位。 根據本揭不内容’即可整合具有主動電子電路之一言皆 15振器以形成一小型、低功率、以及高效能(低震動靈敏度、 低溫漂移與低相位雜訊)並具有降低的偏離信號之振盪器。 【發明内容】 發明概要 一種用於製造一振盪器之方法,該方法包含下列步 20 驟:提供具有一蝕刻孔穴之一第一基板;提供具有相對一 第二主要表面之一第一主要表面的一石英基板;將該石英 基板黏合該第一基板,其中一部分該第一主要表面處於該 孔穴之上方;沿著該第二主要表面削薄該石英基板;移除 該石英基板之一部分以曝露該第一基板之一部分並定義一 200818691 石英諧振器;將該石英諧振器黏合具有主動電子電路之一 基底晶圓;以及移除該第一基板,藉此釋放該石英諧振器。 圖式簡單說明 第1圖描繪一根據本揭示内容之振盪器; 5 第2圖描繪一振盪器回授迴路之一電路圖; 第3圖描繪根據本揭示内容使用之一石英基板、處置晶 圓、以及一基底晶圓; 第4圖描繪第3圖具有一孔穴之該處置晶圓; 第5圖描繪第3圖之該石英基板上的一光電阻; 10 第6圖描繪第3圖具有第一電極與金屬黏合襯墊之該石 英基板; 第7圖描繪第3圖黏合第4圖之該處置晶圓的該石英基 板; 第8圖描繪第7圖削薄之該石英基板; 15 第9圖描繪第8圖之該石英基板中形成的孔徑; 第10圖描繪第9圖之該石英基板上的第二電極與底部 金屬黏合襯墊; 第11圖描繪第10圖具有漸增厚度之該石英基板的該等 底部金屬黏合襯墊; 20 第12圖描繪已移除來定義該處置晶圓上之該諧振器的 該石英基板的一部分; 第13圖描繪黏合第3圖之該基底晶圓的該石英基板; 第14圖描繪從該處置晶圓釋放之該石英諧振器;For several GPS, radio, and radar systems, it is small, low power, and high performance (low vibration sensitivity, low temperature drift and low phase noise). In addition, mobile phones and computer motherboards require highly stable clock and timing reference points for analog and digital processing. When the phone and the computer are extended into the multi-frequency mode of operation, the need for a low power requirement ^, the clock frequency is increased. This in turn increases the benefits of a small row of low power oscillators that can replace one of the higher power frequencies. It can be constructed using hybrid techniques. The same as the oxy group, the quartz resonance is typically a quartz oscillator that is manufactured using a variety of conductive materials, including a conductive material, which is manufactured on a small stone (typically about 1 square inch °). The surface of the wire electroacupuncture comes to the money - shout (four) towel. More conductive than the % emulsion provides mechanical and electrical connection to the spectrometer with low tension. Because the benefit handling wafers are used in such manufacturing processes, the resonators need to be thick enough to break during disposal and manufacturing procedures. Since this frequency is reversed depending on the thickness of the tailored device, this indicates that frequencies above about 100 MHz (or quartz thicknesses below about 10 microns) prove to be difficult to fabricate in this way. In addition, for the ^HF operation, the dimensions of the spectral oscillators are significantly smaller than the larger ones. This reduces the equivalent circuit parameters of the resonator and increases the sensitivity of the circuit to the offset capacitance. Typically, this capacitance of the UHF resonator is within the 微"picofarad range, and this requires a parasitic capacitance of less than about 〇. 微1 picofarad does not affect the operation of the oscillator. Therefore, it is necessary to reduce these deviation signals to a manageable level. According to the present disclosure, it is possible to integrate a 15 oscillator with an active electronic circuit to form a small, low power, and high performance (low vibration sensitivity, low temperature drift and low phase noise) with reduced off-signal Oscillator. SUMMARY OF THE INVENTION A method for fabricating an oscillator, the method comprising the steps of: providing a first substrate having an etched aperture; providing a first major surface having one of a second major surface a quartz substrate; the quartz substrate is bonded to the first substrate, wherein a portion of the first major surface is above the aperture; the quartz substrate is thinned along the second major surface; and a portion of the quartz substrate is removed to expose the One portion of the first substrate defines a 200818691 quartz resonator; the quartz resonator is bonded to a substrate wafer having one of the active electronic circuits; and the first substrate is removed, thereby releasing the quartz resonator. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 depicts an oscillator in accordance with the present disclosure; 5 Figure 2 depicts a circuit diagram of an oscillator feedback loop; Figure 3 depicts the use of a quartz substrate, wafer handling, And a substrate wafer; FIG. 4 depicts the wafer having a hole in FIG. 3; FIG. 5 depicts a photo resistor on the quartz substrate of FIG. 3; The quartz substrate with the electrode and the metal bonding pad; FIG. 7 depicts the quartz substrate bonded to the wafer of FIG. 4 in FIG. 3; FIG. 8 depicts the quartz substrate thinned in FIG. 7; Depicting the aperture formed in the quartz substrate of FIG. 8; FIG. 10 depicts the second electrode and the bottom metal bonding pad on the quartz substrate of FIG. 9; FIG. 11 depicts the quartz having an increasing thickness of FIG. The bottom metal bonding pads of the substrate; 20 FIG. 12 depicts a portion of the quartz substrate that has been removed to define the resonator on the wafer; FIG. 13 depicts the bonding of the substrate wafer of FIG. The quartz substrate; Figure 14 depicts the treatment from The quartz resonator released by the wafer;

第15圖描繪一根據本揭示内容之示範UHF混合MEM S 7 200818691 振盪器; 第16圖描繪第15圖之該振盪器產生的一輸出信號之一 波形。 下列說明中,相同參考數字用於識別相同元件。此外, 5 該等圖式意欲以一圖形方式來繪示示範實施例之主要特 徵。該等圖式並不意欲繪示每一個實施態樣之每一特徵, 亦不意欲繪示該等繪示元件之相對維度並且不依標度來繪 製。 I:實施方式3 10 較佳實施例之詳細說明 本申請案揭示之一種程序,可用於使用低溫黏合技術 來將諧振器之一完全晶圓附接於一基板晶圓。此允許將諧 振器之一晶圓完全整合於含有一振盪器電路陣列之一晶圓 中以達到小尺寸及低成本。此外,處置晶圓技術之使用允 15 許該頻率超過由處理一單一石英晶圓(約100 MHz)所設定 之限制。由於該等頻率增加時,一適當標度裝置之電容值 減少,所以微小的寄生電容於較高頻率時會變為效能降級 的一主要來源。針對一晶圓之各種不同振盪器的高穩定及 可複製效能,藉由整合具有縮小化電子元件之該等諧振器 20 於晶片上,該等寄生效應可最小化。再者,整合允許小型、 快速、以及低功率溫度補償方法於該等諧振器附近實施。 此依序提供建構恆温振盪器快速暖機時間(針對大型振盪 器提供毫秒而非分鐘)的能力以及相當低的功率需求。最 後,相較於商業用較低頻振盪器,本申請案呈現之振盪器 8 200818691 已顯示較低的震動敏感度。此可能由於較高頻率操作所需 之堅硬懸臂的結構所致。 本揭示内容之一示範實施例中,第i圓揭示一種整合石 英諧振器20,其直接黏合具有主動電子電路4〇之一晶圓昶 以便形成一小型、低功率、與低相位雜訊振盪器1〇。該晶 圓30可由,例如,矽(Si)、矽鍺或第三至 成。第2圈描繪一振盪器回授迴路50之— 第五族之材料所組 電路圖,該迴路可 使用本揭示内容中揭示之該等技術來執行。 現將參照第3圈至第13圖來說明製造根據本 10 振盘1§ 10的一示範方法。 申請案之 /照第3圓,提供具有-第-表面61及—第二表面… -第-基板70(亦即’處置晶圓)、以及含有主動電子電路% 之-基底晶圓80的-石英基板60。該第—基板7〇可包含諸 如碎或石申化鎵之-材料。該實施例中,該第一基板7〇與該 15石英基板60兩者可以一 3吋或更大晶圓的型式來設置。Figure 15 depicts an exemplary UHF hybrid MEM S 7 200818691 oscillator in accordance with the present disclosure; Figure 16 depicts one of the waveforms of an output signal produced by the oscillator of Figure 15. In the following description, the same reference numerals are used to identify the same elements. Moreover, the drawings are intended to depict the main features of the exemplary embodiments in a graphical manner. The figures are not intended to depict each feature of each embodiment, and are not intended to depict the relative dimensions of the elements and are not drawn to scale. I: Embodiment 3 10 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A procedure disclosed in the present application can be used to attach a complete wafer of a resonator to a substrate wafer using a low temperature bonding technique. This allows a wafer of one of the resonators to be fully integrated into a wafer containing an array of oscillator circuits to achieve small size and low cost. In addition, the use of wafer handling technology allows the frequency to exceed the limits set by processing a single quartz wafer (approximately 100 MHz). As these frequencies increase, the capacitance of an appropriate scale device decreases, so small parasitic capacitance becomes a major source of performance degradation at higher frequencies. These parasitic effects can be minimized by integrating the resonators 20 with reduced electronic components on the wafer for the high stability and reproducibility of the various oscillators of a wafer. Furthermore, integration allows for small, fast, and low power temperature compensation methods to be implemented in the vicinity of such resonators. This provides the ability to build a constant temperature oscillator for fast warm-up time (milliseconds instead of minutes for large oscillators) and relatively low power requirements. Finally, the oscillator 8 200818691 presented in this application has shown lower vibration sensitivity than the commercial lower frequency oscillator. This may be due to the structure of the rigid cantilever required for higher frequency operation. In an exemplary embodiment of the present disclosure, the ith circle discloses an integrated quartz resonator 20 that directly bonds one of the active electronic circuits 4 to form a small, low power, low phase noise oscillator. 1〇. The crystal 30 can be, for example, germanium (Si), germanium or a third. The second circle depicts a circuit diagram of the oscillator feedback circuit 50, the material of the fifth family, which circuit can be implemented using the techniques disclosed in this disclosure. An exemplary method of manufacturing the plenum 10 according to the present tenth disc will now be described with reference to the third to thirteenth drawings. Application/Photo No. 3, provided with --surface 61 and - second surface - - substrate 70 (ie, 'treatment wafer), and substrate wafer 80 containing active electronic circuit % - Quartz substrate 60. The first substrate 7 can comprise a material such as a crumb or a gallium. In this embodiment, both the first substrate 7 and the 15 quartz substrate 60 may be provided in a pattern of one or more wafers.

如第4圖所示,該第-基板觀1分㈣開來建立一 孔穴75。祕刻孔穴75可以,例如,氫氣化鉀之—濕钱刻、 或使用具有-氣化物之-氣體的1反應離子姓刻來製 造。 20 制英基板之該第一表面61之後使用一剝離技術來 圖型化及金屬化。如第5圈所示,該剥離技術中,光電阻幻 之一薄層於該石英基板60之該第一表面的上圖型化。使用 平板印刷術,光電阻可於需要金屬化之區域中移除。該金 属之後可存放該光電阻63上以及移除該光電阻63之該等區 9 200818691 域中。如第6圖所示,該光電阻之後移除並僅於該石英基板 60之該第一表面61上的該等所需區域中留下金屬。圖型化 與金屬化期間,至少一個第一電極襯墊65存放於該石英基 板60之該第一表面61上。該第一電極襯墊65可由鈦、翻、 5 金、或鉻、韵、金之一結合來組成,並以該石英基板之 該第一表面61上的順序來存放。第6圖亦顯示該石英基板6❶ 之該第一表面61上的兩個互連金屬襯塾64。該等兩個互連 金屬襯墊64可由與該第一電極襯墊65相同的材料所組成。 稍後將說明該等兩個互連金屬襯墊64與該第一電極概塾65 10 之用途。 如第7圈所示,存放該互連金屬襯墊64與該第一電極襯 塾65後’該石英基板60可使用例如,商業上可講得之一ev 501晶圓黏合劑來黏合該蝕刻第一基板7〇。為了黏合該石英 基板60與該第一基板70,該石英基板6〇與該第一基板7〇會 15於一超音波洗滌系統中完全洗滌,其使用超音波來移除粒 子污染物。該等晶圓洗滌後,將其彼此接觸並進行退火程 序。由於矽醇(Si-Ο-Η)族之氫鍵黏合之後矽氧化物(Si_〇_Si) 之共價鍵黏合,所以該石英基板6〇與該第一基板7〇間之接 觸會形成一黏合。該石英基板6〇黏合該蝕刻第一基板7〇會 20使得該等互連襯塾64與該第一電極概塾㈣前位於該第一 基板70之該孔穴75中。 如第8圖所示,該石英基板60與雜刻第-基板70黏合 後,該石英基板60之該第二表面_經一削薄程序以取得 更薄之肖彳薄第二表面62a。為了削薄該石英基板 200818691 :二使用下列方法。例如,使用—機械重疊與拋光系統 來削薄該石英基板6G。機械重疊與拋光系統是㈣著名並 可從諸如祕科技之製造絲商業切得…^重疊愈 拋光系統中…拋光磁頭以-高速旋轉。該重疊盘抛光系 統亦包含驗分散該石英基_上之泥_ —対。她 光磁頭旋轉時,會與當中具有祕之該石英基板60接觸, 因而可平均料B英基_之—部分。該賴可由 氧化紹之化學物所組成以便將石英從該石英基板6〇中移 除0 10 另 範例中,例如,使用具有四氣化碳與六氟化硫之 反應離子㈣(岡,該石英基板心1分可被削薄。於 就IE機器中削薄時’使用業界熟於此技者皆知的光譜橢偏 儀或反射量測技術,該石英基板6G之厚度可受監控。使用 RIE削薄該石英基板6G後,該石英基板6G之表面會具有需修 正之瑕疵。此可藉由使用,例如,上述具有諸如二氧化石夕 或氧化鈽之化學物的機械重疊與拋光系統來達成,以便移 除約0.01-0.02微米之石英,接著使用氫氟化銨之一濕蝕刻 來將約0.G5微米之石英從該石英基板辦移除4可協助 確認一拋光、無缺點的石英基板6〇。 如第9圈所示,該石英基板6〇被削薄後,孔徑9〇可於該 石英基板60中產生。該孔徑9〇可使用業界著名之平板印刷 技術來產生。該孔徑90是蝕刻穿透該石英基板6〇至該等互 連襯墊64之接觸點。如第1〇圈所示,一旦該孔徑9〇產生, 使用上述用於沉積該等互連襯墊64之該剝離技術,該孔徑 11 200818691 9〇可被金屬化並且該石英基板⑽之該削薄第二表面62a會 被圖型化及金屬化。該金屬化步驟期間,互連襯墊66會沉 積於该孔徑90上方之該削薄第二表面❿上。該等互連概塾 66可由鈦翻、金、或路、翻、金之_結合來組成,並以 5該石英基板60之該削薄第二表面…上的順序來存放。 該等互連襯墊64、66透過該孔徑9〇連接。此外,如第 10圖所不’沉積該等互連襯墊66之步驟期間,—第二金屬 電極襯墊67被沉積。該第二金屬電極襯墊67可由與該等互 連襯墊66相同之材料所組成。 1〇 &第即所示,—旦該等互連崎66與該第二電極襯 塾67被>儿積,便可使用該上述剝離技術來執行另一圖型與 金屬化步驟,並施用該等互連襯塾66來增加該等互連概塾 66之該厚度。 如第I2圈所示,一旦該等互連襯塾的之該厚度增加, 15該石英基板60之一部分會被移除,因而產生一修正的石英 諳振Is 60a。該石英基板60之一部分可使用業界著名之平板 印刷及RIE技術來移除,以便將該石英基座分為個別的裝置 並判定該等石英譜振器60a所欲之維度。 該修正石英諧振器60a上之該等第一與第二電極襯墊 20 65、67施用橫跨該譜振器之—RF電場,於其自然諧振頻率 時將其驅動至振盪狀態。藉由磨損該第二電極襯墊67之一 部分,該石英諧振器6〇a之該諧振頻率可被調整。該第_電 極襯墊65可使用諸如聚焦離子束研磨或雷射磨損之著名技 術來磨損。 12 200818691 如上述參照第'3圖之詳細說明所提及,其設置一基底晶 圓80。該基底晶圓80可由,例如,石夕(Si)、石夕鍺或第三至第 五族之材料所組成,並可含有包含孔徑82之一氧化層81, 該孔徑82電氣連接該等主動電子電路85與傳導襯墊83。 5 如第13圖所示,該等互連襯墊66之該厚度增加後,該 θ白振器60a之该荨互連概塾66可使用,例如,一金姻熱壓縮 黏合方案,沿著黏合線98黏合該等傳導襯墊83。該金銦熱 壓縮黏合方案中,該石英諧振器60a、該等互連襯墊66、該 等傳導襯墊83、以及該基底晶圓80會於壓力不超過1〇·4托爾 10之真二中加熱至約100 C之溫度。之後該等互連概塾66及 該等傳導襯墊83壓在一起,而以大約1 MPa之壓力來洩壓。 如第13圖所示,此將該等傳導襯墊83及該等互連襯墊的熔 接一起。 該等互連襯墊66及該等傳導襯墊83之黏合提供從該等 15傳導襯塾83至該等第一與第二電極槻塾65、67之電氣接 取。如第14圓所示,該等互連襯墊66黏合該等傳導襯墊83 之後使用濕與乾钱刻技術之一結合,第一基座7〇(處置晶 圓)會從剩餘結構中移除,藉此可取得一振盪器。 4專第一與第二電極襯墊65、67之用途是用於從該等 20傳導襯塾83接收-電氣信號,該信號可以一電場來偏壓或 驅動该石英諧振器6〇a。該電氣信號較佳是一Ac信號。該 電氣信號由該等第一與第二電極襯墊65、67接收時,該修 正石英諧振器60a會施予一壓力。該壓力藉由該著名的壓電 效應而刺激該修正石英諧振器6〇a之該機械諧振頻率,因而 13 200818691 造成该修正石英諧振器60a於其諧振頻率處振盪。此外,亦 可使用遠等第-與第二電極襯墊65、67來感測該修正石英 堦振為60a相對一特定平面(未顯示)之移動。一旦該修正石 英諧振器60a於其諧振頻率處振盪,其可於與其諧振頻率相 5同之一頻率處用來驅動其他電氣元件。 很明顯地,根據意欲修改該晶圓8〇之該頂部表面的程 度,可使用其他變化型態及程序步驟來執行將該諧振器2〇 附接該基底晶圓30。 第15圖描繪一根據本揭示内容之示範111117混合mems 1〇振盪器200。該等石英MEMS諧振器210位於緊附該銅電鍍 Duroid表面女裝卡225之一石夕(Si)基座220上。該銅電錢可從 該等電路元件附近移除以減少寄生電容。第16圖描繪該振 盪态200使用326 MHz碟片諧振器21〇,透過輸出226產生的 一輸出信號之一波形。 15 上述示範及較佳實施例之詳細說明是為了根據規則要 求的舉例說明及揭示内容而呈現。本案並無意欲窮舉或限 制本發明於上述精確的型式中,而只是使業界之熟於此技 者了解本發明如何適用於一特定使用方式或實施態樣。很 明顯地對業界熟於此技之業者而言,本案可作其他修改與 2〇變化型態。該等示範實施例之說明並不意欲視為限制,其 可具有包括之容差、特徵維度、特定操作條件、工程規格 說明、等等,並可於實施態樣之間改變或隨業界最新進技 術而改變,而且不因此意味任何限制。申請人已使本揭示 内容成為最新技術,但亦考量到進步空間,而未來之該等 14 200818691 調適可將該等進步空間列入考慮,亦即隨時根據最新技 術。本發明之範疇意欲由所寫之申請專利範圍及可應用之 等效元件來加以定義。除非明確指定,否則參照該單一數 量中之一要求元件並不意欲表示為“一個或僅有一個”。此 5 外,不論該揭示内容之一元件、成分、方法或程序步驟於 該等申請專利範圍中是否明確列舉,該元件、成分、方法 或步驟皆不意欲公諸於世。除非本文不要求之元件使用該 片語“用以…之裝置”來明確列舉,否則該元件應視為在35 U.S.C.第112節第六段條款之下,而除非本文未提及之方法 10 或程序步驟使用該片語“用以…之步驟”來明確列舉,否則 該步驟、或該等步驟應視為該等條款之下。 L圖式簡單說明3 第1圖描繪一根據本揭示内容之振盪器; 第2圖描繪一振盪器回授迴路之一電路圖; 15 第3圖描繪根據本揭示内容使用之一石英基板、處置晶 圓、以及一基底晶圓; 第4圖描繪第3圖具有一孔穴之該處置晶圓; 第5圖描繪第3圖之該石英基板上的一光電阻; 第6圖描繪第3圖具有第一電極與金屬黏合襯墊之該石 20 英基板; 第7圖描繪第3圖黏合第4圖之該處置晶圓的該石英基 板; 第8圖描繪第7圖削薄之該石英基板; 第9圖描繪第8圖之該石英基板中形成的孔徑; 15 200818691 第10圖描繪第9圖之該石英基板上的第二電極與底部 金屬黏合襯墊; 第11圖描繪第10圖具有漸增厚度之該石英基板的該等 底部金屬黏合襯塾; 5 第12圖描繪已移除來定義該處置晶圓上之該諧振器的 該石英基板的一部分; 第13圖描繪黏合第3圖之該基底晶圓的該石英基板; 第14圖描繪從該處置晶圓釋放之該石英諧振器; 第15圖描繪一根據本揭示内容之示範u H F混合Μ E M S 10 振盪器; 第16圖描繪第15圖之該振盪器產生的一輸出信號之一 波形。 【主要元件符號說明】 10···低相雜訊振盪器 67·.·第二電極襯墊 20…整合石英諧振器 70··.第一基板 30…晶圓 75…姓刻孔穴 40、85···主動電子電路 80···基底晶圓 50···振盪器回授迴路 81···氧化層 60.··石英基板 82、90···孔徑 60a···修改之石英諧振器 83···傳導襯墊 61··.第一表面 98···黏合線 62···第二表面 200...UHF混合MEMS振盪器 62a···較薄第二表面 210···石英MEMS諧振器 63…光電阻 220.··>ε夕基板 64、66…互連金屬襯墊 225 · · .Duroid表面安裝卡 65···第一電極襯墊 226…輸出 16As shown in Fig. 4, the first substrate is opened (1) to form a hole 75. The secret hole 75 can be made, for example, by the hydrogenation of potassium hydroxide, or by the use of a reactive ion having a gas-gas. The first surface 61 of the 20-inch substrate is then patterned and metallized using a lift-off technique. As shown in the fifth lap, in the stripping technique, a thin layer of photoresist is patterned on the first surface of the quartz substrate 60. Using lithography, the photoresist can be removed in areas where metallization is required. The metal can then be stored on the photo resistor 63 and in the region of the region 9 200818691 where the photo resistor 63 is removed. As shown in Fig. 6, the photo resistor is removed and metal is left only in the desired regions on the first surface 61 of the quartz substrate 60. During patterning and metallization, at least one first electrode pad 65 is deposited on the first surface 61 of the quartz substrate 60. The first electrode pad 65 may be composed of titanium, turned, 5 gold, or a combination of chrome, rhyme, and gold, and stored in the order of the first surface 61 of the quartz substrate. Figure 6 also shows two interconnected metal backings 64 on the first surface 61 of the quartz substrate 6''. The two interconnect metal pads 64 may be composed of the same material as the first electrode pad 65. The use of the two interconnect metal pads 64 and the first electrode profile 65 10 will be described later. As shown in the seventh lap, after the interconnect metal pad 64 and the first electrode pad 65 are stored, the quartz substrate 60 can be bonded using, for example, one of the commercially available ev 501 wafer adhesives. The first substrate 7 is. In order to bond the quartz substrate 60 and the first substrate 70, the quartz substrate 6 and the first substrate 7 are completely washed in an ultrasonic cleaning system, which uses ultrasonic waves to remove particulate contaminants. After the wafers are washed, they are brought into contact with each other and subjected to an annealing process. Since the covalent bond of the cerium oxide (Si_〇_Si) after the hydrogen bonding of the sterol (Si-Ο-Η) group is bonded, the contact between the quartz substrate 6〇 and the first substrate 7 is formed. A bond. The quartz substrate 6 is bonded to the etched first substrate 7 such that the interconnect pads 64 and the first electrode are located in the holes 75 of the first substrate 70. As shown in Fig. 8, after the quartz substrate 60 is bonded to the etched first substrate 70, the second surface of the quartz substrate 60 is subjected to a thinning process to obtain a thinner thin second surface 62a. In order to thin the quartz substrate 200818691: Two use the following method. For example, the quartz substrate 6G is thinned using a mechanical overlap and polishing system. The mechanical overlap and polishing system is (4) famous and can be cut from the silk business of the technology such as Mi... The overlap is in the polishing system... The polishing head is rotated at high speed. The overlapping disc polishing system also includes dispersing the mud on the quartz base. When the optical head rotates, it will be in contact with the quartz substrate 60 which has the secret, so that the portion of the B-base can be averaged. The ruthenium may be composed of a oxidized chemical to remove quartz from the quartz substrate 6 0. In another example, for example, a reactive ion having four gasified carbon and sulphur hexafluoride (four) is used. The substrate core 1 can be thinned. When thinning in an IE machine, the thickness of the quartz substrate 6G can be monitored using a spectral ellipsometer or reflection measurement technique well known in the art. After the quartz substrate 6G is thinned, the surface of the quartz substrate 6G may have a defect to be corrected. This can be achieved by using, for example, the above-described mechanical overlap and polishing system having a chemical such as silica dioxide or cerium oxide. In order to remove about 0.01-0.02 micron quartz, followed by wet etching using one of ammonium hydroxide to remove about 0. G5 micron quartz from the quartz substrate 4 can help confirm a polished, defect-free quartz substrate. 6. As shown in the ninth circle, after the quartz substrate 6 is thinned, an aperture 9 〇 can be generated in the quartz substrate 60. The aperture 9 〇 can be produced using the well-known lithographic technique of the industry. Is etching through the quartz The plate 6 is connected to the contact points of the interconnect pads 64. As shown in the first turn, once the aperture 9 is generated, the stripping technique described above for depositing the interconnect pads 64 is used, the aperture 11 200818691 9 can be metallized and the thinned second surface 62a of the quartz substrate (10) can be patterned and metallized. During the metallization step, the interconnect pad 66 is deposited over the aperture 90. The second surface is formed by a combination of titanium flip, gold, or a combination of road, turn, and gold, and in the order of 5 on the thinned second surface of the quartz substrate 60. The interconnect pads 64, 66 are connected through the apertures 9. Further, during the step of depositing the interconnect pads 66 as shown in FIG. 10, the second metal electrode pads 67 are deposited. The second metal electrode pad 67 may be composed of the same material as the interconnect pads 66. As shown in the figure, the interconnected wires 66 and the second electrode pad 67 are >, the above stripping technique can be used to perform another pattern and metallization step, and the interconnect liners are applied 66 to increase the thickness of the interconnects 66. As shown in the circle I2, once the thickness of the interconnective liners increases, a portion of the quartz substrate 60 is removed, thereby producing a correction. Quartz oscillating Is 60a. A portion of the quartz substrate 60 can be removed using industry-famous lithography and RIE techniques to separate the quartz pedestal into individual devices and determine what the quartz crystal oscillator 60a desires. Dimensions. The first and second electrode pads 20 65, 67 on the modified quartz resonator 60a apply an RF electric field across the oscillator to drive it to an oscillating state at its natural resonant frequency. The resonance frequency of the quartz resonator 6A can be adjusted by wearing a portion of the second electrode pad 67. The first electrode pad 65 can be worn using well known techniques such as focused ion beam milling or laser abrading. 12 200818691 As mentioned above with reference to the detailed description of Fig. 3, a base crystal circle 80 is provided. The base wafer 80 may be composed of, for example, Shi Xi (Si), Shi Xi Yu or materials of the third to fifth groups, and may include an oxide layer 81 including an aperture 82 electrically connected to the active Electronic circuit 85 and conductive pad 83. 5 As shown in FIG. 13, after the thickness of the interconnect pads 66 is increased, the interconnector outline 66 of the θ white vibrator 60a can be used, for example, a Jincheng thermal compression bonding scheme along the bonding line. 98 is bonded to the conductive pads 83. In the gold-indium thermal compression bonding scheme, the quartz resonator 60a, the interconnect pads 66, the conductive pads 83, and the base wafer 80 may have a pressure of no more than 1 〇 4 tor 10 The second is heated to a temperature of about 100 C. The interconnects 66 and the conductive pads 83 are then pressed together to relieve pressure at a pressure of about 1 MPa. As shown in Fig. 13, this conductive pad 83 and the interconnect pads are welded together. The bonding of the interconnect pads 66 and the conductive pads 83 provides electrical access from the 15 conductive pads 83 to the first and second electrodes 65, 67. As shown by the 14th circle, the interconnect pads 66 are bonded to the conductive pads 83 and then combined with one of the wet and dry etching techniques, the first pedestal 7 (handling wafer) is moved from the remaining structure. In addition, an oscillator can be obtained. The purpose of the first and second electrode pads 65, 67 is to receive an electrical signal from the 20 conductive pads 83 which can bias or drive the quartz resonator 6A with an electric field. The electrical signal is preferably an Ac signal. When the electrical signal is received by the first and second electrode pads 65, 67, the modified quartz resonator 60a applies a pressure. The pressure stimulates the mechanical resonance frequency of the modified quartz resonator 6a by the well-known piezoelectric effect, and thus 13200818691 causes the modified quartz resonator 60a to oscillate at its resonance frequency. Alternatively, the far-first and second electrode pads 65, 67 can be used to sense the movement of the modified quartz oscillating vibration 60a relative to a particular plane (not shown). Once the modified quartz resonator 60a oscillates at its resonant frequency, it can be used to drive other electrical components at a frequency that is at the same frequency as its resonant frequency. Clearly, depending on the degree of modification of the top surface of the wafer 8 Å, other variations and program steps can be used to perform attaching the resonator 2 to the base wafer 30. Figure 15 depicts an exemplary 111117 hybrid MEMS oscillator 200 in accordance with the present disclosure. The quartz MEMS resonators 210 are located on a Shih (Si) pedestal 220 attached to one of the copper plated Duroid surface women's cards 225. The copper money can be removed from the vicinity of the circuit components to reduce parasitic capacitance. Figure 16 depicts a waveform of an output signal produced by the oscillating state 200 using the 326 MHz disc resonator 21A through the output 226. 15 The detailed description of the above exemplary and preferred embodiments is presented for purposes of illustration and description of the claims. The present invention is not intended to be exhaustive or to limit the invention to the precise forms described above, but only to those skilled in the art to understand how the invention can be applied to a particular use or implementation. Obviously, the industry can make other modifications and changes to the industry. The illustrations of the exemplary embodiments are not intended to be limiting, and may include tolerances, feature dimensions, specific operating conditions, engineering specifications, and the like, and may vary between implementations or with the industry. Technology changes and does not therefore imply any limitations. The Applicant has made this disclosure the latest technology, but it also considers the room for improvement, and the future adjustments of these 2008 14691 can take into account these areas of progress, that is, at any time based on the latest technology. The scope of the invention is intended to be defined by the scope of the appended claims and the applicable equivalents. The requirement for an element to refer to one of the single quantities is not intended to be "one or only one" unless explicitly stated otherwise. In addition, it is not intended that the elements, components, methods, or procedures of the present disclosure are intended to be disclosed. Unless the element is not required to be explicitly recited in the phrase "means for", the element shall be deemed to be under 35 USC Section 112, paragraph 6, unless method 10 or The procedural steps are explicitly recited using the phrase "steps for", otherwise the steps, or steps, should be considered as such. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts an oscillator in accordance with the present disclosure; FIG. 2 depicts a circuit diagram of an oscillator feedback loop; 15 FIG. 3 depicts the use of a quartz substrate, a handle crystal, in accordance with the present disclosure. a circle, and a base wafer; FIG. 4 depicts the wafer having a hole in FIG. 3; FIG. 5 depicts a photo resistor on the quartz substrate of FIG. 3; a quartz 20-inch substrate with an electrode and a metal bonding pad; FIG. 7 depicts a third substrate bonded to the quartz wafer of the processing wafer of FIG. 4; and FIG. 8 depicts a thinned quartz substrate of FIG. Figure 9 depicts the aperture formed in the quartz substrate of Figure 8; 15 200818691 Figure 10 depicts the second electrode and bottom metal bond pad on the quartz substrate of Figure 9; Figure 11 depicts Figure 10 with increasing The bottom metal bonded backing of the quartz substrate of thickness; 5 FIG. 12 depicts a portion of the quartz substrate that has been removed to define the resonator on the handle wafer; FIG. 13 depicts the bonding of FIG. The quartz substrate of the base wafer; Figure 14 depicts The quartz resonator released from the handle wafer; FIG. 15 depicts an exemplary u HF hybrid Μ EMS 10 oscillator in accordance with the present disclosure; and FIG. 16 depicts one of the output signals generated by the oscillator of FIG. Waveform. [Description of main component symbols] 10···low-phase noise oscillator 67·.·second electrode pad 20...integrated quartz resonator 70··.first substrate 30...wafer 75...lasting hole 40,85 ···Active electronic circuit 80···Base wafer 50···Oscillator feedback circuit 81···Oxide layer 60···Quartz substrate 82, 90···Aperture 60a···Modified quartz resonator 83···conductive pad 61··. first surface 98···bonding line 62···second surface 200...UHF hybrid MEMS oscillator 62a···thin second surface 210···quartz MEMS resonator 63... Photoresistor 220.··> Essence substrate 64, 66... Interconnect metal pad 225 · · .Duroid surface mount card 65···First electrode pad 226...Output 16

Claims (1)

200818691 十、申請專利範圍: 1. 一種用於製造一振盪器之方法,該方法包含下列步驟: 提供具有一蝕刻孔六之一第一基板; 提供具有相對一第二主要表面之一第一主要表面 5 的一石英基板; 將該石英基板黏合該第一基板,其中一部分該第一 主要表面處於該孔穴之上方; 沿著該第二主要表面削薄該石英基板; 移除該石英基板之一部分以曝露該第一基板之一 10 部分並界定一石英諧振器; 將該石英諧振器黏合具有主動電子電路之一基底 晶圓;以及 移除該第一基板,藉此釋放該石英譜振器。 2. 如申請專利範圍第1項之方法,其中削薄該石英基板之 15 該步驟將該石英基板削薄至少於十微米之一厚度。 3. 如申請專利範圍第1項之方法,其中該第一基板包含從 矽及砷化鎵組成之該群組中選定的一元件。 4. 如申請專利範圍第1項之方法,其中該基底晶圓包含從 矽、第三至第五族元素、及矽鍺組成之該群組中選定的 20 一元件。 5. 如申請專利範圍第1項之方法,其中該基底晶圓包含: 一含有孔徑之氧化層,其電氣連接該等主動電子電 路與該氧化層支撐之至少一個傳導襯墊。 6. 如申請專利範圍第5項之方法,其中該石英基板包含: 17 200818691 一相對一第二表面之第—表面; 該第一表面上之至少一第一電極;以及 該第二表面上之至少—第二電極。 5 10 15 7·如申請專利範圍第6項之方法,其中該石英基板更包含 連接至該至少-第-電極之至少_孔徑,其中該至少— 孔控填滿一金屬。 8·如申請專利範圍第7項之方法,其中將該石英基板與該 基底晶圓之該黏合包含將該至少一傳導襯墊黏合至該 至夕帛―電極’藉此允許_信號流過該至少—傳導概 墊與該至少一第二電極之間。 9. 如申請專· @第7項之方法,其中該至少—調和襯塾 會磨損來調整該諧振頻率。 10. =申料利範圍第7項之方法,其中該調和襯墊是該至 少一第一電極與該至少一第二電極其中之一。 U· —種振盪器,包含·· 一石英諧振器;以及 3有主動電子電路之基底晶圓,其中該石英譜振 裔係與該基底晶圓黏合。 12:申請專利範圍糾項之振盪器,其中該基底晶圓包含 攸石夕、第三至第五族元素、及補組成之輯組甲選定 的一元件。 13.:申請專利範圍糾項之振蘯器,其中該基底晶圓更包 含電氣連接至該等主動電子電路之至少一傳導觀塾。 14·如申料利_第13項之㈣器,其巾該石英基板包 18 200818691 含: 一相對一第二表面之第一表面; 該第一表面上之至少一第一電極;以及 該第二表面上之至少一第二電極。 5 15.如申請專利範圍第14項之振盪器,其中該石英基板更包 含連接至該至少一第一電極之至少一孔徑,其中該至少 一孔徑填滿一金屬。 16. 如申請專利範圍第15項之振盪器,其中該基底基板與該 石英諧振器間之該黏合,包含該傳導襯墊與該至少一第 10 二電極間之一黏合。 17. 如申請專利範圍第16項之振盪器,其中該頻率可藉由修 整該第一電極之該厚度來調整。 18. —種振盪器製造方法,該方法包含下列步驟: 提供具有一蝕刻孔穴之一第一基板; 15 提供具有相對一第二主要表面之一第一主要表面 的一石英基板; 將該石英基板黏合該第一基板,其中該第一主要表 面之一部分係處於該孔穴之上方; 沿著該第二主要表面削薄該石英基板; 20 移除該石英基板之一部分以曝露該第一基板之一 部分並界定一石英諧振器; 將該石英諧振器黏合具有主動電子電路之一基底 晶圓;以及 移除該第一基板,藉此釋放該石英諧振器; 19 200818691 ♦ 其中該基底晶圓包含: 一含有孔徑之介電層,其電氣連接該等主動電子電 路與由該介電層支撐之數個傳導襯墊。 20200818691 X. Patent Application Range: 1. A method for manufacturing an oscillator, the method comprising the steps of: providing a first substrate having an etched hole six; providing a first main having a second major surface a quartz substrate of the surface 5; bonding the quartz substrate to the first substrate, wherein a portion of the first major surface is above the aperture; thinning the quartz substrate along the second major surface; removing a portion of the quartz substrate Exposing a portion of the first substrate 10 and defining a quartz resonator; bonding the quartz resonator to a substrate wafer having one of the active electronic circuits; and removing the first substrate, thereby releasing the quartz crystal oscillator. 2. The method of claim 1, wherein the step of thinning the quartz substrate is performed by thinning the quartz substrate by at least one of ten microns. 3. The method of claim 1, wherein the first substrate comprises a selected one of the group consisting of germanium and gallium arsenide. 4. The method of claim 1, wherein the base wafer comprises a selected one of the group consisting of: 矽, a third to a fifth group element, and 矽锗. 5. The method of claim 1, wherein the substrate wafer comprises: an oxide layer having an aperture electrically connected to the active electronic circuit and the at least one conductive pad supported by the oxide layer. 6. The method of claim 5, wherein the quartz substrate comprises: 17 200818691 a first surface opposite the second surface; at least one first electrode on the first surface; and the second surface At least - the second electrode. The method of claim 6, wherein the quartz substrate further comprises at least an aperture connected to the at least - the first electrode, wherein the at least - the aperture is filled with a metal. 8. The method of claim 7, wherein the bonding the quartz substrate to the base wafer comprises bonding the at least one conductive pad to the 至-electrode to thereby allow a signal to flow through the At least - between the conductive pad and the at least one second electrode. 9. If the method of applying the @ @第7 item is applied, the at least the lining of the lining will wear to adjust the resonant frequency. 10. The method of claim 7, wherein the conditioning pad is one of the at least one first electrode and the at least one second electrode. An oscillator comprising: a quartz resonator; and a base wafer having an active electronic circuit, wherein the quartz crystal system is bonded to the base wafer. 12: An oscillator for applying for a patent range correction, wherein the base wafer comprises a component selected from the group of the 攸石夕, the third to fifth elements, and the composing group A. 13. A vibrator for applying for a patent range correction, wherein the base wafer further comprises at least one conductive view electrically connected to the active electronic circuits. 14. The apparatus according to claim 13, wherein the quartz substrate package 18 200818691 comprises: a first surface opposite to a second surface; at least one first electrode on the first surface; and the first At least one second electrode on the two surfaces. 5. The oscillator of claim 14 wherein the quartz substrate further comprises at least one aperture connected to the at least one first electrode, wherein the at least one aperture fills a metal. 16. The oscillator of claim 15 wherein the bonding between the base substrate and the quartz resonator comprises bonding the conductive pad to one of the at least one 10th electrode. 17. The oscillator of claim 16 wherein the frequency is adjustable by modifying the thickness of the first electrode. 18. An oscillator manufacturing method comprising the steps of: providing a first substrate having an etched aperture; 15 providing a quartz substrate having a first major surface opposite a second major surface; Bonding the first substrate, wherein a portion of the first major surface is above the hole; thinning the quartz substrate along the second major surface; 20 removing a portion of the quartz substrate to expose a portion of the first substrate And defining a quartz resonator; bonding the quartz resonator to a base wafer having an active electronic circuit; and removing the first substrate, thereby releasing the quartz resonator; 19 200818691 ♦ wherein the base wafer comprises: A dielectric layer having an aperture electrically connecting the active electronic circuitry to a plurality of conductive pads supported by the dielectric layer. 20
TW96129187A 2006-08-08 2007-08-08 An integrated quartz oscillator on an active electronic substrate TW200818691A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102545814A (en) * 2010-12-10 2012-07-04 原子能和能源替代品委员会 Process for fabricating an acoustic wave resonator comprising a suspended membrane
CN105280637A (en) * 2014-07-18 2016-01-27 精工爱普生株式会社 Circuit device, electronic apparatus and moving object
TWI645671B (en) * 2013-12-24 2018-12-21 日商精工愛普生股份有限公司 Electronic component, electronic apparatus, and moving object, and oven controlled crystal oscillator

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102545814A (en) * 2010-12-10 2012-07-04 原子能和能源替代品委员会 Process for fabricating an acoustic wave resonator comprising a suspended membrane
TWI645671B (en) * 2013-12-24 2018-12-21 日商精工愛普生股份有限公司 Electronic component, electronic apparatus, and moving object, and oven controlled crystal oscillator
CN105280637A (en) * 2014-07-18 2016-01-27 精工爱普生株式会社 Circuit device, electronic apparatus and moving object
CN105280637B (en) * 2014-07-18 2020-07-07 精工爱普生株式会社 Circuit devices, electronic equipment and moving bodies

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