[go: up one dir, main page]

TW200741888A - Process for forming an electronic device including discontinuous storage elements - Google Patents

Process for forming an electronic device including discontinuous storage elements

Info

Publication number
TW200741888A
TW200741888A TW095127219A TW95127219A TW200741888A TW 200741888 A TW200741888 A TW 200741888A TW 095127219 A TW095127219 A TW 095127219A TW 95127219 A TW95127219 A TW 95127219A TW 200741888 A TW200741888 A TW 200741888A
Authority
TW
Taiwan
Prior art keywords
forming
storage elements
discontinuous storage
electronic device
device including
Prior art date
Application number
TW095127219A
Other languages
English (en)
Inventor
Gowrishankar L Chindalore
Craig T Swift
Paul A Ingersoll
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200741888A publication Critical patent/TW200741888A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6893—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6894—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having one gate at least partly in a trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/696—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having at least one additional gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/697—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having trapping at multiple separated sites, e.g. multi-particles trapping sites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/699—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having the gate at least partly formed in a trench
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/701—Integrated with dissimilar structures on a common substrate
    • Y10S977/707—Integrated with dissimilar structures on a common substrate having different types of nanoscale structures or devices on a common substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
TW095127219A 2005-07-25 2006-07-25 Process for forming an electronic device including discontinuous storage elements TW200741888A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/188,939 US7211487B2 (en) 2005-07-25 2005-07-25 Process for forming an electronic device including discontinuous storage elements

Publications (1)

Publication Number Publication Date
TW200741888A true TW200741888A (en) 2007-11-01

Family

ID=37679603

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095127219A TW200741888A (en) 2005-07-25 2006-07-25 Process for forming an electronic device including discontinuous storage elements

Country Status (7)

Country Link
US (1) US7211487B2 (zh)
EP (1) EP1911077A4 (zh)
JP (1) JP2009503860A (zh)
KR (1) KR20080035579A (zh)
CN (1) CN101253608B (zh)
TW (1) TW200741888A (zh)
WO (1) WO2007014118A2 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7394686B2 (en) * 2005-07-25 2008-07-01 Freescale Semiconductor, Inc. Programmable structure including discontinuous storage elements and spacer control gates in a trench
US7619270B2 (en) 2005-07-25 2009-11-17 Freescale Semiconductor, Inc. Electronic device including discontinuous storage elements
US7642594B2 (en) 2005-07-25 2010-01-05 Freescale Semiconductor, Inc Electronic device including gate lines, bit lines, or a combination thereof
US7262997B2 (en) 2005-07-25 2007-08-28 Freescale Semiconductor, Inc. Process for operating an electronic device including a memory array and conductive lines
KR100654560B1 (ko) * 2005-12-27 2006-12-05 동부일렉트로닉스 주식회사 플래시 메모리 소자 및 그 제조 방법
US7592224B2 (en) 2006-03-30 2009-09-22 Freescale Semiconductor, Inc Method of fabricating a storage device including decontinuous storage elements within and between trenches
US7651916B2 (en) 2007-01-24 2010-01-26 Freescale Semiconductor, Inc Electronic device including trenches and discontinuous storage elements and processes of forming and using the same
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
WO2009148695A2 (en) * 2008-06-02 2009-12-10 Maxpower Semiconductor Inc. Edge termination for semiconductor devices
JP2010021492A (ja) * 2008-07-14 2010-01-28 Toshiba Corp 不揮発性半導体記憶装置およびその制御方法
US7692972B1 (en) 2008-07-22 2010-04-06 Actel Corporation Split gate memory cell for programmable circuit device
KR101095802B1 (ko) * 2010-01-07 2011-12-21 주식회사 하이닉스반도체 반도체 소자 및 그의 제조 방법
US8951892B2 (en) 2012-06-29 2015-02-10 Freescale Semiconductor, Inc. Applications for nanopillar structures
CN106486529A (zh) * 2015-08-24 2017-03-08 联华电子股份有限公司 存储器元件及其制造方法

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860070A (en) * 1987-01-09 1989-08-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device comprising trench memory cells
US5705415A (en) * 1994-10-04 1998-01-06 Motorola, Inc. Process for forming an electrically programmable read-only memory cell
TW326553B (en) * 1996-01-22 1998-02-11 Handotai Energy Kenkyusho Kk Semiconductor device and method of fabricating same
US5721448A (en) * 1996-07-30 1998-02-24 International Business Machines Corporation Integrated circuit chip having isolation trenches composed of a dielectric layer with oxidation catalyst material
US5824580A (en) * 1996-07-30 1998-10-20 International Business Machines Corporation Method of manufacturing an insulated gate field effect transistor
US5780341A (en) * 1996-12-06 1998-07-14 Halo Lsi Design & Device Technology, Inc. Low voltage EEPROM/NVRAM transistors and making method
US5969383A (en) * 1997-06-16 1999-10-19 Motorola, Inc. Split-gate memory device and method for accessing the same
US5914523A (en) * 1998-02-17 1999-06-22 National Semiconductor Corp. Semiconductor device trench isolation structure with polysilicon bias voltage contact
US6087222A (en) * 1998-03-05 2000-07-11 Taiwan Semiconductor Manufacturing Company Method of manufacture of vertical split gate flash memory device
US6074954A (en) * 1998-08-31 2000-06-13 Applied Materials, Inc Process for control of the shape of the etch front in the etching of polysilicon
US6255166B1 (en) * 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
US6172905B1 (en) * 2000-02-01 2001-01-09 Motorola, Inc. Method of operating a semiconductor device
US6320784B1 (en) * 2000-03-14 2001-11-20 Motorola, Inc. Memory cell and method for programming thereof
US6307782B1 (en) * 2000-04-03 2001-10-23 Motorola, Inc. Process for operating a semiconductor device
JP4834897B2 (ja) * 2000-05-02 2011-12-14 ソニー株式会社 不揮発性半導体記憶装置およびその動作方法
KR100821456B1 (ko) * 2000-08-14 2008-04-11 샌디스크 쓰리디 엘엘씨 밀집한 어레이 및 전하 저장 장치와, 그 제조 방법
US6936887B2 (en) * 2001-05-18 2005-08-30 Sandisk Corporation Non-volatile memory cells utilizing substrate trenches
JP2003046003A (ja) * 2001-07-26 2003-02-14 Sony Corp 不揮発性半導体メモリ装置とその動作方法
TW546840B (en) * 2001-07-27 2003-08-11 Hitachi Ltd Non-volatile semiconductor memory device
KR100400079B1 (ko) * 2001-10-10 2003-09-29 한국전자통신연구원 트랜치 게이트 구조를 갖는 전력용 반도체 소자의 제조 방법
US6818512B1 (en) * 2002-01-04 2004-11-16 Taiwan Semiconductor Manufacturing Company Split-gate flash with source/drain multi-sharing
JP2003309192A (ja) * 2002-04-17 2003-10-31 Fujitsu Ltd 不揮発性半導体メモリおよびその製造方法
TW583755B (en) * 2002-11-18 2004-04-11 Nanya Technology Corp Method for fabricating a vertical nitride read-only memory (NROM) cell
TW569435B (en) * 2002-12-17 2004-01-01 Nanya Technology Corp A stacked gate flash memory and the method of fabricating the same
US6894339B2 (en) * 2003-01-02 2005-05-17 Actrans System Inc. Flash memory with trench select gate and fabrication process
US6706599B1 (en) * 2003-03-20 2004-03-16 Motorola, Inc. Multi-bit non-volatile memory device and method therefor
US6754105B1 (en) * 2003-05-06 2004-06-22 Advanced Micro Devices, Inc. Trench side wall charge trapping dielectric flash memory device
US6958513B2 (en) * 2003-06-06 2005-10-25 Chih-Hsin Wang Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells
US6861315B1 (en) * 2003-08-14 2005-03-01 Silicon Storage Technology, Inc. Method of manufacturing an array of bi-directional nonvolatile memory cells
US7098502B2 (en) * 2003-11-10 2006-08-29 Freescale Semiconductor, Inc. Transistor having three electrically isolated electrodes and method of formation
US7202523B2 (en) * 2003-11-17 2007-04-10 Micron Technology, Inc. NROM flash memory devices on ultrathin silicon
US7050330B2 (en) * 2003-12-16 2006-05-23 Micron Technology, Inc. Multi-state NROM device
US20050148173A1 (en) * 2004-01-05 2005-07-07 Fuja Shone Non-volatile memory array having vertical transistors and manufacturing method thereof
US7015537B2 (en) * 2004-04-12 2006-03-21 Silicon Storage Technology, Inc. Isolation-less, contact-less array of nonvolatile memory cells each having a floating gate for storage of charges, and methods of manufacturing, and operating therefor
US7196935B2 (en) * 2004-05-18 2007-03-27 Micron Technolnology, Inc. Ballistic injection NROM flash memory

Also Published As

Publication number Publication date
EP1911077A4 (en) 2009-09-23
JP2009503860A (ja) 2009-01-29
KR20080035579A (ko) 2008-04-23
CN101253608A (zh) 2008-08-27
CN101253608B (zh) 2010-09-01
WO2007014118A3 (en) 2007-07-19
EP1911077A2 (en) 2008-04-16
US7211487B2 (en) 2007-05-01
WO2007014118A2 (en) 2007-02-01
US20070020857A1 (en) 2007-01-25

Similar Documents

Publication Publication Date Title
TW200713280A (en) Electronic device including discontinuous storage elements
TW200741888A (en) Process for forming an electronic device including discontinuous storage elements
TW200725709A (en) Semiconductor apparatus and making method thereof
WO2008078197A3 (en) Method for controlled formation of the resistive switching material in a resistive switching device and devices obtained thereof
TW200616053A (en) A method for making a semiconductor device that includes a metal gate electrode
TW200737555A (en) Light-emitting device and method for manufacturing the same
TW200509391A (en) A device having multiple silicide types and a method for its fabrication
TW200733438A (en) Film bulk acoustic resonator and method for manufacturing the same
SG148897A1 (en) Methods of forming trench isolation regions
TW200629422A (en) Method of manufacturing a capaciotr and a metal gate on a semiconductor device
WO2004109770A3 (en) Through wafer via process and amplifier with through wafer via
TWI315584B (en) Display device and manufacturing method thereof
TW200711005A (en) Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof
WO2009052156A3 (en) Isolation trench with rounded corners for bicmos process
TW200731850A (en) Organic light-emitting transistor element and method for manufacturing the same
TW200605713A (en) Mask, method for manufacturing a mask, method for manufacturing an electro-optical device, and electronic equipment
TW200742071A (en) Polysilicon control etch-back indicator
TW200641972A (en) Semiconductor device and integrated circuit
TW200616028A (en) Passive device and method for forming the same
TW200715556A (en) Electronic device with a gate electrode having at least two portions and a process for forming the electronic device
TW200635027A (en) Semiconductor device manufacturing method, semiconductor device, laminated semiconductor device, circuit substrate, and electronic apparatus
WO2007079157A3 (en) Electronic device having black layers
TW200634977A (en) Method of forming transistor using step sti profile in memory device
TW200515505A (en) Method of forming a contact on a silicon-on-insulator wafer
TW200744196A (en) Memory device