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TW200732925A - Parallel data storage system - Google Patents

Parallel data storage system

Info

Publication number
TW200732925A
TW200732925A TW095117567A TW95117567A TW200732925A TW 200732925 A TW200732925 A TW 200732925A TW 095117567 A TW095117567 A TW 095117567A TW 95117567 A TW95117567 A TW 95117567A TW 200732925 A TW200732925 A TW 200732925A
Authority
TW
Taiwan
Prior art keywords
data
data storage
interface
storage devices
buffer
Prior art date
Application number
TW095117567A
Other languages
Chinese (zh)
Inventor
Hooshmand Torabi
Chak-Fai Cheng
Nader Salessi
Hosein Gazeri
Original Assignee
Simpletech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/358,043 external-priority patent/US7376034B2/en
Application filed by Simpletech Inc filed Critical Simpletech Inc
Publication of TW200732925A publication Critical patent/TW200732925A/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Landscapes

  • Information Transfer Systems (AREA)

Abstract

A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received from the host system via the interface. A switch is used to selectively connect the interface and the data storage devices to the buffer to facilitate the transfer of data into and out of the buffer. The data sectors are transferred by segmenting each sector into multiple smaller data cells and distributing these data cells among the data storage devices using an arbitrated distribution method.
TW095117567A 2006-02-22 2006-05-18 Parallel data storage system TW200732925A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/358,043 US7376034B2 (en) 2005-12-15 2006-02-22 Parallel data storage system

Publications (1)

Publication Number Publication Date
TW200732925A true TW200732925A (en) 2007-09-01

Family

ID=38514730

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095117567A TW200732925A (en) 2006-02-22 2006-05-18 Parallel data storage system

Country Status (2)

Country Link
DE (1) DE102006052328A1 (en)
TW (1) TW200732925A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI383298B (en) * 2008-11-05 2013-01-21 承景科技股份有限公司 Direct memory access controller and method for accessing the same
TWI421680B (en) * 2007-05-10 2014-01-01 Memoright Memoritech Corp Parallel flash memory controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI421680B (en) * 2007-05-10 2014-01-01 Memoright Memoritech Corp Parallel flash memory controller
TWI383298B (en) * 2008-11-05 2013-01-21 承景科技股份有限公司 Direct memory access controller and method for accessing the same

Also Published As

Publication number Publication date
DE102006052328A1 (en) 2007-10-18

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