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TW200727395A - A low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method - Google Patents

A low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method

Info

Publication number
TW200727395A
TW200727395A TW095104143A TW95104143A TW200727395A TW 200727395 A TW200727395 A TW 200727395A TW 095104143 A TW095104143 A TW 095104143A TW 95104143 A TW95104143 A TW 95104143A TW 200727395 A TW200727395 A TW 200727395A
Authority
TW
Taiwan
Prior art keywords
low temperature
aspect ratio
conductive material
devices fabricated
fabricating high
Prior art date
Application number
TW095104143A
Other languages
Chinese (zh)
Inventor
Robert L Borwick
Philip A Stupar
Jeffrey F Denatale
Chia-Lun Tsai
Zhi-Min J Yao
Kathleen Garrett
John White
Les Warren
Morgan Tench
Original Assignee
Rockwell Scient Licensing Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/167,014 external-priority patent/US7538032B2/en
Application filed by Rockwell Scient Licensing Llc filed Critical Rockwell Scient Licensing Llc
Publication of TW200727395A publication Critical patent/TW200727395A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

Embodiments of the present invention are directed to a process for forming small diameter vias at low temperatures. In preferred embodiments, through-substrate vias are fabricated by forming a through-substrate via; and depositing conductive material into the via by means of a flowing solution plating technique, wherein the conductive material releases a gas that pushes the conductive material through the via to facilitate plating the via with the conductive material. In preferred embodiments, the fabrication of the substrate is conducted at low temperatures.
TW095104143A 2005-02-09 2006-02-08 A low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method TW200727395A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US65195105P 2005-02-09 2005-02-09
US11/167,014 US7538032B2 (en) 2005-06-23 2005-06-23 Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method

Publications (1)

Publication Number Publication Date
TW200727395A true TW200727395A (en) 2007-07-16

Family

ID=36518538

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095104143A TW200727395A (en) 2005-02-09 2006-02-08 A low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method

Country Status (2)

Country Link
TW (1) TW200727395A (en)
WO (1) WO2006086337A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1892757B1 (en) * 2006-08-25 2017-06-07 Imec High aspect ratio via etch
US7807583B2 (en) 2006-08-25 2010-10-05 Imec High aspect ratio via etch
US20080142478A1 (en) * 2006-11-01 2008-06-19 Microchem Corp. Epoxy removal process for microformed electroplated devices
FR2933425B1 (en) 2008-07-01 2010-09-10 Alchimer PROCESS FOR PREPARING AN ELECTRIC INSULATING FILM AND APPLICATION FOR METALLIZING VIAS THROUGH

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69737262T2 (en) * 1997-11-26 2007-11-08 Stmicroelectronics S.R.L., Agrate Brianza A method of manufacturing a front-to-back via in micro-integrated circuits
US6278181B1 (en) * 1999-06-28 2001-08-21 Advanced Micro Devices, Inc. Stacked multi-chip modules using C4 interconnect technology having improved thermal management
JP3834589B2 (en) * 2001-06-27 2006-10-18 株式会社ルネサステクノロジ Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
WO2006086337A1 (en) 2006-08-17

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