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TW200539179A - Concurrent refresh mode with distributed row address counters in an embedded DRAM - Google Patents

Concurrent refresh mode with distributed row address counters in an embedded DRAM Download PDF

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Publication number
TW200539179A
TW200539179A TW094100085A TW94100085A TW200539179A TW 200539179 A TW200539179 A TW 200539179A TW 094100085 A TW094100085 A TW 094100085A TW 94100085 A TW94100085 A TW 94100085A TW 200539179 A TW200539179 A TW 200539179A
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Taiwan
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memory
refresh
array
arrays
semiconductor
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TW094100085A
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Chinese (zh)
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TWI330368B (en
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John E Barth Jr
Toshiaki Kirihata
Paul C Parries
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Ibm
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

A concurrent refresh mode is realized by allowing a memory array to be refreshed by way of a refresh bank select signal, while concurrently enabling a memory access operation in another array. The refresh address management is greatly simplified by the insertion of row address counter integrated within each array. In the preferred embodiment, any combination of a plurality of the memory arrays is refreshed simultaneously while enabling a memory access operation. This concurrent mode also supports a multi-bank operation.

Description

200539179 九、發明說明： 【發明所屬之技術領域】 本發明大體而言係關於一種内嵌動態隨機存取記憶體 (内嵌DRAM)，且更特定言之，係關於一種採用整合於每個 DRAM中的分散列位址計數器之並行刷新模式與設計。 【先前技術】 半導體技術之改良已使得處理器之設計擁有超越i Giga Hz的效能。然而，系統之效能常受限於其記憶體之效能。 此缺點之存在已引起潛在對高效能内嵌DRAM的強烈需 求’以幫助處理器獲得必要之速度。由於9〇 nm技術之產生 與超越，減小單元尺寸且改良内嵌DRAM之陣列存取電晶 體之效能很困難。此歸因於當裝置洩漏存在時，電晶體臨 限電壓不會降低。於是，必須降低操作電壓來保證裝置之 可靠性與邏輯處理相容性。此等考慮已引起一基本轉變·· 藉由利用一高效能邏輯裝置作為一記憶體單元使資料保持 驅動設計轉變為記憶體可用性驅動設計。 參考圖1，所示為說明前述聲明之模擬感應訊號。在參考 曲線（A)中，一習知之具有2·5 V字元線升高電壓（vpp)且由 耦& 256單元之長位元線（256 b/BL)支撐之陣列裝置 52A(未圖示）與苓考曲線（B)相比較，其中一由u伏vpp供 電之謎輯陣列裝置22A(未圖示）由一耦合64單元之短位元 線支撐。藉由改變訊號發展時間（tSIG)來提取感應訊號，訊 號毛展日守間思即，當在接地感應機制中經過隨機存取週期 化間（tRC)啟動一字元線時，在該位元線上發展一訊號所需 98441.doc 200539179 的時間。隨著該訊號發展時間增加，單元中之過量電荷被 傳送到位元線，增加了感應訊號。然而，當tsIG增加超過 之約40%時，該電壓不足以寫回至該單元，導致一較小訊 號。因為邏輯陣列裝置22A的啟用電流比相應陣列裝置52八 可用的電流高約30% ,所以即使對3·2 ns隨機存取週期亦可 達成約80 mV的感應電壓。然而，採用邏輯陣列裝置a需 要該資料保持時間減少至64 us之值。較短保持時間大大減 少記憶體之可用性，對大密度記憶體尤其如此，因為所有 記憶體單元需要在一給定保持時間内進行刷新來保持資料 位元。以實例說明之，一具有8尺字元線之4Mb記憶體需要 在64 us内有8 K刷新週期。如此，又需要每8 ns至少有一刷 新指令，導致該記憶體在8 ns隨機週期記憶過程中不可用。 為了克服在短保持時間DRAM中的記憶體可用性問題，通 常使用一並行刷新模式，例如，如在頒予J〇hns〇n等人的美 國專利號為4，185,323之專利中所述。 圖2為由複數個DRAM記憶體組210組成的一半導體記憶 體晶片200之方塊圖表示。每個記憶體組2丨〇由以二維矩陣 組態排列之複數個DRAM記憶體單元（未圖示）組成，此是此 項技術中所熟知的且因此不進一步討論。一旦在一 DRam 組210(例如，210i)中起始一記憶體存取操作（讀、寫、或刷 新操作），該DRAM組（例如，210i)在一隨機存取週期時間 tRC内將不可用。在該〇11入]^組（例如，21〇〇進行記憶體存 取操作期間，可同時刷新其他DRAM組（例如，2丨〇J_)。如此， 藉由在啟用記憶體存取操作時並行執行刷新操作，記憶體 9844J.doc 200539179 可用性得到大大提高。有兩種已知方法用於在一半導體記 憶體中啟用一並行刷新模式，其詳細說明將在下文描述， 如下文參考圖3與圖4說明。 圖3說明在一習知靜態隨機存取記憶體（SRAM)緩衝器中 啟用一並行刷新模式之第一種方法。例如，此方法之詳細 說明在頒予Leung等人的美國專利號為5,999,474之專利中 所述。半導體記憶體晶片300由複數個DRAM組（310DRAM) 組成，每個DRAM組由以二維矩陣組態排列的複數個記憶 體單元組成。存取組310DRAM-310j同時並行刷新至少一其 他組3 1 0DRAM-3 1 Ok為可能的，只要被存取組與被刷新組是 不同的。如此允許刷新DRAM組（3 10k)中相應字元線320k 支持之複數個單元（330k)，同時存取DRAM組（310j)中相應 字元線（320j)支持之複數個單元（330j)。然而，若陣列310j 是連續定址的，則因為不間斷的記憶體存取操作使得陣列 3 10j連續為忙，所以在同一陣列310j中的某些記憶體單元將 完全不會被刷新。如此排除了對同一陣列（3 10j)中的某些記 憶體單元執行刷新操作。 為了克服此問題，藉由增加一 SRAM組（310SRAM)，以一 允許在一時鐘週期内接收與傳送資料的雙埠功能為特徵來 增強記憶體晶片300。TAG記憶體（310TAG)控制DRAM組 (310DRAM)與SRAM(310SRAM)之存取操作，而藉由讀或寫 指令（未圖示）、組位址（XBADD)與字組位址（XWADD)來啟 用記憶體晶片300之記憶體存取，其中XB ADD與XWADD識 別一 DRAM組（3 10DRAM)與選定DRAM組内之適當字元 98441.doc 200539179 線。當啟用記憶體存取時，藉由解碼字組位址（XWADD)啟 動TAG記憶體（310TAG)内之字元線（320TAG)與SRAM組 (310SRAM)内之字元線（320s)。如此使得讀出TAG記憶體 (310TAG)内之記憶體單元（330TAG)内之資料與SRAM緩衝 器（310SRAM)内之記憶體單元（330s)内之資料。TAG記憶體 (310TAG)之讀出資料位元（330TAG)界定組位址（TBADD)， 該組位址又為當前自SRAM緩衝器（3 10SRAM)讀出之資料 位元（330s)識別相應的DRAM組。當TB ADD符合組位址輸入 (XBADD)時，該等資料位元（330s)即為記憶體存取指令請求 之位元，此係因為該等資料位元（330s)已提前從相應的 DRAM組複製至SRAM緩衝器（310SRAM)。因此，不需要存 取DRAM組，且從XDATA引腳讀出來自SRAM緩衝器 (310SRAM)之讀出資料位元。另一方面，若TBADD不同於 組位址輸入（XBADD)，則TAG記憶體（310TAG)如下控制 DRAM組（310DRAM)。 假設TADD識別出DRAM組（310i)，則SRAM緩衝器 (310SRAM)内之資料位元（330s)被儲存回DRAM組（310i)， 其中字元線320i與320s之字元線位址相同（直接映射）。如此 允許自SRAM記憶體單元（330s)傳送資料位元至DRAM記憶 體單元（330i)。與組位址輸入（XBADD)並行，相應DRAM組 (3 10j)為一讀操作而被啟動。於是，讀出在該相應DRAM組 (310j)内之該等單元之資料位元（330j)，其中字元線320j符 合320s之字元線位址（直接映射）。自XDATA引腳讀出該等 資料位元。該等單元之資料位元（330j)亦被儲存在SRAM緩 98441.doc 200539179 衝器（310SRAM)内之單元（330s)中。於是為了 一未來記憶體 存取指令’更新TBADD來識別DRAM組3 10j。由於一隨後 相同定址方式（意即330j)，資料位元被讀出或寫入至sraM 緩衝器（310SRAM)，即使當僅有一陣列（意即33〇j)為連續定 址時’亦啟用該等記憶體單元之刷新操作。此係可能的， 因為最後在該陣列内之資料位元將被拷貝至SRAM陣列，在 沒有任何破壞下刷新該陣列。 然而，此並行刷新方法有幾個缺點。首先，其需要一 SraM 陣列（3 10SRAM) ’该陣列顯著較大。其次，考慮到tag管 理，邏輯變付較複雜，此又減緩了記憶體存取之等待時間。 最後，因為記憶體組在給定DRAM組週期（tRC)内的刷新操 作期間不可用，所以此方法不適合於多組記憶體。多組記 憶體晶片需要在每個組至組存取週期（tRRD)(其短於tRc) 内定址任何需要被定址之組，使得當需要一 t R c週期時不可 能啟用刷新操作。 圖4說明藉由利用DRAM之並行功能，啟用一同時刷新之 第二種方法。半導體記憶體晶片4〇〇由複數個組 410(41 〇ι至410j)組成，每個DRAM組由相應的位址與指令埠 (420i至420j)控制。因此可並行啟動任兩個或兩個以:的 組。以該並行功能說明之，記憶體組41〇〗保持在讀模式， 同時仍為記憶體組41〇j啟用刷新操作。然而，此方法需要 一複雜的刷新系統管理來避免由並行功能引起的組存取爭 用（contention)。因為需要獨立管理所有組之被刷新記憶$ 的位址TAG ’所以在避免並行功能引起之組存取爭用的同 98441.doc -10- 200539179 時，在系統階層上處理每個陣列内之刷新位址是高度複雜 的。結果’為同時刷新採用並行功能需要進行顯著的系統 修正。 【發明内容】 因此，本發明之一目的係為内嵌dram提供並行刷新操 作來改良記憶體可用性。 本發明之另一目的係不求助於使用SRAM緩衝器為内嵌 DRAM提供並行刷新操作。 本發明之另一目的係為内嵌DRAM提供並行刷新操作來 間化s己憶體系統之設計。 本I明之又一目的係為内嵌在一多組記憶體系統内之 dram啟用並行刷新操作。 本毛月之另目的係僅採用刷新組選擇為内嵌DRAM啟 用並行刷新操作。 抑本發明說明—種並行刷新模式，其中内❹RAM經由簡 單系、先t正來啟用—同時記憶體存取並刷新操作。該並行 刷新模式藉由允許僅由—刷新組選擇埠來刷新未選定記憶 體陣列來實現。不像習知之方法，整合於每個組内之大量 使用之列位址計數H追崎叫減、㈣之字元線位址。 :大大減小了在並行刷新模式内管理刷新位址之複雜性， 运疋由於在每組内大量倭用 — 便用之刷新計數器獨立保持刷新的 字元線。僅藉由管理組存取泰 筆用即達成採用此並行刷新方 法之系統改良。因為刷新管 g里了被整合於現有多組管理系 統内，所以本發明對呈右站奴』士 + 、有紐保持時間dram之多組系統尤 98441.doc 200539179 其有盃。只要管理好組爭用就可實現記憶體1〇〇%的可 性。 在本發明之另一態樣中，提供一由兩個或兩個以上之記 it體陣列組成之半導體記憶體，纟中兩個陣列中之每一個 當給出一刷新指令時，耦合至一列位址計數器來產生每個 陣列内之一第一字組位址，同時啟用至少一個以上陣列處 於δ己憶體存取模式中。 在本發明之另一態樣中，提供一半導體記憶體，其包含·· 1)複數個記憶體陣列，每個陣列包括以一矩陣排列且由唯一 指派給每個記憶體陣列的列位址計數器控制之複數個記憶 體單元，該列位址計數器產生一第一字組位址；及ii)用來 在將刷新指令發佈給相應記憶體陣列時，在記憶體單元内 啟用刷新操作之構件，該等記憶體單元由該第一字組位址 識別出。 併入本說明書且組成該說明書之一部分的隨附圖式說明 了本發明之當如較佳之實施例，並與上文給出之一般陳述 及下文給出之較佳實施例之【實施方式】一起來說明本發 明之原則。 【實施方式】 現在參考圖5，圖示為具備本發明之具有分散列位址計數 器之並行刷新模式的記憶體架構。本實施例假設内嵌 DRAM集。然而本發明亦適用於單獨的dram。 該DRAM集採用具有16個獨立組選擇埠bSEL〇_15之可撓 性多組協定，每個埠控制ΒΑΝΚ0·15中之一相應陣列。視需 98441.doc -12- 200539179 要BSELo·^可建構為一四位元組位址向量，其用來識別 BANK〇-】5令之一陣列。不像習知之集，其進一步包 含16個刷新組選擇.RBSELq_】5，每個埠控制作為一獨立於 記憶體存取操作之組的相應陣列。本發明之基本概念不是 並行刷新模式，而是引入整合於每組内之分散列位址計數 器來達成在系統階層上大大簡化刷新管理。 每個陣列包含一為一並行刷新模式識別字組位址 WRAC〇·6之列位址計數器RAC(例如，52〇)。每個陣列進一 步包含一父換裔530來選擇性地耦合字組位址WADDg_6或 字組位址WRAC〇·6至該陣列組（BANK)之列解碼器（未圖 不）。為一記憶體存取操作，組選擇訊號BSEL發佈之字組位 址WADDw經由交換器53〇耦合至陣列5丨〇内之列解碼器（未 圖示）。如此允許根據字組位址WADD〇 ^^動陣列51〇内之相 應子元線（未圖示）。另一方面，當發佈組刷新指令rbsel 時，來自計數器RAC 520之字組位址（wrac〇6)經由交換器 530耦合至該陣列内之列解碼器（未圖示）。如此允許根據字 組位址（WRACV6)啟動陣列51〇内之相應字元線（未圖示）來 刷新相應的記憶體單元。藉由管理BSEL(意即，BSEL〇)與 RBSEL(意即，RBSEL0)，啟用一陣列（意即，BANK〇)之記 憶體存取，同時為另一陣列（意即，BANKi4)並行啟用刷新 操作。因為RAC計數器被整合於每組中，所以在選定刷新 組（意即，BANK〇)内之字元線啟動是在内部管理的。此大 大簡化了系統設計。 如上所述，避免组爭用係多組記憶體系統之習知設計實 98441.doc -13- 200539179 踐方法。假設每個陣列由128條字元線組成，在保持時間内 只要對每組發佈128條刷新指令，資料將被保持。此藉由正 確管理RBSEL，可使得利用幾乎全部記憶體。在多組系統 中，可在每個組至組存取時間週期（tRRD)内以交錯方式啟 動該組，同時在每個tRRD内並行刷新其他陣列。只要相同 組之啟動比隨機存取週期時間（tRC)長，就可避免被存取組 與被刷新組之間之存取爭用。更特定言之，藉由BSELn與 RBSELn啟動隨後組（ΒΑΝΚη)必須比tRC長。此管理比現存 具有相應位址與指令埠之並行刷新管理簡單的多。選定刷 新組不需要有刷新位址管理。視需要，在每個時鐘週期内， 同時刷新兩個或兩個以上記憶體陣列，同時啟用記憶體存 取。此係藉由同時啟動複數個刷新組控制訊號RBSEL〇_15而 有利實現的。當在位址埠與各控制電路之間未建立通訊 時，分散RAC計數器方法需要對相應被刷新組控制 RBSEL。此將引起高達10 mA之電流節約，假設是七位址匯 流排轉移，每個具有在1 GHz頻率下運作之1.5 pF電容。當 記憶體速度與密度增加時，進一步改良該電流保存優勢。 圖6為整合於每組（BANK)内之列位址計數器520的電晶 體階層示意圖。該列位址計數器包含七個計數器邏輯元 件，610—0至610_6，每個均產生相應位址位元WRACg_6。 每個計數器邏輯元件（例如，610_0)由兩個CMOS通閘622與 624、兩個CMOS鎖存器626與628及兩個反相器620與630組 成。圖5中所示之刷新啟用訊號RBSEL耦合至CMOS通閘622 之NMOS閘，與CMOS通閘624之PMOS閘。藉由反相器620 98441.doc -14· 200539179 將RBSEL反相且其耦合至CM〇s通閘622之問與 CMOS通閘624之NMOS閘。因此，只要訊號Rbsel^/，' CMOS通閘624將節點N2耦合至節點N3，且隨後至節點。 CMOS通閘622保持斷開，使節點no與N4斷開。 器邏輯元件610-0之WRAC0(耦合至m)之輪 因此自計數 出遵循節點 N1。當訊號RBSEL交換為高以啟用一並行刷新模式時，200539179 IX. Description of the invention: [Technical field to which the invention belongs] The present invention generally relates to an embedded dynamic random access memory (embedded DRAM), and more specifically, relates to a method of integrating and integrating into each DRAM Parallel refresh mode and design of distributed column address counters in. [Previous technology] Improvements in semiconductor technology have enabled the design of processors to exceed i Giga Hz performance. However, the performance of a system is often limited by the performance of its memory. The existence of this disadvantage has caused a potential strong demand for high-performance embedded DRAM 'to help the processor achieve the necessary speed. Due to the generation and surpassing of the 90 nm technology, it is difficult to reduce the cell size and improve the performance of the array access transistor with embedded DRAM. This is due to the fact that the threshold voltage of the transistor does not decrease when a device leak is present. Therefore, the operating voltage must be reduced to ensure the reliability of the device and the compatibility with the logic processing. These considerations have led to a fundamental shift ... The transformation of a data retention-driven design into a memory availability-driven design by using a high-performance logic device as a memory unit. Referring to FIG. 1, there is shown an analog inductive signal that illustrates the foregoing statement. In the reference curve (A), a conventional array device 52A (not shown) has a 2.5 V word line boost voltage (vpp) and is supported by a long bit line (256 b / BL) of a coupling & 256 cell. Compared with the Lingkao curve (B), a mystery array device 22A (not shown) powered by uV vpp is supported by a short bit line coupled with 64 cells. By changing the signal development time (tSIG) to extract the induction signal, the signal Mao Zhanji thinks, when a word line is activated in the ground induction mechanism after random access periodization (tRC), It takes 98441.doc 200539179 to develop a signal online. As the signal development time increases, the excess charge in the cell is transferred to the bit line, increasing the sensing signal. However, when tsIG increased by about 40%, the voltage was not enough to write back to the cell, resulting in a smaller signal. Because the enable current of the logic array device 22A is approximately 30% higher than the current available in the corresponding array device 528, it is possible to achieve an induced voltage of approximately 80 mV even for a 3.2 ns random access cycle. However, the use of the logic array device a requires the data holding time to be reduced to a value of 64 us. Shorter hold times greatly reduce the availability of memory, especially for high-density memory, as all memory cells need to be refreshed within a given hold time to hold data bits. By way of example, a 4Mb memory with 8-foot character lines requires an 8 K refresh cycle within 64 us. In this way, at least one refresh instruction is required every 8 ns, resulting in the memory being unavailable during the 8 ns random period memory process. To overcome memory availability issues in short-hold DRAMs, a parallel refresh mode is commonly used, for example, as described in U.S. Patent No. 4,185,323 issued to Johns et al. FIG. 2 is a block diagram representation of a semiconductor memory chip 200 composed of a plurality of DRAM memory groups 210. As shown in FIG. Each memory group 2 is composed of a plurality of DRAM memory cells (not shown) arranged in a two-dimensional matrix configuration, which is well known in this technology and therefore will not be discussed further. Once a memory access operation (read, write, or refresh operation) is initiated in a DRam group 210 (eg, 210i), the DRAM group (eg, 210i) will be unavailable for a random access cycle time tRC . During the memory access operation (for example, 2100), other DRAM groups (for example, 2J_) can be refreshed at the same time. In this way, by enabling the memory access operation in parallel Perform refresh operation, the usability of memory 9844J.doc 200539179 is greatly improved. There are two known methods for enabling a parallel refresh mode in a semiconductor memory, the detailed description of which will be described below, as shown below with reference to FIG. 3 and FIG. 4. Explanation. Figure 3 illustrates the first method of enabling a parallel refresh mode in a conventional static random access memory (SRAM) buffer. For example, a detailed description of this method is provided in US Patent No. issued to Leung et al. It is described in the patent of 5,999,474. The semiconductor memory chip 300 is composed of a plurality of DRAM groups (310DRAM), and each DRAM group is composed of a plurality of memory cells arranged in a two-dimensional matrix configuration. The access groups 310DRAM-310j simultaneously It is possible to refresh at least one other group 3 1 0DRAM-3 1 Ok in parallel, as long as the accessed group is different from the refreshed group. This allows the corresponding word line 320k in the DRAM group (3 10k) to be refreshed. Several cells (330k), and simultaneously access a plurality of cells (330j) supported by the corresponding word line (320j) in the DRAM group (310j). However, if the array 310j is continuously addressed, it is because of uninterrupted memory storage The fetch operation keeps array 3 10j continuously busy, so some memory cells in the same array 310j will not be refreshed at all. This precludes performing refresh operations on some memory cells in the same array (3 10j). To overcome this problem, the memory chip 300 is enhanced by adding a SRAM bank (310SRAM), which is characterized by a dual-port function that allows data to be received and transmitted within one clock cycle. The TAG memory (310TAG) controls the DRAM bank ( 310DRAM) and SRAM (310SRAM) access operations, and memory access to memory chip 300 is enabled by read or write commands (not shown), bank address (XBADD), and block address (XWADD) Among them, XB ADD and XWADD identify a DRAM bank (3 10 DRAM) and appropriate characters in the selected DRAM bank 98441.doc 200539179 line. When memory access is enabled, the TAG memory is activated by the decode block address (XWADD) Characters in the body (310TAG) Line (320TAG) and the word line (320s) in the SRAM group (310SRAM). This makes it possible to read out the data in the memory cell (330TAG) in the TAG memory (310TAG) and the memory in the SRAM buffer (310SRAM). The data in the body unit (330s). The read data bit (330TAG) of the TAG memory (310TAG) defines the group address (TBADD), which is the address currently read from the SRAM buffer (3 10SRAM). The data bits (330s) identify the corresponding DRAM bank. When TB ADD meets the group address input (XBADD), these data bits (330s) are the bits requested by the memory access instruction. This is because these data bits (330s) have been removed from the corresponding DRAM in advance. The bank is copied to the SRAM buffer (310SRAM). Therefore, there is no need to access the DRAM bank and read the read data bits from the SRAM buffer (310SRAM) from the XDATA pin. On the other hand, if TBADD is different from the bank address input (XBADD), the TAG memory (310TAG) controls the DRAM bank (310DRAM) as follows. Assuming TADD recognizes the DRAM bank (310i), the data bits (330s) in the SRAM buffer (310SRAM) are stored back to the DRAM bank (310i), where the word line addresses of the word lines 320i and 320s are the same (directly Mapping). This allows data bits to be transferred from the SRAM memory unit (330s) to the DRAM memory unit (330i). In parallel with the bank address input (XBADD), the corresponding DRAM bank (3 10j) is started for a read operation. Then, the data bits (330j) of the cells in the corresponding DRAM group (310j) are read out, where the character line 320j corresponds to the word line address (direct mapping) of 320s. These data bits are read from the XDATA pin. The data bits (330j) of these cells are also stored in cells (330s) in the SRAM buffer 98441.doc 200539179 (310SRAM). TBADD is then updated for a future memory access instruction 'to identify the DRAM bank 3 10j. Due to a subsequent addressing method (meaning 330j), data bits are read or written to the sraM buffer (310SRAM), which is enabled even when only one array (meaning 33〇j) is continuously addressed. Refresh operation of the memory unit. This is possible because the last data bits in the array will be copied to the SRAM array, and the array will be refreshed without any damage. However, this parallel refresh method has several disadvantages. First, it requires an SraM array (3 10 SRAM), which is significantly larger. Secondly, considering tag management, logical changes are more complicated, which in turn slows down the waiting time for memory access. Finally, because memory banks are not available during a refresh operation within a given DRAM bank cycle (tRC), this method is not suitable for multiple banks. Multiple sets of memory chips need to address any group to be addressed within each group-to-group access cycle (tRRD) (which is shorter than tRc), making it impossible to enable a refresh operation when a t R c cycle is required. Figure 4 illustrates a second method of enabling a simultaneous refresh by using the parallel function of DRAM. The semiconductor memory chip 400 is composed of a plurality of banks 410 (410 to 410j), and each DRAM bank is controlled by a corresponding address and instruction port (420i to 420j). Therefore, any two or two groups starting with: can be started in parallel. With this parallel function description, the memory group 41〇 remains in the read mode, while the refresh operation is still enabled for the memory group 41〇j. However, this method requires a complex refresh system management to avoid group access contention caused by parallel functions. Because the address TAG 'of the refreshed memory $ of all groups needs to be managed independently, when avoiding group access contention caused by parallel functions, the same as 98441.doc -10- 200539179 is handled at the system level in each array. Addresses are highly complex. Result 'The use of parallel functions for simultaneous refresh requires significant system corrections. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a parallel refresh operation for an embedded dram to improve memory availability. Another object of the present invention is not to resort to the use of SRAM buffers to provide parallel refresh operations for embedded DRAM. Another object of the present invention is to provide a parallel refresh operation for an embedded DRAM to design a memory system. Another purpose of this document is to enable parallel refresh operations for drams embedded in multiple memory systems. The other purpose of this month is to use only the refresh group selection to enable parallel refresh operation for the embedded DRAM. The present invention describes a parallel refresh mode, in which the internal RAM is enabled via a simple system and is first forwarded at the same time-memory access and refresh operations. The parallel refresh mode is implemented by allowing only the -select bank to refresh unselected memory arrays. Unlike the conventional method, a large number of used column address counts H are integrated into each group. : It greatly reduces the complexity of managing the refresh address in the parallel refresh mode. Since it is used a lot in each group, it uses the refresh counter to keep the refreshed character lines independently. Only by the management group accessing Thai pens, a system improvement using this parallel refresh method is achieved. Because the refresh tube g is integrated into the existing multiple sets of management systems, the present invention is particularly useful for multiple sets of systems that have a right-side slave + + and a new-year hold time ram 98441.doc 200539179. As long as the contention of the group is managed, 100% of the memory can be achieved. In another aspect of the present invention, a semiconductor memory is provided which is composed of two or more arrays of memory cells. Each of the two arrays is coupled to a column when a refresh instruction is given. The address counter is used to generate a first block address in each array, and at least one array is enabled in the delta memory access mode. In another aspect of the present invention, a semiconductor memory is provided, comprising: 1) a plurality of memory arrays, each array including a column address arranged in a matrix and uniquely assigned to each memory array A plurality of memory cells controlled by a counter, the column address counter generates a first block address; and ii) a component for enabling a refresh operation in a memory cell when a refresh instruction is issued to a corresponding memory array The memory units are identified by the first block address. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate the preferred embodiments of the present invention, and are consistent with the general statements given above and the preferred embodiments given below. Together, the principles of the invention are explained. [Embodiment] Referring now to FIG. 5, there is shown a memory architecture having a parallel refresh mode with a distributed column address counter according to the present invention. This embodiment assumes an embedded DRAM set. However, the invention is also applicable to individual dram. The DRAM set uses a flexible multi-group protocol with 16 independent bank selection ports bSEL0_15, and each port controls one of the corresponding arrays in BANK0 · 15. As required 98441.doc -12- 200539179 BSELo · ^ can be constructed as a four-byte address vector, which is used to identify an array of BANK〇-] 5 orders. Unlike the conventional set, it further includes 16 refresh group selections. RBSELq_] 5, each port controls as a corresponding array independent of the memory access operation. The basic concept of the present invention is not a parallel refresh mode, but a distributed column address counter integrated in each group to achieve a greatly simplified refresh management at the system level. Each array includes a column address counter RAC (e.g., 52), which is a parallel refresh pattern identification block address WRAC0.6. Each array further includes a parent 530 to selectively couple the block address WADDg_6 or the block address WRAC0.6 to a column decoder of the array bank (not shown). For a memory access operation, the block address WADDw issued by the group selection signal BSEL is coupled to a column decoder (not shown) in the array 5 through the switch 530. This allows the corresponding sub-element lines (not shown) within the array 51 to be moved according to the block address WADD. On the other hand, when the group refresh instruction rbsel is issued, the word block address (wrac0) from the counter RAC 520 is coupled to the column decoder (not shown) in the array via the switch 530. This allows the corresponding word line (not shown) in the array 51 to be activated according to the block address (WRACV6) to refresh the corresponding memory cell. By managing BSEL (meaning BSEL0) and RBSEL (meaning RBSEL0), memory access of one array (meaning BANK0) is enabled, while refresh is enabled for the other array (meaning BANKi4) in parallel operating. Since the RAC counter is integrated in each group, the activation of the character lines in the selected refresh group (i.e. BANK0) is managed internally. This greatly simplifies system design. As mentioned above, avoiding group contention is the practice of designing multiple sets of memory systems 98441.doc -13- 200539179. Assume that each array is composed of 128 word lines. As long as 128 refresh instructions are issued for each group during the hold time, the data will be held. By properly managing the RBSEL, this allows the use of almost all memory. In a multi-group system, the group can be started in a staggered manner during each group-to-group access time period (tRRD), while other arrays are refreshed in parallel within each tRRD. As long as the start of the same group is longer than the random access cycle time (tRC), access contention between the accessed group and the refreshed group can be avoided. More specifically, the subsequent group (BANKK) initiated by BSELn and RBSELn must be longer than tRC. This management is much simpler than the existing parallel refresh management with corresponding addresses and instruction ports. The selected refresh group does not need to have refresh address management. As needed, two or more memory arrays are refreshed at the same time in each clock cycle, and memory access is enabled at the same time. This is advantageously achieved by activating a plurality of refresh group control signals RBSEL0_15 at the same time. When communication is not established between the address port and each control circuit, the distributed RAC counter method needs to control RBSEL for the corresponding refreshed group. This will result in current savings of up to 10 mA, assuming a seven-address bus transfer, each with 1.5 pF capacitors operating at 1 GHz. As memory speed and density increase, this current preservation advantage is further improved. FIG. 6 is a schematic diagram of the transistor hierarchy of the column address counter 520 integrated in each bank (BANK). The column address counter contains seven counter logic elements, 610-0 to 610_6, each of which generates a corresponding address bit WRACg_6. Each counter logic element (e.g., 610_0) is composed of two CMOS gates 622 and 624, two CMOS latches 626 and 628, and two inverters 620 and 630. The refresh enable signal RBSEL shown in FIG. 5 is coupled to the NMOS gate of the CMOS pass gate 622 and the PMOS gate of the CMOS pass gate 624. The RBSEL is inverted by an inverter 620 98441.doc-14.200539179 and it is coupled to the NMOS gate of the CMOS gate 622 and the CMOS gate 624. Therefore, as long as the signal Rbsel ^ /, the 'CMOS pass gate 624 couples the node N2 to the node N3, and then to the node. The CMOS open gate 622 remains open, so that the node no is disconnected from N4. The WRAC0 (coupling to m) wheel of the logic element 610-0 of the controller therefore counts itself as following node N1. When the signal RBSEL is switched high to enable a parallel refresh mode,

CMOS通閘622與624分別接通與斷開。WRAc〇保持其狀熊 處於CMOS鎖存器628設置之初始值。藉由耦合節點^〇至節 點N1翻轉節點N1之狀態（注意：這是因為節點_處於^ WRAC〇反相之狀態）。當RBSEL交換為低以停用相應的並行 刷新模式時，CMOS通閘622與624分別斷開與接通，允許位 元WRAC〇翻轉且遵循已更新之節點N卜最後，位元WRAC 在每個RBSEL週期被翻轉，且充當列位址計數器52〇之最低 有效位址位元。對於剩餘的位址位元（WRACu)，元件61〇 内之CMOS通閘622耦合至元件610一n-1内之計數器輸出 N4，η為1至6之整數。如此允許位元WRAq、…、WRA(； 每2、4、8、16、32與64個RBSEL週期分別翻轉，在每個择 列内建立了七位元計數器以產生刷新位址。 圖7為由陣列510、列位址計數器（RAC 520)與七位元交換 元件530組成之詳細組架構。該陣列包含作為一單元陣列之 以 '一維矩陣排列的複數個記憶體單元715。列解碼器7 2 〇與 位元線感應放大器725支持該單元陣列。如上所論述，並行 刷新模式與記憶體存取模式之字組位址分別由字組位址 WRAC〇、…、WRAC6與字組位址 WADD〇、·.·、WADD6支持。 98441.doc -15- 200539179 該選擇由七個交換元件53 0實現，每個交換元件將WADD或 WRAC耦合至歹〇解碼器720 〇對於記憶體存取模式，組選擇 訊號BSEL交換為高，啟動每個交換元件530内之NMOS 732。此將字組位址WADD耦合至CMOS鎖存器736。藉由 CMOS鎖存器736，該WADD位元即使在BSEL交換為低後亦 能保持。對於並行刷新模式，刷新組選擇訊號RBSEL交換 為高，啟動每個交換元件730内之NMOS 734。此將字組位 址WRAC耦合至CMOS鎖存器736。鎖存交換元件530内之字 組位址允許字組位址WADD〇、...、WADD6在多組操作期間 内無需等待相應組操作完成就可啟動其他組。另外，在多 組操作期間，可在每個組啟動週期内發佈一並行刷新操 作。以實例說明之，為刷新與記憶體存取操作而啟動第一 與第二陣列。然後，不用等待第一與第二記憶體陣列操作 之完成，即可為第三組啟用記憶體存取操作，同時並行地 為第四陣列發佈刷新操作。 列解碼器720啟動字元線WL。如上所論述，解碼位元由 自七位元交換元件530傳送之位址位元確定。當字元線交換 為高時，經由位元線BL讀與寫單元715内之資料位元。將差 動BL對有利地耦合至位元線感應放大器725，將自單元715 讀出之小訊號放大。該等感應放大器用於將資料位元寫回 至該等單元（715)，此為熟知，因此不作論述。 儘管已根據幾個較佳實施例論述了本發明，但不脫離本 發明熟習此項技術者可設計出各種替代實施例與修正。因 此，本發明意欲包含屬於附加之申請專利範圍之範疇的所 98441.doc -16- 200539179 有該等替代實施例。 【圖式簡單說明】 圖1為自256 b/BL與64 b/BL兩個DRAM陣列產生之表厂、 模擬感應訊號的兩條曲線，其說明自資料保持驅動設計至 記憶體可用性驅動設計之習知轉變。 圖2為表示一多組DRAM記憶體裝置之方塊圖，其說明如 何藉由應用先前技術之啟用記憶體存取的同時進行刷新操 作之並行效能來改良記憶體可用性。The CMOS gates 622 and 624 are turned on and off, respectively. WRAc keeps its shape at the initial value set by the CMOS latch 628. The state of node N1 is reversed by coupling node ^ 0 to node N1 (note: this is because node_ is in the state of ^ WRAC〇 inversion). When the RBSEL is switched low to disable the corresponding parallel refresh mode, the CMOS gates 622 and 624 are turned off and on respectively, allowing the bit WRAC to flip and follow the updated node N. Finally, the bit WRAC is at each The RBSEL period is inverted and serves as the least significant address bit of the column address counter 52. For the remaining address bits (WRACu), the CMOS pass gate 622 in element 61 is coupled to the counter output N4 in element 610-n-1, where n is an integer from 1 to 6. This allows the bits WRAq, ..., WRA (; to be flipped every 2, 4, 8, 16, 32, and 64 RBSEL cycles, and a seven-bit counter is established in each selected column to generate a refresh address. Figure 7 shows Detailed group architecture consisting of an array 510, a column address counter (RAC 520), and a seven-bit switching element 530. The array includes a plurality of memory cells 715 arranged in a 'one-dimensional matrix as a cell array. A column decoder 7 2 0 and bit line sense amplifier 725 support the cell array. As discussed above, the block addresses of the parallel refresh mode and memory access mode are respectively the block addresses WRAC0, ..., WRAC6 and the block addresses. WADD〇, .., WADD6 support. 98441.doc -15- 200539179 This selection is implemented by seven switching elements 53 0, each switching element couples WADD or WRAC to 歹 〇 decoder 720 〇 For memory access mode When the group selection signal BSEL is switched high, the NMOS 732 in each switching element 530 is activated. This couples the block address WADD to the CMOS latch 736. With the CMOS latch 736, the WADD bit is even in the BSEL It can be maintained after the exchange is low. For parallel brush Mode, the refresh group selection signal RBSEL is exchanged high, and the NMOS 734 in each exchange element 730 is activated. This couples the block address WRAC to the CMOS latch 736. The block address allowable word in the latch exchange element 530 is latched The group addresses WADD0, ..., WADD6 can start other groups without waiting for the corresponding group operation to complete during multiple groups of operations. In addition, during multiple groups of operations, a parallel refresh operation can be issued within each group startup cycle Illustrated by an example, the first and second arrays are started for refresh and memory access operations. Then, without waiting for the completion of the first and second memory array operations, memory access can be enabled for the third group While simultaneously issuing refresh operations for the fourth array in parallel. The column decoder 720 activates the word line WL. As discussed above, the decoded bits are determined by the address bits transmitted from the seven-bit swap element 530. When the word line When the exchange is high, the data bits in the read and write unit 715 are read and written via the bit line BL. The differential BL pair is advantageously coupled to the bit line sense amplifier 725 to amplify the small signal read from the unit 715. These Induction amplification The device is used to write data bits back to these units (715), which is well known and will not be discussed. Although the present invention has been discussed according to several preferred embodiments, those skilled in the art can design without departing from the present invention. Various alternative embodiments and amendments are provided. Therefore, the present invention is intended to include those alternative embodiments which are within the scope of the appended patent application. 98441.doc -16- 200539179 These alternative embodiments are provided. [Schematic description] Figure 1 is from 256 b / BL and 64 b / BL two DRAM arrays produced by the watch factory, the two curves of the analog sensor signal, which illustrate the change from data retention-driven design to memory availability-driven design. Fig. 2 is a block diagram showing a plurality of sets of DRAM memory devices, which illustrates how to improve memory availability by applying the parallel performance of the refresh operation while enabling the memory access of the prior art.

圖3為在記憶體晶片300内啟用一並行刷新模式之先前技 術方法，其藉由增加— SRAM，且以一用於在一時鐘週期内 接收與傳送資料的雙埠功能為特徵來增強記憶體晶片3〇〇。 圖4為藉由利用DRAM之一並行功能啟用一並行刷新模 式之2 —習知方法，其中藉由該並行功能，該記憶體組保 持在靖模式同時仍為記憶體組啟用一刷新操作。 _圖5為根據本發明之適用於具有分散列位址計數器之並 行刷新模式的記憶體架構。 口圖6為根據本發明之整合於每組dram内之列位址計數 裔的電晶體階層示意圖。 列位址與交換元件組成之 半導體記憶體晶片 dram記憶體組 半導體記憶體晶片 圖7為根據本發明之由一核心 詳細組架構。 【主要元件符號說明】 200 、210i、2i〇j 98441 .doc 300 200539179 310k DRAM ^ 320i 330j、330i 、610_0 、 610_1 、 2 、 610 3 、 610 4 310、310i、310j、 320s、320k、320j 330s 、 330k 310TAG 320TAG 330TAG 400 410、410i、410j DRAM 420i、420j 510 520 530 610 610 字元線 記憶體單元、資料位元 TAGf己憶體 字元線 記憶體單元 半導體記憶體晶片 組 指令埠 陣列 列位址計數器RAC 交換器、交換元件 計數器邏輯元件 610」、610_6 620 622 624 626 628 630 715 720 725 反相器 CMOS通閘 CMOS通閘 CMOS鎖存器 CMOS鎖存器 反相器 記憶體單元 列解碼器 感應放大器 98441.doc -18- 200539179 732 NMOS 734 NMOS 736 CMOS鎖存器FIG. 3 is a prior art method of enabling a parallel refresh mode in the memory chip 300, which enhances the memory by adding-SRAM and featuring a dual port function for receiving and transmitting data in a clock cycle Wafer 300. Fig. 4 is a conventional method for enabling a parallel refresh mode by utilizing a parallel function of DRAM, in which the memory group is kept in Jing mode while still enabling a refresh operation for the memory group by using the parallel function. Fig. 5 is a memory architecture suitable for a parallel refresh mode with a distributed column address counter according to the present invention. Figure 6 is a schematic diagram of the transistor hierarchy of the column address counters integrated into each group of dram according to the present invention. Semiconductor memory chip composed of column address and exchange element dram memory group Semiconductor memory chip FIG. 7 is a detailed structure of a core according to the present invention. [Description of main component symbols] 200, 210i, 2i〇j 98441.doc 300 200539179 310k DRAM ^ 320i 330j, 330i, 610_0, 610_1, 2, 610 3, 610 4 310, 310i, 310j, 320s, 320k, 320j 330s, 330k 310TAG 320TAG 330TAG 400 410, 410i, 410j DRAM 420i, 420j 510 520 530 610 610 word line memory cell, data bit TAGf memory byte line memory unit semiconductor memory chip set instruction port array column address Counter RAC switch, switching element counter logic element 610 ″, 610_6 620 622 624 626 628 630 715 720 725 Inverter CMOS open gate CMOS open gate CMOS latch CMOS latch CMOS latch inverter memory cell column decoder induction Amplifier 98441.doc -18- 200539179 732 NMOS 734 NMOS 736 CMOS latch

98441.doc -19-98441.doc -19-

Claims (1)

200539179 十、申請專利範圍·· 1 _ 一種半導體記憶體，其包括： 複數個記憶體陣列，每個陣列包括以一矩陣排列且由 唯一指派給該等記憶體陣列中之每一個的一列位址計數 * 器控制之複數個記憶體單元，該列位址計數器產生一第 一字組位址；及 用來在一刷新指令被發佈給一相應記憶體陣列時，在 口亥等。己丨思體單元内啟用一刷新操作之構件，該等記憶體 ® 單元由該第一字組位址識別出。 月长員1之半導體記憶體，其中該等記憶體陣列中之每 個進一步包含一至少兩個該等記憶體陣列共用之第二 組位址，且其令在一記憶體存取指令被發佈給-相應 。己隱體陣列時，_啟用構件在該等記憶體單元内啟用一 記憶體存取操作，該等記憶體單元由該第二字組位址識 別出。 籲3.，清求項2之半導體記憶體’其中該刷新指令由一刷新組 選擇矾號提供給一相應記憶體陣列。 4.如=求項}之半導體記憶體，其中該第一位址在該刷新操 作完成時，藉由遞增該列位址計數器而進行更新。 έ e长員3之半導體S己憶體，其中該記憶體存取指令由一 組選擇訊號提供給一相應記憶體陣列。 6· 東項5之半導體記憶體，其中該刷新組選擇訊號在該 …己It體陣列内啟用—刷新操作，㈣並行地在該第 一记憶體陣列内啟用一記憶體存取操作。 98441.doc 200539179 ★ι叫，項6之半導體記憶體，其中該刷新組選擇訊號在至 _員外5己憶體陣列内啟用一刷新操作，同時並行地在 人莫D己憶體陣列内啟用一記憶體刷新操作且在該第二 。己隐體陣列内啟用一記憶體存取操作。 之—，員6之半導體記憶體，其中該等複數個記憶體陣列 之母一個進一步包括用於選擇性地將該第一與該第二字 、，且位址輕合至該記憶體陣列内之列解碼器之交換構件， 且其中-刷新操作由該第—字組位址控制，且—記憶體 存取操作由該第二字組位址控制。 9·如請求項8之半導體記憶體，其中該等記憶體陣列之每一 :進：：包括字組位址鎖存器，該等字組位址鎖存器耦 斤一义乂換構件’且其中當該相應組選擇訊號被提供至 該第，記憶體陣列時，該第三記憶體陣列起始一記憶體 存取操作，而不用等待下述操作完成： a)在該第一記憶體陣列内之該刷新操作，與 W在該第二記憶體陣列内之該記憶體存取操作。 10.如請求項9之半導體記憶體’其中當一相應刷新組選擇訊 说被提供至一第四記憶體陣列時，該第四記憶體陣列起 始一記憶體刷新操作，而不料待下述操作完成： a) 在該第-記憶體陣列内之該刷新操作，與 b) 在该第二記憶體陣列内之該記憶體存取操作，同時並 行地在該第三記憶體陣列内起始一記憶體存取操作。 11 ·如請求項10之半導體記愔辦 己隐體，其中該刷新組選擇訊號在 至少一額外記憶體陣列内啟用一刷新操作，同時並行地 98441.doc 200539179 在該第一記憶體陣列内 二 内啟用一圮fe體刷新操作並在該第 二體陣列内啟用一記憶體存取操作。 12·如請求項丨丨之半導體 ,,^ 己^體，其中該刷新組選擇訊號在 至少一額外記憶體陣列内啟 ^㈣—刷新操作，同時並行地 在该弟四記㈣陣列内啟用—記憶體職操作並在該第 二§己憶體11車列内啟肖-記憶體存取操作。 13. 如請求項5之半導體記憶 豆 , s 4 /、中3亥刷新組選擇訊號與該 δ己匕體存取組選擇訊號相互獨立。 14. 如請求項7之半導體記憶體，盆 取組與該至少-個以上刷新/ 新組、該記憶體存 ^ 调以上刷新組互不相同。 15·:請：項10之半導體記憶體’其中用於啟動 =中：一個來執行-刷新操作或-組存取操作之；： 間隔比P返機存取週期時間長。 、 16.如請求項15之半導體記憶體，立 ,._ . ^ T用於啟動至少兩個印 憶體陣列來執行一刷新操作或一 1U^ ^ 組存取刼作之時間問碎 比該隨機存取週期時間短。 Ί Π ^ 17· —種半導體記憶體，其包括： 複數個記憶體陣列，該等記憶體陣列中之每—個 以-矩陣排列且由唯一指派給該等記憶體陣列中之:― 個的-列位址計數器控制之複數個記憶體單元，I 址計數器產生一第一字組位址； 以夕〗位 用來在-刷新指令被提供至一相應記憶體陣列時 該等記憶體單元内啟用—刷新操作之構件，其中該 憶體單元由該第一字組位址識別出； 己 98441.doc 200539179 耦合至少兩個記憶體陣列之共用第二位址；及 用於選擇性地將該第一與該第二字組位址 記Μ陣列中之每-個内的列解碼器之構件，其D中至該等 精由該第-字組位址在一第一記憶體陣列内啟用— 新操作’同時藉由該第二字組位址在—第二記 :: 内啟用一記憶體存取操作。 Μ 請求項17之半導體記憶體’其中該第_位址在該刷新 操作完成時，藉由遞增該列位址計數器而進行更新。200539179 X. Application Patent Scope ... 1 _ A semiconductor memory including: a plurality of memory arrays, each array including a column of addresses arranged in a matrix and uniquely assigned to each of the memory arrays A plurality of memory cells controlled by a counter, the column address counter generates a first block address; and is used when a refresh instruction is issued to a corresponding memory array, etc. The components that enable a refresh operation in the body unit are identified by the first block address. The semiconductor memory of month 1, wherein each of the memory arrays further includes a second set of addresses shared by at least two of the memory arrays, and which causes a memory access instruction to be issued Give-accordingly. When the hidden array is used, the _ enabling component enables a memory access operation in the memory units, and the memory units are identified by the second block address. Call 3. The semiconductor memory of claim 2, wherein the refresh instruction is provided to a corresponding memory array by a refresh group selection alum number. 4. The semiconductor memory such as = seeking term, wherein the first address is updated by incrementing the column address counter when the refresh operation is completed. The semiconductor S memory of the elder 3, wherein the memory access instruction is provided to a corresponding memory array by a set of selection signals. 6. The semiconductor memory of Dong item 5, wherein the refresh group selection signal enables-refresh operation in the… It array, and concurrently enables a memory access operation in the first memory array. 98441.doc 200539179 ★ The semiconductor memory of item 6, wherein the refresh group selection signal enables a refresh operation in the memory array of the external memory, and simultaneously enables a refresh operation in the memory array of the human memory. The memory refresh operation is in this second. A memory access operation is enabled in the hidden array. Among them, the semiconductor memory of member 6, wherein the mother of the plurality of memory arrays further comprises for selectively selectively the first and the second words, and the addresses are lightly fit into the memory array. The exchange component of the decoder, and wherein-refresh operation is controlled by the first block address, and-memory access operation is controlled by the second block address. 9. The semiconductor memory according to claim 8, wherein each of the memory arrays: advance: includes block address latches, and the block address latches are coupled to replace the components. And when the corresponding group selection signal is provided to the first memory array, the third memory array starts a memory access operation without waiting for the following operations to be completed: a) in the first memory The refresh operation in the array and the memory access operation in the second memory array. 10. The semiconductor memory of claim 9, wherein when a corresponding refresh group selection message is provided to a fourth memory array, the fourth memory array initiates a memory refresh operation, but it is not expected that The operation is completed: a) the refresh operation in the first memory array, and b) the memory access operation in the second memory array, while starting in parallel in the third memory array A memory access operation. 11 · The semiconductor memory bank of claim 10, wherein the refresh group selection signal enables a refresh operation in at least one additional memory array, and at the same time 98441.doc 200539179 in the first memory array A memory refresh operation is enabled and a memory access operation is enabled in the second array. 12. · Semiconductor of the request item, wherein the refresh group selection signal enables refresh operation in at least one additional memory array and is enabled in parallel in the four memory arrays at the same time— The memory operation is performed and the memory access operation is initiated in the second §11 memory train. 13. If the semiconductor memory device of claim 5, s 4 /, 3, 3 refresh group selection signal and the δ hexadecimal body access group selection signal are independent of each other. 14. If the semiconductor memory of item 7 is requested, the fetch group is different from the at least one or more refresh / new groups, and the memory refresh and the refresh groups are different from each other. 15 ·: Please: The semiconductor memory of item 10 ', which is used for startup = Medium: One to perform a -refresh operation or -group access operation ;: The interval is longer than the P return access cycle time. 16. If the semiconductor memory of claim 15 is established, ._. ^ T is used to start at least two imprint memory arrays to perform a refresh operation or a 1U ^^ group of access operations. Short random access cycle time. Ί Π ^ 17 · —A type of semiconductor memory, including: a plurality of memory arrays, each of the memory arrays is arranged in a matrix and is uniquely assigned to one of the memory arrays: ― -A plurality of memory cells controlled by a column address counter, the I address counter generates a first block address; the bit is used to store the memory cells in the memory cell when a refresh instruction is provided to a corresponding memory array A component of the enable-refresh operation, wherein the memory unit is identified by the first block address; 98841.doc 200539179 has a common second address coupled to at least two memory arrays; and The first and the second block addresses are members of the column decoder in each of the M arrays, and D to the essence are enabled by the first block addresses in a first memory array. — New operation 'At the same time, the second block address is used to enable a memory access operation in —Second Note ::. The semiconductor memory of claim M17, wherein the _th address is updated by incrementing the column address counter when the refresh operation is completed. 98441.doc .4 -98441.doc .4-
TW094100085A 2004-01-15 2005-01-03 An embedded dram performing concurrent refresh mode with distributed row address counters TWI330368B (en)

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