TW200423385A - Pure CMOS latch-type fuse circuit - Google Patents

Abstract

An option fuse circuit, which can be viewed as a latch-type option fuse circuit, is produced via a standard single-poly CMOS manufacturing process. The option fuse circuit includes a non-volatile memory module for storing a logic data bit in a data program status, a data control circuit electrically connected to the non-volatile memory module for controlling operations of the option fuse circuit, and an output circuit electrically connected to the data control circuit for outputting the logic data bit in a data read status.

Description

200423385 V. Description of the invention (1) Technical field to which the invention belongs • The present invention provides a selective fuse circuit (〇pti〇n Fuse

Circuit), especially a single-poly CM0S Manufacturing process

Process) select fuse circuit. The previous technology is one of the most important components in various electronic products currently on the market. Memory (such as ROM, DRAM, and SRAM) has always been one of the most important components. It is used to store volatile and non-volatile data in electronic products. Features. A memory contains a plurality of memory cells (Memory Cel 1). Each memory cell is used to store a bit of digital data, and the plurality of memory cells are usually arranged in an array (Ar ^ ay), and is made in the form of integrated circuits using semiconductor processes. In the general semiconductor manufacturing process, since the yield cannot usually reach 100%, it is expected that a certain percentage of defective products will be generated during the manufacturing of integrated circuits, which is why from the manufacturing to the shipment of integrated circuits In the process, product testing steps are very important and indispensable. Only through the process of product testing can we screen out the incomplete or unusable products in the semiconductor process due to insufficient yield.

Page 6 200423385 V. Description of the invention (2) is out and eliminated, so as to ensure that the products obtained by the customers at the time of shipment are normal operating products. It can be seen that product testing is one of the very important processes in the semiconductor system. Because the memory contains a very large number of memory units (the current memory capacity is mostly tens to hundreds of megabytes (Mbyte), such as 64M, 128M, etc.), so there are so many memories In the body unit, the probability of failure of at least one memory unit will be very high, and if only one memory unit fails in a memory, the memory will be regarded as defective and cause it to be unusable. As a result, memory manufacturers will be greatly troubled. Therefore, in the design of general memory, a group of spare memory cells (Redundancy Cell) is usually added in addition to the original memory cell array, and a special circuit configuration design is used to control and select the group. The connection between the spare memory unit and the memory unit array. With this design, when a memory unit at a specific location in the memory unit array is found to be faulty during the product test process, the special circuit configuration can be used to control the set of spare memory units to It replaces the original function of the faulty memory unit, so that the memory is not scrapped due to the failure of a few parts, thus saving a lot of costs. This special circuit configuration is generally called Option Fuse Circuit. Please refer to FIG. 1. FIG. 1 shows a conventional selection fuse circuit 1 0—

Page 7 200423385 V. Description of the invention (3) e '一 " The intention of the embodiment. The selective fuse circuit includes two p-type metal oxide semiconductor transistors P1, P2, an N-type metal oxide semiconductor transistor N1, and two selective fuses, 12. Transistor P2 and transistor N 丨 are electrically connected to each other to form an inverter 14, in which the two gates are connected as the input terminal of the inverter 14 and the two drains are connected as the inverter 4 Output. One terminal of the transistor P1 and the selection fuse 丨 2 is electrically connected to the input terminal of the inverter 14, and the gate of the transistor p 丨 is electrically connected to the output terminal of the inverter i 4, and the The output terminal is an output terminal Vout which is one of the selection fuse circuits. Finally, the source of the transistor p2 is electrically connected to a system voltage Vdd ', and the source of the transistor N1 and the other end of the selection fuse 12 are electrically connected to the ground voltage Vs s. Please refer to FIG. 1, FIG. 2 and FIG. 3 at the same time. FIG. 2 shows a schematic diagram of the layout of the selected fuse 1 2 in FIG. 1. Generally, Hyun wire 12 is selected by using metal (poly) or polycrystalline silicon (Poli) line layout, and the fuse 1 2 can be used for point burnout according to needs during the product test phase, as shown in Figure 3. As shown, FIG. 3 is a schematic diagram of the layout of the selected fuse 12 in FIG. 2 after being blown. Because the selection fuse circuit J 〇 when the selection fuse 12 has not been blown and when it is blown, the signal value output by its output terminal vout is different (take the selection fuse circuit shown in Figure 1 as an example) When the selection fuse 12 has not been blown, Vout outputs a signal "丨" / that is, a high potential, and when the selection fuse 12 is blown, v〇ut outputs a ^ "" 〇 ", that is, a low potential) Then, in the circuit design of a memory, the output signal value of a plurality of selection fuse circuits 10 can be used to encode and determine the set of spare notes.

200423385 V. Description of the invention (4) What kind of combination of the memory unit replaces the memory unit of the memory unit array with ten failures. Please refer to FIG. 4, which is a schematic diagram of another embodiment of the conventional selective fuse circuit 20. The selective fuse circuit 20 includes two N-type metal oxide semiconductor transistors N2 and N3, a P-type metal oxide semiconductor transistor P3, and a selective fuse 22. Similar to the embodiment in FIG. 1, the transistor p 3 and the transistor N3 are electrically connected to each other to form an inverter 24. The source of the transistor P3 and the selection fuse 22 are electrically connected to a system voltage V dd, and The transistors N2, N3 are electrically connected to the ground voltage vss. Please note that the layout and operation of the selection fuse 22 in this embodiment can still refer to the selection fuse 12 shown in FIGS. 2 and 3. In this way, when the selection fuse 22 has not been blown out, the Vout output signal π 0 ”, that is, a low potential, and when the selection fuse 22 is blown, the Vout output signal turns 11 to a high potential, achieving the same effect as in the embodiment of the foregoing FIG. 'A plurality of selection fuse circuits can be used 2 The output signal value of 〇 is used to encode the set of spare memory units to replace the faulty memory unit in the memory unit array. However, because of the choice of 1 2 (or 2 2) in the layout, usually Sufficient space must be reserved in a certain area around it (as shown in Figures 2 and 3, 'reserving a space of 5 / z mx 5 / zm) to prevent damage to surrounding components during laser blowout' and in order to carry out The laser burns out. The oxide layer on the surface needs to be hollowed out to select an opening for the fuse 1 2 (or 2 2). However, this open product will cause water vapor to penetrate and corrode, which will damage other components and reduce 200423385 V. Description of Invention (5) Sin, this phenomenon is most obvious when the number of selected fuse circuits 10 (or 20) increases with the increase in memory capacity of a memory ^, the more choices of fuse circuits 10 ( Or 20) represents more reserved openings, thus increasing the chance of contamination of various components in the memory. The other side, because laser blowout is a relatively time-consuming process, it may be There will be a problem of incomplete cutting. During the test process, a large number of select fuses 12 (or 22) must be used to perform the blow operation, which also causes the test to take a long time. As mentioned earlier, multiple memories The structure is usually arranged in an array and fabricated in the form of integrated circuits using semiconductor processes. The complementary metal-oxide-semiconductor (CMOS) process is the most important and widely used semiconductor integrated circuit technology. In the application of the CMOS process, "n + poiy-Si" is also used as the gate of the n- and p-channel metal oxide semiconductors, which is called single polycrystalline silicon complementary metal oxide semiconductor. Process (Single-poly CMOS Manufacturing Process) has the important advantages of easy processing and low cost. Some conventional technologies use non-volatile flash memory and suitable circuit design to achieve the same purpose. ' In order to avoid the above problems caused by the use of electro-radiation technology, it also sacrifices the use of single-polycrystalline silicon complementary metal oxide semiconductor manufacturing processes, which can achieve low-cost control, and must use an additional layer of polycrystalline silicon in the manufacturing process. Even layer (Poly Silicon), thus increasing manufacturing costs

200423385 V. Description of the invention (6) Summary of the invention Therefore, the main object of the present invention is to provide a selective fuse circuit and a related method through a single polycrystalline silicon complementary metal oxide semiconductor manufacturing process to solve the above problems. The guide belongs to the system of knowledge, and the h-B narrator of the semi-selection of deposits will receive tch, and the pre-timed formula will be exempted from the formation of Lat, oxygen, and oxygen. The mode lock α8- hair test is a technical and memorable memorable latch type. It will be like a golden silicon chip, so it will be remembered that there is a lock W not low-type burning crystal. U due to the mutual electric power is suitable for silicon as M, relying on the use of silicon to create a non-operational view of the crystal can be used to make more than a dozen systems and a single circuit. No hair, an increase in the value of U wire production is based on the cost of the material and "in the present invention, we based on the system process, put forward one: 丨 Rongsi circuit, first, because of the oxide semiconductor process technology In the manufacturing process, only the flash memory needs to be used in the manufacturing process to store a digital logic data in the selection fuse circuit of the present invention. In the function, the selection fuse circuit of the present invention can be selected (ty P e). Decided the output signal in order to use the laser blowout technology is too long. The purpose of the present invention is to provide a selective fuse circuit (Option Fuse Circuit), which is passed through a single-poly CMOS complementary metal oxide semiconductor manufacturing process (Single-poly CMOS Manufacturing).

200423385 V. Description of Invention (7) ----

(Process), the selection fuse circuit includes a non-volatile memory module (Non-volatile Memory Module), which is used to store a digital logic data during a data writing phase; a data control circuit, Electrically connected to the non-volatile memory module for controlling the operation of the selection fuse circuit; and a round-out circuit electrically connected to the shell material control circuit for outputting and storing in the non-volatile during a data reading stage The digital logic data of the memory module. Jin Xinyi aims to provide a method based on a single polycrystalline silicon complementary metal oxide semiconductor process technology to complete a selective melting circuit. The selective fuse circuit includes a single polycrystalline silicon non-volatile memory module (Single-poly Non-volatile Memory Module), a data control circuit, and an output circuit, the method includes: using the data control circuit to switch the selection fuse circuit between a data writing phase and a data reading phase; using the The data control circuit stores a digital logic data to the single polycrystalline silicon non-volatile memory module during the data writing stage; and uses the data control circuit and the output circuit to output and store the non-volatile polycrystalline silicon non-volatile during the data reading stage. Modular = the digital logic data.丨 ^ Chess, and another object of the present invention is to provide a selective fuse circuit, the bean is produced by a single polycrystalline silicon complementary metal oxide semiconductor process. The selective wiremaking circuit includes a single polycrystalline silicon non-volatile memory unit ^ (S i ng 1 e-ρο 1 y Non-νο 1 ati 1 e Memory Ce 1 1).

200423385 V. Description of the invention (8) A digital logic data is stored for the data writing stage; a data control circuit is electrically connected to the non-volatile memory module for controlling the selection fuse circuit during the data writing stage and a The data reading operation is switched; an inverter is electrically connected to the data control circuit; and a swollen metal oxide semiconductor (NM0S) is electrically connected to the data control circuit and the inverter. Implementation

Please refer to FIG. 5, which is a schematic diagram of an embodiment of an option fuse circuit 3 0 (Option Fuse Circuit) according to the present invention. The selected fuse circuit 30 of the present invention is a single polycrystalline silicon complementary metal oxide semiconductor process (Single-p0ly CM0S Manufacturing).

Process), which can be used at good cost control and without the need for electric firing technology f. Use, select the fuse circuit. 30 contains a non-volatile memory module 32 (Non-vol at i le Memory Module), a The data control circuit 36 (Data control circuit) and an output circuit 38 are accompanied by an output terminal Dout. The non-volatile memory module 32 can also be implemented by using a single polycrystalline silicon complementary metal oxide semiconductor manufacturing process, which is used to store a digital logic data during a material writing stage and a data reading stage.

"ftf joint venture" control circuit 36 and output circuit 3 · output terminal Dout outputs it digital logic data, this non-volatile memory module 32 has the function of latching data in data processing, which means that the selective fuse circuit of the present invention 3 0 can be regarded as a latch-type (Latch-type ^ select fuse circuit 30.

Page 13 200423385

Please refer to FIG. 6, which is an example of the fuse circuit 30 selected in FIG. In FIG. 6, the output circuit 38 in FIG. 5 is an inverter 34, two P-type metal oxide semiconductor (PM0s) transistors p5, and: two N-type metal oxide semiconductor (NM0s) transistors N4. , N5, the source and drain of the second and second transistors P5 and P6 are connected to each other, and the drains of the other two transistors N4 and N5 are also electrically connected to each other, and are connected to each other. Crystals P5, P6 and inverter 34. The non-volatile memory module 32 is an embedded single-time programmable memory cell (Embedded 0TP, Memory Cell), which is still a memory cell that can be implemented using a single polycrystalline silicon complementary metal oxide semiconductor process. In actual implementation, Can be a floating gate p-type metal oxide semiconductor embedded single programmable memory cell (Floating-gate PM0S Embedded OTP Memory Cell) with a floating gate (FG) or a floating gate N-type metal oxide semiconductor ( Float ing-gate NMOS) embedded single-time programmable memory unit. Next, a preferred embodiment will be used to explain the operation principle of the selection fuse circuit 30 in FIGS. 5 and 6 in detail. Please refer to FIG. 7, which is a selection fuse circuit 50 in a preferred embodiment of the present invention. Schematic. The selection fuse circuit 50 of this embodiment includes a non-volatile memory module 5 2 (

200423385 V. Description of the invention (in) single-time programmable memory cell), three-type metal oxide semiconductor transistors N6, N7, N8, three p-type metal oxide semiconductor transistors P4, P 7, P 8 'And an inverter 5 4. The non-volatile memory module 5 2 can correspond to the non-volatile memory module 3 2 in FIG. 5 and the embedded single-time programmable memory unit 3 2 in FIG. 6. The three have the same function and meaning; the transistor M6 , N7 'P7, P8, and inverter 54 may correspond to the transistors IH, P5, P6, and inverter 34 of FIG. 6, respectively, and may also be combined with the output circuit 38 corresponding to FIGS. 5 and 6, which can be regarded as The output circuit 58 is one of the embodiments, and the transistor P4 and the transistor N8 can be regarded as a part of the data control circuit of the embodiment. Testers and users can control the operation of the selection fuse circuit 50 by using the potential of a plurality of endpoints, including the endpoint vCp (connected to the non-volatile memory module 52), the endpoint PGM, the endpoint DIN, Endpoint BIAS, end re, and end point ZEN. Some specific memories are re-selected. The faulty way in the memory is 50. Among them, the data writing stage enters the data writing data (1 or 0). Figure 8 lists the resources. Continue to see Figure 7. In the process of product testing, the process personnel found that there is a memory cell failure in a memory cell array, then the tester will perform a write operation on the selected fuse circuits 50 to select a preset one. A plurality of spare memory units are used to replace the memory unit, and the plurality of fuse circuits will be selected here, that is, the fuse circuit of Figure 7 is selected, and the operation principle of the section will be explained. When the fuse circuit is selected, At this time, the main purpose is to enter the number of decisions into the non-volatile memory module 52. Please also refer to Figure 8

200423385 V. Description of the invention (π) The voltage value of each end point in Figure 7 when the material is written. In the data writing stage of the embodiment in FIG. 7, the terminal VCP voltage is Vpp, and the voltage Vpp is a high potential higher than the general voltage Vdd. The terminal RE is connected to the high voltage Vdd and the terminal Bias ^ voltage Vpp to turn off the transistor P4. The terminal PGM is connected to the high potential Vdd to turn on the transistor N8. The terminal ZEN is connected to a high potential Vdd to turn off the transistor p7. If the digital logic data to be written is 1, the terminal DIN is a high voltage vdd. In this way, the node DLU voltage is a higher voltage Vpp, non-volatile One of the floating gates FG of the memory module 52 loads no electrons and regards it as an ERASE state. If the digital logic data to be written is 0, the terminal DIN is low voltage Vss, then the node DLU voltage is low voltage Vss, and the floating gate FG of the non-volatile memory module 52 will be loaded with electronics, which is regarded as a program. Yes (PGM state). Note that the failure action of the fuse unit is to record the original description of the filament through the memory electronic circuit. After the theory of the latching circuit is shown in Fig. 7, when the whole assembly is installed in an electronic product and the power is turned on, the memory 50 reads the action to select the correct one, so that it can be used. The function of the memory unit makes it clear that the selection fuse circuit 50 of the plurality of selection and refining is used for further explanation. Furthermore, the technical characteristics of the information in this embodiment can be more clearly described as a latch type (Latch type). -type). When the user realizes that the plurality of memory circuits capable of normal memory 50 when its data is read and processed, it shows that the selection fuse is deemed to be qualified to replace the memory with the plurality of selection memories of the memory. One is to clearly describe the invention of selecting a fuse circuit in terms of operation. Please continue

Page 16 200423385 V. Description of the invention (12) Refer to Figure 7 and Figure 8. The data reading stage is mainly to read the digital logical data stored in the non-volatile memory module 52. According to the table shown in Figure 8, during the data reading phase of the embodiment of Figure 7, the voltage source ν [ρ voltage is Vdd. The terminal PGM is connected to the low potential VSS to turn off the transistor N8, the terminal B ^ s is connected to an ideal voltage Vb, and the transistor p4 is appropriately turned on, so that the transistor p4 is in an ideal state. The electricity of the control node DLU is at an ideal value. Prevent read disturbance (Read Disturb) from occurring in the non-volatile memory module 52 during reading. The so-called read disturbance is to write trace data to the non-volatile memory module 5 2 when the digital logic data is read. Into the effect. The terminal ZEN is connected to the low potential Vss to turn on the transistor P7. The terminal re is firstly a high potential Vdd, and after a suitable delay (after an ideal time), the terminal RE is connected to a low potential Vss. If the non-volatile memory module 52 is in the form of a program (PGM state), the node DL is at a high potential, and the output terminal Doot is at a low potential Vss, then the transistor N6 is turned off, the transistor p8 is turned on, and the node is latched. At a high potential, the output terminal Dout is latched at a low potential Vss. If the non-volatile memory module 52 is erased, the node DL is at a low potential, and the output terminal "" is a high potential and a low potential, then v transistor f, transistor P8 is closed, and node_flash lock At the potential Vss, the output knowledge point Dout is flash-locked to the high potential vdd, and then the terminal ZEN is connected to the high potential Vdd to turn off the transistor p7. The above facts have revealed the flash lock data and stable output data signals:

Circuit selection material circuit can be regarded as -flash lock type S

200423385 V. Description of the invention (13) Compared with the Xisi circuit, a non-volatile memory is used to store a digital material control circuit. The non-volatile memory control circuit and phase avoid the decrease in the degree of knowledge and test the silk circuit. It is manufactured by Jiexiu, and the technology that is exempt from learning is covered by the patent scope mentioned above. Known selective fuse circuit technology, the selective latch-type selective fuse circuit of the present invention utilizes the logic data of the 愫 module (an embedded single-time programmable memory unit) during the data writing stage. Use the relevant data to cooperate with the operation, store a preset digital logic data into the module, and in the data reading phase, use the data wheel out circuit to output the digital logic data. In order to use the laser blowout technology, The problem of too long reliable time is also due to the selective melting of the present invention; single polycrystalline silicon oxide complementary metal oxide semiconductor = = only one layer of polycrystalline sand is needed in the process, so it can also be avoided. The problem of increasing manufacturing cost. It is only a preferred embodiment of the present invention. Any equal change and modification according to the present invention belongs to the end of the patent chapter of the present invention. 200423385 Schematic description of the diagram. Schematic of the examples. FIG. 2 is a schematic diagram of the layout of the fuse selected in FIG. 1. FIG. 3 is a schematic diagram of the selected fuse layout of FIG. 2 after being blown out. FIG. 4 is a schematic diagram of another embodiment of a conventional selective fuse circuit. FIG. 5 is a schematic diagram of selecting a fuse circuit according to the present invention. FIG. 6 is a schematic diagram of an embodiment of the selective marry silk circuit of FIG. 5. FIG. 7 is a schematic diagram of a preferred embodiment of a selective fuse circuit of the present invention. Figure 8 is a list of the voltage values of the endpoints in the embodiment of Figure 7 during the data writing phase and the data reading phase. Explanation of symbols in the drawings 1 0, 2 0, 3 0, 5 0 Select fuse circuit 1 2, 2 2 Select fuse 14, 24, 34, 54 Inverter 3 2, 5 2 Non-volatile memory module 36 Data control circuit 38, 58 output circuit

Page 19

Claims (1)

200423385 6. Scope of patent application 1. An option fuse circuit is generated by a single poly CMOS complementary metal oxide semiconductor manufacturing process (Singlepoly CMOS Manufacturing Process). The option fuse circuit includes ... Non-volatile memory module (N ο η-v ο 1 ati 1 e M em 〇ry Module), used to store a digital logic data in a data write stage; a data control circuit, electrical connection The non-volatile memory module is used to control the operation of the selection fuse circuit; and an output circuit is electrically connected to the data control circuit for outputting the data stored in the non-volatile memory module during a data reading phase. The digital logic data. 2 · Select the fuse circuit according to item 1 of the patent application scope, wherein the output circuit includes an inverter, two p-type metal oxide semiconductors (PM0S), and two N-type metal oxide semiconductors (nm0S) . 3. If the selective fuse circuit of item 1 of the scope of patent application is applied, when the selective fuse circuit is in the data writing stage and the digital logic data is 1, the non-volatile memory module is in an erased state (ERASE state). 4 · If the selective fuse circuit of item 3 of the patent application scope, wherein when the selective fuse circuit is in the data writing stage and the digital logic data is 0, the non-volatile memory module is in a program state (pGM state). Page 20 200423385 5 · If you choose the fuse circuit of item 1 of the patent application scope, the non-volatile memory module is an embedded single programmable memory cell (Embedded OTP Memory Cell). 6 · If you choose a fuse circuit for item 5 of the scope of patent application, the non-volatile memory module is a floating gate p-type metal oxide semiconductor (Floating-gate PM0S) embedded single programmable memory unit or a Floating-gate N-type metal oxide semiconductor (Floating-gate NM0S) embedded early programmable memory cell. 7. · A method based on a single polycrystalline silicon complementary metal oxide semiconductor process (Single-poly CMOS Manufacturing Process) technology to complete an Option Fuse Circuit, the selective fuse circuit includes a single polycrystalline silicon Non-volatile memory module (Single-poly Non-volatile Memory Module), a data control circuit, and an output circuit, the method includes: using the data control circuit to select the selected fuse circuit in a Switching between a data writing phase and a data reading phase; using the data control circuit to store a digital logic data to the single polycrystalline silicon non-volatile memory module in the data writing phase; and using the data control circuit and The output circuit outputs the digital logic stored in the single polycrystalline silicon non-volatile memory module during the data reading stage. Page 21 200423385 Editing information. 8. The method as described in item 7 of the scope of patent application, which further includes: when the selection fuse circuit is in the data writing stage and the digital logic data is 1, use the data to control the circuit to make the single The polysilicon non-volatile memory module is in an ERASE state; and ° When the selection fuse circuit is in the data writing stage and the digital logic data is 0, the data is used to control the circuit to make the single polysilicon non-volatile memory The volatile memory module is in a PGM state. ° 9 · The method as described in item 7 of the scope of patent application, wherein the single polycrystalline silicon non-volatile memory module is a floating gate P-type metal oxide semiconductor (Float ing-gate PM0S) embedded single-shot Programmable memory cell (Embedded OTP Memory Cell) or a floating gate n-type metal oxide semiconductor (Floating-gate NM0S) embedded single programmable memory τνσ early in the morning 70. 10. The method according to item 7 of the scope of patent application, wherein the output circuit comprises an inverter, two P-type metal oxide semiconductors (PM0S), and two N-type metal oxide semiconductors (NM0S). 11. · An option fuse circuit is produced by a single poly CMOS manufacturing process (Singlepoly CMOS Manufacturing Process). 200423385 The silk circuit includes: (Single-poly Non- data write stage stores a single polycrystalline silicon non-volatile memory cell volatile Memory Cell), used for a digital logic data; a-shell material control circuit (Data control circuit), Electrically connected to the non-volatile memory module for controlling the selection fuse circuit to switch between the data writing phase and a data reading phase; a P-type metal oxide semiconductor (PM0S), electrically connected to the The source and drain of the P-type metal oxide semiconductor in the eighth data control circuit are connected to each other; ”, a secondary inverter is electrically connected to the two p-type metal oxide semiconductors. A conductor; and an N-type metal oxide semiconductor (NM0S), which is electrically connected to the two p-type metal oxide semiconductor and the inverter. 1 2 • The selection fuse circuit according to item 11 of the scope of patent application, wherein when the selection fuse When the wire circuit is in the data writing stage and the digital logic data is 1, the single polycrystalline silicon non-volatile memory module is in an ERASE state. 0 3 Selection fuse circuit, wherein when the selection fuse circuit and the read phase of the data in the single polysilicon non-volatile memory module based on the erased state, the selection fuse circuit outputs the output signal of a high potential. Page 23 200423385 6. Scope of patent application 1 4. If the selection fuse circuit of item 11 of the scope of patent application is applied, when the selection fuse circuit is in the data writing stage and the digital logic data is 0, the non-volatile The sexual memory module is in a PGM state. 15. If the selective fuse circuit of item 14 of the scope of patent application is applied, when the selective fuse circuit is in the data reading stage and the single polycrystalline silicon non-volatile memory module is in the program state, the selective fuse The circuit outputs a low-level output signal. 16 6. The selective fuse circuit according to item 11 of the scope of patent application, wherein the single polycrystalline silicon non-volatile memory cell is a floating gate P-type metal oxide semiconductor embedded single-time programmable memory cell (Floating-gate PM0S Embedded OTP Memory Cell) or a floating gate N-type metal oxide semiconductor (Floating-gate NM0S) embedded single-time programmable memory.