TW200421699A - Controller for DC to DC converter - Google Patents

Abstract

A switching circuit includes at least one switch, and a controller configured to provide a periodic control signal. The switch is responsive to the periodic control signal to change states with a start of each period, and a frequency of the periodic control signal has a predetermined minimum frequency level greater than an audible frequency limit for humans. The switching circuit may be used to control a high side switch and a low side switch in a DC to DC converter. A controller having an input voltage sensing circuit to sense an input of a DC to DC converter without using an additional input pin is also provided. Related methods are also provided. A dual phase controller having a phase selection circuit to select between phases is also provided.

Description

200421699 发明 Description of the invention: [Cross-reference of related applications in the technical field 3 to which this invention belongs] This application is a follow-up application of US Provisional Application No. 5 10 / 389,037 filed on March 14, 2003. This is incorporated by reference, and both applications claim the benefit of US Provisional Application No. 60/425, 553, filed November 12, 2002, the teachings of which are also incorporated herein by reference. FIELD OF THE INVENTION The present invention relates to a controller for a DC / DC (DC to DC) converter, and more specifically to a controller for controlling an inductor current level without directly measuring the current level. t Prior Art 3 Background of the Invention 15 A DC / DC converter is used to convert an input DC voltage to an output DC voltage. This type of converter can reduce or increase the input DC voltage. One step-down converter is a synchronous step-down converter. The converter usually has a controller, a driver, a pair of switches, and an inductive capacitor (LC) filter connected to the pair of switches. The controller provides a control signal 20 to the driver to drive the pair of switches, such as a high-side switch and a low-side switch. The driver alternately closes and opens each switch to control the inductor current and the output voltage of the DC / DC converter. The controller usually uses a PWM signal to control the state of the high-side and low-side switches. Generally, if the PWM (Pulse Width Modulation) signal is high, the high-side switch 5 200421699 is closed (ON) and the low-side switch is open (OFF). This switching state is referred to herein as the "switch ON" state. In this state, the inductor is connected to the input voltage source. For a buck converter, the input voltage must be greater than the output voltage, so when the switch is closed, there is a net positive voltage on the inductor. Therefore, the inductor current starts to ramp up. If the PWM (Pulse Width Modulation) signal is at the low level, the high-side switch is open (OFF) and the low-side switch is closed (0N). This switching state is referred to herein as a "switch OFF" state. For a buck converter, there is a net negative voltage across the inductor in this switch-off state. As a result, the inductor current starts to decrease with the slash 10 in the switch-off state. Therefore, the pulse width of the PWM (Pulse Width Modulation) signal determines the closing time of the switch-on state and the opening time of the switch-off state. This pulse width can be adjusted by monitoring the inductor current level directly with a sense resistor or comparing the output voltage and reference voltage levels. Therefore, there is a need in the art for the controller 15 for a DC / DC converter, which is provided in the first time interval according to the difference between the input voltage of the DC / DC converter and the signal representing the output voltage. A PWM (Pulse Width Modulation) signal. [Summary of the Invention] Summary of the Invention 20 In one embodiment, a switching circuit of the present invention includes at least one switch and a controller that generates the cycle control signal. At least one switch responds to the cycle control signal and changes state at the beginning of each cycle of the cycle control signal, where the frequency of the cycle control signal has a preset minimum frequency value greater than the audible frequency range of the human ear. 6 200421699 In another embodiment, a switching circuit of the present invention includes at least one switch and a controller that controls at least one switching state by a cycle control signal. The at least one switch responds to a cycle control signal and changes state at the beginning of each cycle of the cycle control signal. The controller also has 5 skip modes (skiPmode), in which the controller keeps at least one switch in the OFF state. The controller responds to a timer, which counts a preset time interval based on the start of each cycle of the cycle control Shao Lu, wherein the controller starts one of the cycle control signals in response to the end of the preset time interval. For a new period, the preset time signal is set to obtain a preset minimum frequency value of 10 period control signals greater than the minimum audible audio frequency of the human ear. = In another embodiment, a method is provided to keep the minimum frequency of the switching state greater than the audible frequency of the human ear. The method of the present invention includes: starting the timing of the pre-a time interval at the start of the first state switching of the switch to the first state; monitoring the state of the switch; and if the switch is still in the first state, changing the state of the switch to In response to the expiration of the preset time interval, < the minimum frequency of the state of the hold switch is greater than the audible frequency of the human ear. In another embodiment, a DC / DC converter for converting an input voltage to a wheel-out voltage is also provided. The DC / DC converter package 20 carries a first time interval in a first state based on a difference between a first signal representing an input voltage and a second signal representing an output voltage signal. A controller for a PWM (pulse width modulation) signal in a state; a driving circuit that receives at least the PWM signal and generates a switch driving signal; a pair of switches including a high-side switch and a low-side switch, the on / off switch The pair is in response to the switch driving signal being driven to the switch-on state, where the high-side switch is closed and the low-side switch is open when the PWM signal is in the first state; and an inductor connected to the output of the pair of switches, where the switch is closed The current level of the inductor increases in a state; and a logic circuit that provides a low-side enable signal with an enabled state and an inactive state, where the PWM signal controls the low-side when the low-side enable signal is in the enabled state Switch, the logic circuit receives a comparison signal from an over-current comparator, wherein the over-current comparator is based on a current level flowing through the inductor and a Comparison of critical current values to provide a comparison signal if the current level flowing through the inductor current is greater than the threshold value, the logic circuit is also provided in the lower side of the disable status enable signal. In another embodiment, a method for detecting an input voltage level of a DC / DC converter using an existing pin connected to a switching node of the DC / DC converter is provided. The method includes: determining a state of a high-side switch connected to an input voltage source and a switching node; determining a state of a low-side switch connected to ground and the switching node; and detecting an input voltage when the high-side switch is closed and the low-side switch is open . In another embodiment, the controller of the DC / DC converter of the present invention includes an input pin terminal connected to a switching node of the DC / DC converter; when the high-side switch is closed and the low-side switch is open A switching node of a DC / DC converter connected to the input voltage; an input voltage detection circuit connected to the input pin terminal. The input voltage detection circuit includes: a switching state judging circuit, when the parent switching node is connected to the input voltage based on the states of the high-side switch and the low-side switch, the switching state judging circuit responds to detect and provide a judgment signal; And a voltage detection circuit, the voltage detection circuit responds to a determination signal indicating a switching node connected to the input voltage, thereby detecting a voltage level indicating the input voltage. In another embodiment, a dual-phase DC / DC controller of the present invention includes: a first phase controller to provide a first PWM signal based on an input voltage representing a DC / DC converter The difference between the first signal of the DC signal and the second signal of the output voltage of the DC / DC converter; a second phase controller that provides a second PWM signal; the second PW M signal is based on the A difference between the first signal of the input voltage and the second signal representing the output voltage of the DC / DC converter; and a phase selection circuit for selecting the first phase controller and the second phase controller. In another embodiment, a controller is provided that is capable of providing a control signal to control the state of at least one switch. The controller includes a time interval for the preset time interval after ^ switches change the state to the first state. If at least one switch is in a Ga state from the beginning of the preset time interval, the controller switches at least one of the minimum 'of the preset time interval settings to ensure state switching' in response to the end of the time interval, and the item rate is greater than that of a human ear. The advantages of t, and in the simple illustration of the audio-frequency diagram can be considered in the following exemplary implementations of the present invention; and these descriptions should be accompanied by the drawings to instruct the figures: Figure 1A shows the present invention. A block diagram of a DC / 200421699 DC (DC to DC) converter including a controller; Figure 1B shows the input PW M (pulse width modulation) signal and the low-side enable signal, as shown in Figure 1A An exemplary table of the switching states of the pair of switches; FIG. 2A shows a block diagram of an embodiment of a controller for the DC / DC converter of FIG. 1A; FIG. 2B shows a description of FIG. 2A The comparison curve of the change of the charging level of the energy memory element of the controller and the corresponding change of the inductor current level in the same time interval; Figure 3 shows the DC for Figure 1A A block diagram of another embodiment of the controller 10 of the DC converter; FIG. 4 shows a detailed block diagram of the exemplary delay circuit in FIG. 3; FIG. 5 shows a DC / DC converter used in FIG. Block diagram of another embodiment of a controller of a DC converter; Figure 6 shows a block diagram of an exemplary two-phase controller; 15 Figure 7 shows an input voltage detection using the controller's LX pin Circuit diagram of the circuit; Figure 8 shows a block diagram of another embodiment of the controller with an internal timer for controlling the minimum switching frequency of the present invention; Figure 9 shows a The timer is used to control the block diagram of the DC / DC converter with a minimum switching frequency of 20; and Fig. 10 shows the timing diagrams of the embodiments of Figs. 8 and 9. [Embodiment 3 Detailed Description of the Preferred Embodiment According to the present invention, FIG. 1A shows an exemplary DC / DC converter 100 including a controller 102 10 200421699. The controller 102 can be used for various DC / DC converters. The DC / DC converter 100 shown is a synchronous step-down converter, which typically includes a controller 102, a driver circuit 104, a pair of on and off switches including a high-side switch Q1 and a low-side switch Q2. 106 and a low-pass filter 108. The low-pass filter includes an inductor L and a capacitor C. The controller 102 is generally used to provide a PWM (pulse width modulation) signal and a low-side switch enable signal (LDRJEN) to the driver circuit 104. Based on these signals, the driver circuit 104 can control the states of the high-side switch Q1 and the low-side switch 10 Q2. The controller 102 has an input pin SLEW which can set a desired output voltage target. In the exemplary embodiment of FIG. 1A, a siew capacitor Cslew is charged based on the resistance value in the resistor divider R2 / R3 and the reference voltage value REF. Those skilled in the art will know various methods to charge the slew capacitor and generate a target voltage signal. In this embodiment, the voltage swings from 0 to a value set in accordance with the swing capacitance Cslew. An optional sense resistor R1 can be used to provide a feedback voltage value representing the level of the current flowing through the inductor L to the pins CSN and CSP of the controller 102. In addition, the VFB pin of the controller 102 can receive a feedback signal No. 20 indicating the output voltage level. Fig. 1B shows an exemplary table of each switching state of the high-side switch Q1 and the low-side switch Q2 in Fig. 1A under various PWM (pulse width modulation) signal and LDRJEN signal states. If the LDR_EN signal is bit 1 of column 122 in Table 120, then the state control switch of the PWM (pulse width modulation) signal is 11 200421699 Q2. For example, in the column 122, if pwm (pulse width modulation) is a digit 1, Q1 is closed (ON) and Q2 is open (OFF). This state is called the switch-on state. In addition, in this column 122, if the PWM (pulse width modulation) is a number 0, Q1 is OFF and Q2 is ON. This state is called the 5-switch off state. In contrast, if the LDR_EN signal is digital 0 and the PWM (pulse width modulation) is digital 1, the switches Q1 and Q2 are in the switch closed state. However, if PWM is digital 0, the low-side switch Q2 remains off. In this way, the high-side switch qi and the low-side switch Q2 are both OFF (skip state) or switch 10 disable state (OFF). One end of the inductor L is connected to the output DC voltage, and the other switch end is alternately connected to the input voltage Vin or the ground according to the states of the switches Q1 and Q2 (the switch is on or off). When the switch is closed, the inductor is connected to the input voltage Vin. Ignoring the small voltage drop across the sense resistor R1, the voltage difference across the inductor L15 is equal to Vin-Voixt. In a buck converter, the input voltage Vin must be greater than the output voltage Vout, so there is a net positive voltage on the inductor, and the inductor current rises according to Equation 1 during the switch closure. (1) di / dt = (Vin-Vout) / L =) I / Ton In Equation 1, Vin is the input voltage of the DC / DC converter, and vout is the output voltage of the DC / DC converter. Ton is the switch The time interval 'L' in which Qi and Q2 are in the switch-on state is the value of inductor L, and 1) is the change in inductor current during Ton. During the switch-off period, the voltage across inductor L is proportional to Vout. In the buck converter in this example, there is a net negative voltage on the inductor and the inductor current drops according to the diagonal line of Equation 2. 12 200421699 (2) di / dt = (Vout) / L =) I / Toff In formula 2, Vout is the output voltage of the DC / DC converter, Toff is the time interval when switches Q1 and Q2 are in the off state, L Is the value of inductance L, and) 1 is the change in inductor current during Toff. 5 FIG. 2A shows a more specific block diagram of an embodiment of the controller 200 for the DC / DC converter in FIG. 1A. Generally, the controller 200 provides a digital 1 PWM (pulse width modulation) signal based on the difference between the first signal representing the input voltage and the second signal representing the output voltage signal to place the switches Q1, Q2 on the switches Closed. The second signal can be a target voltage level signal such as Vslew, or an output voltage level signal such as Vout. Normally, using a target voltage level signal produces a smoother current. In a buck converter, the duty cycle of the PWM (pulse width modulation) signal generated by the controller 200 is usually inversely proportional to the difference between the input voltage and the output voltage or target voltage. In other words, as the difference increases by 15, the duty cycle of the PWM (pulse width modulation) signal decreases, thereby reducing the switch-on time of switches Q1 and Q2. Conversely, as the difference between the first signal and the second signal decreases, the duty cycle of the PWM (pulse width modulation) signal increases, thereby reducing the "switch-off," time of switches Q1 and Q2.

In the embodiment shown in Figure 2A, this control is usually dominated by charging the energy storage element during the first time interval of 20 and discharging the energy storage element during the second time interval. During the first time interval, the PWM output signal is digital 1, so switches Q1 and Q2 are in the switch-on state, and the inductor current increases proportionally with the voltage on the energy storage element 202. Once the voltage on the energy storage element 202 reaches a preset voltage threshold, the PWM 13 200421699 signal becomes a digital zero, so the switch is driven to the switch-off state. Therefore, the inductor current decreases proportionally as the voltage on the energy storage element 202 decreases. The controller 200 typically includes different current sources II, 12 and 13 which charge and discharge the energy memory element 202 based on the respective comparison voltages generated by the comparators CMP2, CMP3 and CMP4. The first current source II is proportional to the output voltage or the target voltage, such as Vslew, and is used to provide a first current level. The second current source 12 is proportional to the input voltage of the DC / DC converter and is used to provide a second current level. Finally, the third current source 13 is proportional to the output voltage and is used to provide a third current level. The third current level is usually greater than the first current level, but it does not have to be greater. The third current source 13 is not necessary. However, it can eliminate the parasitic trigger of a new PWM pulse. If a third current source is not used, the switch S2 can directly discharge the energy storage element 202. The controller 200 may further include an output decision circuit 240 to provide a PWM signal to the switch driving circuit. The controller 200 may further include a first comparator CMP1 for comparing the voltage on the energy storage element 202 (for example, the capacitor C1) with the second reference voltage V2. The second reference voltage V2 may be a rated voltage, for example, 20 is 20 millivolts in one embodiment, and is connected to the positive pin of the comparator CMP1, so that when the voltage on the energy memory element 202 is less than the rated voltage V2, CMP1 provides a high signal.

The output of the comparator CMP1 can also be connected to the inverse gate G1. One SKIP input can be connected to the other input of the inverse gate G1. If the SKIP 14 200421699 signal is 0 ', regardless of the signal of the comparator CMP1, the LDR_EN signal is a digital one, so that the PWM signal controls the states of the switches Q1 and Q2. However, if the SKIP signal is a digital one and the output of the comparator cmpi is also a digital one, the output of the inverse gate G1 is a digital zero. As such, if Pwm is a digit 0, both switches 5 Q1 and Q2 are driven to the off state. During operation, because the voltage on the energy memory element 202 is discharged to ground, the voltage on the energy memory element 202 is initially set to 0 volts, and the output determination circuit 240 provides a PWM signal with a number of zero. When the controller is enabled, the SLEW voltage will increase from zero to a ratio based on R2 and R3. Comparator 10 CMP3 then detects that the SLE W voltage is greater than the feedback voltage VFB 'indicating the output voltage Vout, so a digital 1 signal is provided to the AND gate G2 of the output determination circuit 240. Because no current flows through the inductor L, the comparator CMP4 does not detect To any overcurrent condition, so a digital 1 signal is provided to the gate G2. In addition, because the voltage on the energy storage element 202 is discharged to 0 volts, when the voltage is compared with the rated threshold voltage V2, the output signal of the comparator CMP1 is also a digital one. In this way, all the input signals of the gate G2 are digital ones, so the flip-flop 242 is triggered. At this time, the PWM signal becomes digital 1 and the switch S1 is closed. When the switch S1 is closed, the energy memory element 202 is charged by a current equal to the second current level provided by the second current source minus the first current level provided by the first current source. Advantageously, the first current level provided by the first current source may represent an output voltage, for example, may be proportional to an output voltage value such as Vout, or a target voltage level such as Vslew or Vtarget. As such, the energy memory element 202 is composed of one proportional to I (Vin-Vout) or (Vin-15 200421699

Vslew). The energy storage element 202 is charged until a predetermined threshold voltage level is reached, such as 2.5 V in one embodiment or VI. The comparator CMP2 compares the voltage on the energy storage element 202 with a preset threshold voltage value 5 and generates an output signal to the output determination circuit based on the difference between them. If the voltage of the energy storage element 202 reaches the preset threshold voltage value VI, the comparator CMP2 will output a digital 1 signal to the reset pin R of the flip-flop 242 to reset the flip-flop, so that the output q of the flip-flop becomes It is digital zero, so that the PWM signal also becomes digital zero. 10 At this time, because the output Q of the flip-flop is digital 0, the switch S1 is turned off. As such, the energy storage element 202 is discharged by the current source 12. If the output of the AND gate G3 is a digital one, the energy storage element 202 will accelerate the discharge. If pwm believes

The number 0 is digital. The above situation will occur, so one input from the QB pin of the flip-flop 242 and the gate G3 is digital i. In addition, if the feedback voltage 15 VFBk is smaller than the SLEW voltage, the other input from the comparator CMP3 and the gate G3 is digital 1. As such, a digital operator at gate G3 will cause switch S2 to close. In this way, the third current source can be connected to the energy storage element 202 to provide accelerated discharge. In this implementation, the value of the current source 13 is ιχχ—Vout, which can be adjusted according to the specific energy memory element 202 and other parameters 20, so as to obtain a desired accelerated discharge level. In addition, the third current source 13 may be replaced by a short circuit, so that the switch S2 will discharge the energy storage element 202 to ground. sPWMW is a number 0, and the voltage level θ, ·, ’, and 贝 discharged by the energy memory element are discharged. According to the comparison between the comparator voltage Cmp3 and the feedback voltage 16 200421699 voltage VFB, the discharge can be normal speed or acceleration. Once the voltage level on the energy memory element 202 is discharged to a value less than the rated threshold V2 (the output of the comparator CMP1 is therefore a digital one), and the outputs of the comparators CMP3 and CMP4 are both a digital one. The output Q of the converter becomes digit 1 and a new PWM pulse is generated. In conjunction with FIG. 2A and FIG. 2B, a voltage level curve 203 on the energy storage element 202 is shown as a function of time. In addition, the curve 205 is the level of the inductor current on the inductor L during the same time interval. For example, at the start time (to) of the operation of the controller 200, the voltage on the energy storage element is 0 volts. During the tenth time interval or Ton between time to and t1, when the PWM output signal is digital 1, the voltage level on the energy memory element 202 increases linearly until it reaches a preset threshold VI, for example, in one embodiment Medium is 2.5 volts. In this way, Ton between t0 and tl depends on the difference between the signal representing the input voltage Vin and the signal representing the output voltage Vout or Vtarget, because the energy 15 of the memory element 202 during this time interval is formed by a Proportional current (current source 12-11) for charging. The duration of Ton also depends on the threshold voltage value VI and the voltage value of the energy storage element 202. Where the energy storage element is a capacitor C1 'and the second current source is proportional to Vout, the duration of Ton can be obtained by the following formula 3: 2 (3) Ton = Cl * Vl / I (Vin-Vout) where Cl is a capacitor The value of Cl, VI is a preset charge threshold (2.5 Volts in one embodiment). When the second current source is proportional to vout, I (Vin-Vout) is the second current source 12 and The charging current value provided by the difference between the first current sources II. 17 200421699 If Ton in equation (3) is used for the inductor current of equation (1), then equation (1) can be written as: (4)) I = (Vin-Vout) * (Cl * Vl / I (Vin- Vout)) / L Because (Vin —Vout) / I (Vin-Vout) are constants, then) I is also constant, and 5 is also constant for other terms (L, VI, and C1). As such, during the ton periods of t0 and t1, the inductor current rises proportionally as the voltage level on the energy storage element 202 rises. During the second time interval of t1 and t2, the voltage level on the energy storage element 202 decreases due to the discharge. In comparison, the inductor current level also decreases during this time. 10 Advantageously, when the voltage on the energy storage element 202 reaches zero, for example at time t2, the inductor current at time t2 should also be zero. In this way, the controller 200 also provides an inductor current estimator °. For each PWM pulse, when the initial inductor current is zero and the energy storage 15 element is completely discharged, the skip mode is When enabled (when the SKIP signal is digital 1). When the energy storage element is discharged below the rated voltage V2, the output of the comparator CMP1 becomes a digital one. If the skip mode is enabled, LDRJEN is set to digit 0 by the inverse gate G1. Therefore, when the inductor current is zero, the low-side switch Q2 and the high-side switch Q1 are turned off. Therefore, the switching side of the 20 inductor L will be left floating (floating). Skip mode is good for small load conditions, because when the load discharges the energy memory element, a new PWM cycle will begin, thereby reducing Q1 and Q2 switching and conduction losses. FIG. 3 shows another embodiment of the controller 300 of the present invention. Similar to the embodiment in FIG. 1A, the controller 300 provides a PWM control signal to the relevant Driver circuit. However, instead of charging and discharging the energy memory element, the controller 300 actually counts the time periods and provides the appropriate PWM and 5 LDR_EN signals based on these counts. For example, the controller 300 usually includes an on-time one shot circuit 302, a low side driver one shot circuit 304, a comparator 306, and a time delay Circuit 308 and a reverse OR gate 310. The time delay circuit 308 10 may be a re-trigger blanking circuit that generates a gate time single trigger circuit 302. The one-shot circuits 302 and 304 can be triggered by the falling edge of the input signal. Ideally, the gating time of the one-shot circuit 302 is proportional to the difference between the input voltage Vin of the DC / DC converter and the output target voltage Vtarget of the DC / DC converter, and Tldr is proportional to vtarget, 15 As shown in the formula (5): Ton ^ Vin-Vtarget (5) TLDR Vtarget is generally chosen to be shorter than that obtained by the formula (5). There are several ways to generate τπ / Tldr. Generally, Vtarget can be an invariant value or a variable discrete value. The delay 20 of the one-shot circuits 3202 and 304 may be an actual delay that is a multiple of the basic delay. For example, the delay To may be obtained by equations (6) and (7): (6) Ton = Tol * Μ

(7) TLDR = To2 * N 19 200421699 The figure shows an exemplary delay circuit 400, which can generate a desired delay to maintain a proper gate time for the gate time one-shot circuit:. The delay-latency circuit 400 generally includes an oscillator that generates time pulses, a counter for ten-time time pulses 404, and a digital comparator 406 that compares the count value with a multiple of five (for example, M or N). Thus, the comparator generates an output signal indicating whether the juice counter 40 has reached the necessary M or N value. Therefore, the appropriate strobe time is controlled by counting the number compared with the multiple μ * ν. Therefore, the appropriate delay can be selected by the multiples M and N. Because τ〇η is a function of 10 Vln and Vtarget, and there are several ways to control them. In the first example, Tol and To2 are equal and constant. In this way, the multiple N can be generated from a lookup table (LUT) by a digital signal that sets vtarget. The lut in this example is one-dimensional because each N value corresponds to a corresponding Vtarget value. In the same example, where τ〇ΐ and τ〇 2 15 are equal and constant, the multiple M can be generated from a lookup table (LUT) by a digital signal that sets Vtarget and a digitized Vin signal. The digitized Vin signal can be obtained by an A / D converter. In this way, the LUT that generates μ in this example is two-dimensional, because the value of μ corresponds to a corresponding Vtarget and Vin value. In another example, Tol and To2 are not equal. In this example, if τ〇2 2〇 is constant, the multiple N is the same as the method produced in the first example. Multiples M can be generated by a one-dimensional LUT with a digital signal that sets Vtarget. However, Tol is not a constant, but a function of Vin or Vin and Vtarget. Fig. 5 shows another controller 500 of the present invention used as the controller of the DC / DC converter of Fig. 1A. Many of the controller 500 shown in FIG. 5 are similar to the controller 200 shown in FIG. 2A with the same reference numerals. Since the components of FIG. 2A have been described in detail above, for the sake of brevity, the repeated description of similar components is omitted, and the differences between FIG. 2 and FIG. 5 are explained in detail. Generally, the controller 500 has an additional connection 511 to connect the output of the 5 comparator CMP4 to the input of the inverse gate G1. The inverse gate G1 now has three inputs: the first input from the comparator CMP1; the second input from the SKIP terminal; and the second input from the comparator CMP4. If any one of the inputs of the three inverting gates G1 is a digital 0 ', then the output of the inverting gate G1 is a digital one. This is especially useful in the skip 10-over mode under overcurrent conditions. In this example, the output of the comparator CMP4 may be digital 0 'and the output voltage of the DC / DC converter will drop, so that the output of the comparator CMP3 is digital 1. In this way, the switch S2 will be closed and the discharge of the energy memory element 202 will be accelerated. Due to the connection 511 between the comparator CMP4 and the inverting gate G1, as long as the output of the comparator CMP4 is digital 0, the output 15 of the inverting gate G1 is digital 1, so LDR_EN is digital 1, which causes the low-side switch Q2 to close . When all three inputs of the inverse gate G1 are high, the LDRJEN signal becomes low. At the same time, the flip-flop FF1 set by the output of the AND gate G2 starts a new PWM cycle. FIG. 6 shows a two-phase controller 600 according to the present invention. Generally, the 20 bi-phase controller 600 includes a first phase controller 602, a second phase controller 604, and a phase selection circuit 606. The phase selection circuit selects the phase controllers 602 and 604 so that one of them generates a PWM control signal at any one time. Many components of the first phase controller 602 and the second phase controller 604 are similar to those of the controller 500 shown in FIG. 21 200421699 (see also the controller 200 shown in FIG. 2A). Therefore, for the sake of brevity, repeated description of any similar components and operations is omitted here. The phase selection circuit 606 enables only one of the phase controllers 602, 604 to generate a pWM signal at any one time. Various circuit 5 configurations can be employed to implement the desired function of the phase selection circuit 606. In one embodiment, the phase selector 606 includes a flip-flop 619 and a reverse gate G7. Reverse gate G7 receives a first Pwm signal PWM1 from the first phase controller 602 and a second PWM signal pwM2 from the second phase selector 604. The output of the inverting gate G7 is then fed back to the clock terminal "CK" of the flip-flop 619. The "Q" terminal of the flip-flop 10 619 is connected to the input of the first phase controller 602 and the gate 02, and the "Q" terminal of the flip-flop 619 is connected to the second phase controller 604 and the gate G5 The inputs are connected. The inputs of the gates G2 and G5 must be digit 1 to provide a digit 1 output to set the associated flip-flop FF1 or FF2. “QB” is the inversion of “Q”, which ensures that the setting of the flip-flop 15 occurs at different times. During operation, after the first phase controller 602 generates a PWM pulse, the falling edge of the PWM pulse at the PWM1 terminal of the flip-flop 619 changes state, thereby allowing the PWM2 of the second phase controller 604 to generate a PWM pulse. When the feedback voltage VFB drops below the SLEW voltage, the PWM2 terminal of the second phase controller 604 generates a PWM pulse. The falling edge of the PWM pulse changes the state of the flip-flop 619 again. Therefore, the next PWM signal is generated by the PWM1 terminal of the first controller 602. As the flip-flop 619 changes state at the falling edge of each PWM pulse, the process continues. In Skip (SKIP) mode, since each controller 602, 604 has independent estimates of 22 200421699 LDR-EN pulses, namely LDRJEN1 and LDRJEN2, PWM pulses can be generated alternately with precision. Figure 7 shows an input voltage detection circuit 700 of the present invention that does not require a separate input pin on the controller. This reduces the total number of pins on the controller to 5 meshes. The input voltage detection circuit 700 receives an input signal from the LX pin 703. The LX pin 703 is connected to the switching node 715 (not shown in Fig. 9) of the DC / DC converter. When the high-side switch Q1 is closed and the low-side switch Q2 is open, the switching node 715 is connected to the input voltage. When the high-side switch Q1 is opened and the low-side switch Q2 is closed, the switching node 715 can also be grounded. In addition, the switch 10 node can maintain the drift state in the skip state where both Q1 and Q2 are open. Generally, the 'input voltage detection circuit 700 has a switching state determination circuit 740 and a voltage detection circuit 742. When the high-side switch Q1 is closed and the low-side switch Q2 is open, the switching node 715 is connected to the input voltage, and at this time, the switching state determination circuit 740 makes a determination. The switching state judging circuit 74o then 15 provides a judging signal to the voltage detecting circuit 742 to cause the voltage detecting circuit 742 to detect a voltage indicating the voltage at the LX pin 703. The switching state determining circuit 740 further includes an AND gate 712. When both the delayed PWM signal and the pWM signal received by the AND gate 712 are digital 1, the output of the AND 712 is also digital 1, and the switch 706 is then closed. The 20-input voltage detection circuit may further include a voltage divider composed of a pair of resistors 702 and 704 to reduce the voltage at the LX pin 703 to a low level by a certain proportion. In one embodiment, the resistor 702 may be 210 kiloohms, and the resistor 704 may be 30 kiloohms. When the switching state judging circuit 740 determines that the voltage at the switching node 715 23 20042l699 indicates that the voltage level is not input (for example, the pWM signals received by the gate 712 are all high), the switch 706 is closed. The voltage detection circuit 742 includes a transconductance amplifier 714 and a transistor Q3. The transconductance amplifier 714 receives an input signal representing an input voltage at its non-inverting input terminal, and provides a signal 5 to the control electrode of the transistor 03. Transistor Q3 then provides a signal indicating the level of the input voltage, such as I-Vin. Therefore, an input voltage detection circuit 700 is provided without a separate input pin on the controller. This reduces the total number of pins on the controller. In addition, if there is a two-phase controller on a chip similar to the controller 600 shown in FIG. 6, every 10 controllers can detect different input voltages. For example, the first controller can convert a battery voltage of 16 volts to 2.5 volts, and the second controller can convert a 5 volt input voltage to 1.5 volts. Both controllers work properly. In the circuit diagram shown in Fig. 8, a timer 802 is added between the Pwm terminal of the controller 800 and the input of the feedback gate G1. Figure 9 shows the external implementation of the timer 802 between the PWM * SKIP terminals of the controller. The timer 802 starts timing at the leading edge of a period control signal (such as a PWM signal) that can control the states of the high-side switch qi and the low-side switch Q2. This document will further detail this with reference to the timing diagram in FIG. The timer 802 guarantees the switching state of the switch at a frequency greater than the audible audio range of the human ear (ie, about 20 kHz to 25 kHz 20 Hz). This article will detail the frequency of the control cycle control signal Described. As shown in the timing chart in Figure 10, a PWM pulse is generated at time t1. Between t1 and t2, the PWM pulse is a digital one. Therefore, the high-side switch qi is closed and the low-side switch Q2 is open. In addition, the low-side enable signal LDR_EN is also a digital one during the time interval ^ to 24 200421699. Therefore, during the "on and off" state, the inductor current increases. Between times t2 and t3, the PWM signal is a digital zero and the LDR ^ EN signal is a digital one. Therefore, at this time interval, the high-side switch Q1 is open and the low-side switch Q2 is closed. Therefore, the inductor current drops during this "switch-off" state until it drops to zero at time t3. At time t3, the LDR__EN signal becomes digital zero. Because the PWM signal is also digital 0 at this time, the skip state is entered at time t3. As such, in the skipped state between times t3 and t4, both the high-side switch Q1 and the low-side switch Q2 are turned off. 10 If the output voltage measured by the feedback terminal VFB of the controller drops below the set voltage level VSET, a new PWM pulse will be generated. In addition, the operation of the timer 802 can ensure that the input voltage drops to the VSET level. For example, the timer starts counting at the leading edge of the PWM pulse, or starts a preset time interval (X seconds) at time t1. In the fifteenth embodiment shown in Fig. 8, the timer supplies a digital 1 signal to the reverse gate G1 in the time interval from time t3 to t4. After the preset time interval limit (X seconds) expires at time t4, the LDR_EN signal becomes digital one. In the embodiment shown in FIG. 8, this is because the timer signal input of the anti-gate G1 becomes a digital zero, so that the output of the anti-gate G1 20 or the LDRJEN signal becomes a digital one. In the embodiment shown in Fig. 9, the 'timer 802 controls the input state of the SKIP terminal, and thus produces the same effect as the timer of Fig. 8. That is, when the predetermined time interval limit is terminated, the 'LDR_EN signal becomes a digital one. Thus, the skip mode is inactive and the low-side switch Q2 is closed at time t2. Once the low-side switch Q2 is closed, the output voltage 25 200421699 begins to decrease because the output capacitor c is discharged to ground via the inductor's low-side switching path. When the output voltage drops below the set voltage VSET, for example at [5], a new PWM pulse is generated and the process starts again. Advantageously, the timer 802 can select a time limit to ensure the minimum frequency of the PWM pulse in the skip mode, thereby realizing the minimum switching frequency of the switching state. More advantageously, this time limit can also be selected so that the frequency of the PWM pulses is greater than the audible frequency range of the human ear. The average audible frequency range of the human ear is 20 Hz to 20 kHz. To keep the frequency at a minimum of 20 kHz, this time limit can be set to% microseconds. In order to keep the frequency at a slightly higher 25 kHz, the time limit can be set to 40 microseconds. Therefore, by properly selecting the time limit of the timer 80, the high-side switch Q1 and the low-side switch Q2 The minimum switching frequency can be maintained in a range, for example, greater than 20 kHz, which is greater than the average frequency range audible to the human ear. Although the timer described herein is used for a DC / DC converter controller, those skilled in the art will know that the timer can also be used in various other switching circuits. The switching circuit expects a minimum switching frequency to avoid people The ear can hear the switching noise. The embodiments described here are just a few of the inventions, and are for illustrative purposes only, and are not intended to limit the invention. Obviously, those skilled in the art will be able to think of many other embodiments without departing from the spirit and scope of the present invention defined by the scope of the attached patent. 26 200421699 Figure 1A shows a block diagram of a DC / DC (DC-to-DC) converter including a controller according to the present invention; Figure 1B shows the input pw M (pulse width modulation) signal and low Side enable signal, an exemplary table describing the switching states of the pair of switches in FIG. 1A; FIG. 2A shows a block diagram of an embodiment of a controller for the DC / DC converter of FIG. 1A; Fig. 2B shows a comparison curve describing the change in the charge level of the energy memory element of the controller in Fig. 2A and the corresponding change in the inductor current level in the same time interval; Fig. 1A is a block diagram of another embodiment of the controller of the DC / DC converter; Fig. 4 is a detailed block diagram of the exemplary delay circuit in Fig. 3; Fig. 5 is used as Fig. 1A DC / DC converter control FIG. 6 is a block diagram of an exemplary dual-phase controller; FIG. 7 is a circuit diagram of an input voltage detection circuit using a controller LX pin; FIG. 8 Shown is a block diagram of another embodiment of the controller with an internal timer for controlling the minimum switching frequency of the present invention; FIG. 9 shows a timer with an external timer for controlling the minimum switching frequency. A block diagram of a DC / DC converter; and FIG. 10 shows timing diagrams of the embodiments of FIGS. 8 and 9. [Representative symbol table of main components of enclosure type] 100 ... DC / DC converter 102, 200, 300 ... Controller 27 200421699 CMP1 ～ 4, COMP1 ～ 6, 306 ··· 742 " 104 ... 106, S1 to S4, 706 ... Switch 108 ... Low-pass filter C, C1 to C2, 708 ... Capacitance

Cslew ... swing capacitor L ... inductor Q1 ... high-side switch Q2 ... low-side switch R1 to R3, 702, 704 ... resistance

Vin ... input voltage

Vout ... Output voltage 120 ... Tables 122, 124 ... Column 202 ... Energy storage element 240 ... Output decision circuits 242, 619 ... Flip-flop REF ... Reference voltage value II ~ 15 ... Current source VI ... Critical voltage value V2 ... Second reference voltage comparator

Gl, G4, G7 ... Gates G2 ~ G3, G5 ~ G6, 712 ... Gate 203 ... Voltage level curve 205 ... Curve 302 ... Gate time one-shot circuit 304 ... Low-side drive one-shot circuit 308 ... time delay circuit 310 ... reverse OR gate Vtarget ... output target voltage 400 ... delay circuit 402 ... oscillator 404 ... counter 406 ... digital comparator 500, 800 ... controller 511 ... connection 600 ... Two-phase controller 602 ... First phase controller 604 ... Second phase controller 606 ... Phase selection circuit 700 ... Input voltage detection circuit 703 ... LX pin 714 ... Transconductance amplifier 740 ... Switching state determination circuit voltage Detection circuit Q3 ... transistor 802 ... timer 715 ... switch nodes t1 to t7 ... time / time 28

Claims (1)

Patent application scope: 1. A switching circuit, comprising: at least one switch; and a controller that generates a cycle control signal, the at least one switch is turned on and off in response to the cycle control signal at each of the cycle control signals. The state changes at the beginning of the cycle, where the frequency of the cycle control signal has a preset minimum frequency value that is greater than the audible frequency range of the human ear. 2. The circuit according to item 1 of the scope of patent application, wherein the preset minimum frequency value is about 20 kHz. 10 3. The circuit according to item 1 of the scope of patent application, wherein the preset minimum frequency value is about 25 kHz. 4. The circuit according to item 1 of the scope of patent application, wherein the period control signal includes a pulse width modulation signal. 5. The circuit as described in item 1 of the scope of patent application, wherein the controller includes-15 timers, which count a preset time interval based on the start of the first cycle of the cycle control signal, if the cycle The control signal has not changed state since the first cycle, and the controller starts the second cycle of the cycle control signal in response to the end of the preset time interval. 6. The circuit according to item 5 of the scope of patent application, wherein the preset time interval 20 is about 40 microseconds, and the preset minimum frequency is about 25 kHz. 7. The circuit according to item 5 of the scope of patent application, wherein the preset time interval is about 50 microseconds, and the preset minimum frequency is about 20 kHz. 8. The circuit according to item 1 of the scope of patent application, wherein the timer is connected between an output terminal of the controller for the control signal and the -round 29 200421699 terminal of the controller. 9. The circuit according to item 1 of the scope of patent application, wherein the controller is a controller of a DC / DC converter, wherein the at least one switch includes a high-side switch and a low-side switch 'and the cycle control signal Includes a pulse 5 pulse width modulation signal. 10 · —A switching circuit including: at least one switch; and a controller that controls a state of the at least one switch through a period control signal, the at least one switch responding to the period control signal and The state changes at the beginning of each cycle; the controller has a skip mode, where the controller keeps the at least one switch in the off state; the controller responds to a timer, which is based on the The start of a cycle counts a preset time interval. If the cycle signal has not changed state from the first cycle, the controller responds to the end of the preset time interval and starts the second cycle of the cycle control signal. The preset time interval is set to obtain a preset minimum frequency value of the periodic control signal that is greater than the audible frequency range of the human ear. 11. The circuit as described in item 忉 of the patent application range, wherein the period control signal includes a pulse width modulation signal. 20 12. The circuit according to item 10 of the scope of patent application, wherein the preset time interval is about 40 microseconds, and the preset minimum frequency is about 25 kHz. 13. The circuit according to item 10 of the scope of patent application, wherein the preset time interval is about 50 microseconds, and the preset minimum frequency is about 20 kHz. 14. The circuit as described in item 10 of the scope of patent application, the skip mode becomes invalid based on the termination of the preset time interval of 30 200421699. 15. The circuit of claim 4, wherein the timer is connected between an output terminal of the controller for the cycle control signal and an input terminal of the controller for the skip mode. 5 16. The circuit according to item 10 of the scope of patent application, wherein the timer is an internal component of the controller. 17. A method for keeping the minimum frequency of the switch state switching greater than the audible frequency of the human ear, the method comprising: at the beginning of the first state switching at which the switch changes to the first state, starting 10 for a preset time interval Monitor the state of the switch; and if the switch is still in the first state, change the state of the switch in response to the end of a preset time interval, thereby keeping the minimum frequency of the state switching of the switch greater than the Human ear audible frequency. 15 18. The method according to item 17 of the scope of patent application, wherein the preset time interval is about 40 microseconds, and the preset minimum frequency is about 25 kHz. 19. The method according to item 17 of the scope of patent application, wherein the preset time interval is about 50 microseconds, and the preset minimum frequency is about 20 kHz. 20. The method according to item 17 of the scope of patent application, wherein the period control signal 20 includes a pulse width modulation signal. 21. A DC / DC converter for converting an input voltage into an output voltage, the DC / DC converter comprising: a controller based on a first signal representing the input voltage and a first signal representing the output voltage The difference between the second digits provides a PWM signal in the first state within the first time 31 200421699 interval; a driver circuit that receives at least the PWM signal and generates a switch drive signal; includes a high-side switch and a low A pair of switches of the side switch, the switch 5 is driven to a switch closed state in response to the switch driving signal, wherein when the PWM signal is in the first state, the high-side switch is closed and the low-side switch is opened; An inductor connected to an output of the switch pair, wherein a current level on the inductor increases in a closed state of the switch; and 10 a logic circuit providing a low-side enable signal having an enable and an inactive state, Wherein, when the low-side enable signal is in the enable state, the PWM signal controls the low-side switch; the logic circuit receives a A comparison signal from an overcurrent comparator that provides the 15 comparison signal based on a comparison of the current level flowing through the inductor with a threshold current value, wherein if the current level flowing through the inductor When the value is greater than the threshold current, the logic circuit further provides the low-side enable signal in the enable state. 22. The DC / DC converter according to claim 21, wherein the logic circuit includes a reverse AND gate. 20 23. A method for detecting an input voltage level of a DC / DC converter by using an existing pin connected to a switching node of the DC / DC converter, the method comprising: determining an input voltage source and the switching node; The state of a connected high-side switch; 32 200421699 determines the state of a low-side switch coupled between the ground point and the switching node; and detects the input voltage when the high-side switch is closed and the low-side switch is open . 5 24. The method according to item 23 of the scope of patent application, wherein the determining steps are performed based on a state of a pulse width modulation signal controlling the high-side and low-side switches. 25. A controller for a DC / DC converter, the controller comprising: an input terminal 10 connected to a switching node of the DC / DC converter, when a high-side switch is closed and a low-side switch is opened When the switching node of the DC / DC converter is connected to an input voltage; and an input voltage detection circuit connected to the input pin terminal, the input voltage detection circuit includes: a switching state determination circuit for sensing When the switching node 15 is connected to the input voltage based on the state of the high-side switch and the low-side switch, and provides a determination signal in response to the sensing result; and a voltage detection circuit, the voltage detection circuit responds to The determination signal of the switching node connected to the input voltage is detected to detect a voltage level indicating the input voltage. 20 26. The controller according to item 25 of the scope of patent application, wherein the switching state determination circuit generates the determination signal in response to a state of a pulse width modulation signal controlling the state of the high-side switch and the low-side switch. 27. A two-phase DC / DC controller, comprising: a first phase controller that provides a first PWM signal, the 33 200421699 a PWM signal based on an input voltage representing an input voltage of a DC / DC converter The difference between the first signal and a second signal representing an output voltage of the DC / DC converter is provided; a second phase controller providing a second PWM signal, the fifth second PWM signal is based on the A difference between the first signal of the input voltage of the DC / DC converter and the second signal representing the output voltage of the DC / DC converter; and a selection of the first phase controller and the second Phase selection circuit of the phase controller. 10 28. A controller that provides a control signal that controls the state of at least one switch, the controller comprising: a timer that counts a preset time interval after the at least one switch changes state to a first state; if The at least one switch has been in the first state since the start of the preset time interval, the controller will return to the end of the time interval to switch the state of the at least one switch, where the preset time interval setting enables The minimum frequency of this state switch is greater than the audible frequency of a human ear. 29. The controller of claim 28, wherein the preset time interval is about 40 microseconds, and the preset minimum frequency is about 25 kHz. 20 30. The controller according to item 28 of the scope of patent application, wherein the preset time interval is about 50 microseconds, and the preset minimum frequency is about 20 kHz. 34