TW200414506A - CMOS device and its manufacturing method - Google Patents

Abstract

The present invention provides a CMOS device. Its structure includes a gate electrode configured on a substrate; source/drain configured in the substrate at two sides of the gate electrode; a stress buffer liner layer conformably configured on two sides of the gate electrode and partial portion extended to the surface of the substrate; and a stress layer configured on the gate electrode, the stress buffer liner layer and source/drain for contacting the stress buffer liner layer, so as to increase the stress of the channel in the substrate below the gate electrode.

Description

200414506 V. Description of the invention (i) [Technical field to which the invention belongs] The present invention relates to a CMOS device and a method for manufacturing the same, and more particularly, to a method using local mechanical stress control (10 cai, 疋 mechainca, stress control 'referred to as LMC) ) Method and structure to increase the effectiveness of the CD element. [Previous Technology] In the current semiconductor devices, Si buik is used as the substrate, and high-capacity operation and low volume are achieved by reducing the device size. However, the reduction in component size is now approaching the physical limit: and the cost limit. Therefore, it is necessary to develop other technologies different from the downsizing method to achieve high-speed operation and low power consumption. Therefore, some people have proposed to use the stress control method in the channel region of the transistor to overcome the limit of the reduction of the element. This method is to increase the mobility of electrons and holes by changing the lattice spacing of silicon. A common method is to use a channel layer placed on a Si-Ge layer (tensile-strained Si layer "NM0S transistor, and a lithography layer using compressive tension ... u⑽Presslve-strained Si_Ge layer) (at ') as the channel layer of the PM0S transistor. By using a Si: Ge layer with a tensile force of == compressive tension as the channel layer of the M0S transistor: Fenton II and electron and hole mobility At the same time, the purpose of high-speed operation is achieved at the same time. However, this technology has some problems. When the tensile tension is formed at the same time,

〇5〇3-8980TW (Nl); TSMC2002-0937; Amy.ptd Page 6 200414506 V. Description of the invention (2) When the S i layer (n channel layer) and the compressive tension s CMOS channel layer, the process will change It is reported that & P transport layer) as the NMOS channel layer and the PMOS channel layer are phase-matched: and, when the Si-Ge layer is formed by selective heat treatment, it will occur ,,, '. Moreover, when segregation of Ge occurs by high, = (dlslocatlon) or sexual deterioration. In addition, the breakdown voltage of the gate is particularly affected by the recent use of stress as a layer of Shi Xi to influence the transistor's behavior ::: = layer: nitrided mechanical stress control. By adding additional; Is the mobility of the local transistor; by reducing the external application, the mobility of the PM0s NM0S transistor can be improved. Although the shrinkage stress can be improved, although the above-mentioned method using nitrided layer production + virtual method is more effective than using S i-Ge buffer The method of the layer should be a single force to improve the transistor / efficiency. However, the method can improve the effect. [Summary of the Invention] In view of this, the present invention provides a technology that can utilize local mechanical stress control to further Structure and method for improving transistor performance. Therefore, the present invention provides a CMOS device including a gate electrode on a substrate and a source / drain electrode in a substrate on both sides of the gate electrode. The buffer liner is compliantly arranged on both sides of the gate electrode and partially extends to the surface of the substrate, and a stress layer is provided on the gate electrode, the stress buffer liner, and the source / drain electrode, and is connected to the stress buffer liner. Contact to increase the stress in the channel region in the substrate below the gate electrode.

V. Description of the invention (3) Where = If the above stress layer has tensile stress, the transistor composed of the free electrode and source / drain electrode under the stress layer is a pM0s transistor and the above stress layer A transistor with compressive stress and a gate electrode and a source / drain covered under the stress layer is a pMOS transistor. The present invention also provides a method for manufacturing a CMOS device. The method is as follows. First, a gate electrode is formed in the active region of the substrate, and a lightly doped region is formed in the active region in the two: j substrate. Then, a stress buffer liner is formed on both sides of the gate electrode and partially extends to the base: 'and a core: wall is formed on the stress buffer layer on both sides of the gate electrode: The gate electrode is not on both sides of the gate electrode The main: region formation covered by the spacer wall is a heavily doped region, wherein the above-mentioned lightly doped region and the heavily doped region constitute a source / drain region. After the source / drain region is formed, =-walls are inferior to the gate electrode, stress buffer liner, and source / non-electrode ^ except for one of the underlying substrates = layer contact, which is used to improve the inter-electrode where Before removing the barrier ribs, a chemical process is also performed to form the source / non-electrode surface—metal fragments, quasi-lithium. In addition, one can also be performed after removing the barrier ribs. In the chemical process, a metal stone is formed on the source / drain surface: quasi-stone. The thickness of the above-mentioned stress buffer liner is less than 500 angstroms. The material of the stress layer can be silicon nitride (si Ν), — 〇〇〇Ν), or nitride nitride (SlN) and oxynitride (Si〇n = 2 Shixi 200414506) Description of the invention (4)

), Fast: ϊ ί: Ϊ; f enhanced chemical vapor deposition ☆ (PECVD

). Or low-pressure chemical vapor deposition (LPCVD) forms an inner layer on the stress layer of the above-mentioned CMOS device: Method: Second step includes the following steps: engraving in the inner dielectric layer-the two i ^ layers are ㈣stop layers 'The stress layer in the mouth. The contact 1 ^ opening' and the removal of the contact window are opened to make the present invention more specific. The purpose of a preferred embodiment is as follows: the characteristics and advantages can be more clearly understood. Below: & The attached drawings are explained in detail as in [Embodiment] According to the results of the study, + compressive stress in the channel region is shown: When the transistor is a f-ft transistor, the rate is increased. For N-channel transistors 电When the stress is applied, the channel migration of the M-channel plus hole also increases the channel area: when the compressive stress transfer rate of the low channel area is reduced. In order to increase the load: the extension stress day: 'the electronic load will be added The migration of the species can be effectively discriminated. The present invention provides a manufacturing method. The method of adding stress in the channel region to the structure of the element and the structure thereof. The present invention provides a C M 0 S element Structure, as shown in Figure 1d.

0503-8980TW (Nl); TSMC2002-0937; Amy.ptd Page 9 200414506 Description of the invention (5) The electrode 104 is provided on the substrate 100, and the source / drain S / D = is also at the gate electrode 1〇 Bases on both sides of 100. Among them, the pole electrode can be polycrystalline silicon, metal, silicon germanium, or polycrystalline silicon containing germanium. In addition, an electrode dielectric layer 1 U Z ′ is provided between the idler electrode 104 and the substrate 100, and the material may be silicon oxide. The lateral stress buffer liner 10 is compliantly disposed on both the gate electrodes 104 and partially extends to the surface of the substrate 100. The thickness of the stress buffer liner 110 is controlled to less than 500 angstroms, and the material can be silicon oxide. Next, a stress layer 118 is provided on the gate electrode 104, the stress buffer liner 110 and the source and electrode S / D, and is in contact with the gate electrode 104 and the stress buffer liner 110 to improve the gate electrode. The stress of the channel region 1〃14〃 in the substrate 100 below the 104. The material of the stress layer 8 is silicon nitride ($ 丨 n), silicon oxynitride (SiON), or a stack of silicon nitride (SiN) and silicon oxynitride (SiON). If the stress layer 118 has tensile stress, the transistor composed of the gate electrode 104 and the source / drain S / D covering the stress layer 118 is a pMOS transistor and a NMOS transistor. The stress layer 118 on the right has compressive stress, and the transistor composed of the interlayer electrode 104 and the source / non-polar S / D layer under the stress layer 118 is a pM0s transistor. In addition, a metal silicide layer 1 1 6 is provided between the stress layer 1 18 and the source / drain s / ο to reduce the sheet resistance of the source / drain s / ρ. Normally, a metal oxide layer 116 of the same material is also provided between the stress layer 118 and the gate electrode 104.

0503-8980TW (Nl); TSMC2002-0937; Amy.ptd

200414506

Manufacturing Method FIGS. 1A to 1E are schematic views showing a method of manufacturing a ytterbium element. First, according to FIG. 1A, a substrate 100 is provided. The substrate 100 has a main region AA. The active region AA is formed by an isolation element structure formed in the substrate 100. For example, a shallow trench isolation element STI , And defined. Then, a transistor is formed in the active region. The transistor can be a PMOS transistor and a NMOS crystal. As shown in the figure, a gate dielectric, a layer 102 and a gate electrode 104 are formed on a substrate i0q. The material of the gate dielectric layer ι〇2 can be equal to that of the silicon gate electrode 104. The material can be polycrystalline silicon, metal, silicon germanium or digermanium. The formation and method of the gate dielectric layer 〇2 and the gate electrode 104 are, for example, sequentially depositing a dielectric layer and a conductive layer on the substrate 100, and forming a pattern on the conductive layer. The mask layer (not shown), and then the patterned mask layer is used as a mask, and the conductive layer and the dielectric layer are sequentially non-directionally etched to form a gate dielectric layer as shown in the figure. 〇2 and the gate electrode 104, and then remove the patterned mask layer. After that, the active region AA in the substrate on both sides of the gate electrode 104 is formed with a c-doped region 106. The formation method is to implant the dopant by the ion implantation method without gate. The electrode 104 and the shallow trench isolation element ST are in a covered substrate. First, referring to FIG. 1B, a stress buffer liner 108 is formed compliantly on both sides of the gate electrode 104 and partially extends to the surface of the substrate 100. The thickness of the stress buffer liner 108 described above is less than 500 angstroms, and its material can be oxidized ^

200414506 V. Description of the invention (7) Shi Xi ◦ Stress buffer transfer It can also be used to keep the tank Γ = 8. In addition to its role as a stress buffer, it can be used as a domain. After :: the sidewall of the electrode 104 and the partition wall 11 near the channel region U4. The material of the stacked Λ gap wall 110 formed on the stress buffer layer on both sides of the upper electrode 1 () 4 is a nitrogen cutting or oxygen cutting / forming method, such as 9 ′ stress buffer lining 1 08 and The exposed surface of the shape layer 102 of the partition wall 110 is in the order of the substrate 10, the gate electrode is called an insulating layer of inter-electrode dielectric; the second layer is formed on the back of the iron-a thin insulating layer and another-thicker 1 10 and the force π: ·, using non-temporal etching 'to form-the gap wall 丄 丄 υ Han Han heart knife buffer liner 1 0 8. 110 cover # * 者 之 '/ Z electrode electrode 04 on both sides are not free electrode electrode 104 and the spacer ^ the active region AA in the substrate 100 forms a heavily doped region 112, the i-shaped gap m and the method will change The substrate is implanted in the substrate 100 which is not covered by the idler electrode 104 and the trench isolation element STI. Of which light

Qn 6 and the heavily doped region 1 12 form the source / drain region / S / D of the transistor. Following Ming Lingzhi, Fig. 1c, the wet etching or dry etching is used to remove the substrate 11 to expose the stress. Buffer liner 108. Before removing the spacer 丨 丨 0, it also includes performing an auto-alignment silicide process to form a metal silicide layer 11 6 on the surface of the source / drain S / D or moving After removing the spacer 1 10, an automatic alignment silicide is performed, so that a metal oxide layer 11 6 ′ is formed on the surface of the source / inverter S / D as shown in FIG. 1 c. In the above-mentioned automatic alignment silicide process, if the material of the interfacial electrode 104 is polycrystalline silicon, silicon germanium, or germanium-containing polycrystalline stone, a metal silicide layer 1 16 will also be formed on the surface, as shown in the figure. As shown.

Page 12

V. Description of the invention (8) Next, please refer to 图 1 D Μ quasi-silicide, t4, remove the spacer 11 and complete the automatic source / drain S / = bu ^ i gate electrode 104 The stress buffering layer 108 and the force buffering layer are connected to each other: the second layer is the layer of the substrate below the stress south gate electrode 104 in the channel region iu of _ ^ 100, and the layer 118 may be repeatedly shrunk. The stress layer or a laminate with a tensile stress of 300 ~ fossil evening (S10N) has a thickness of about 60%, and its formation method can be plasma enhanced: PECVD), Rapid thermal process chemical vapor deposition Xingyou +, atomic-level chemical vapor deposition (ALCVD), low pressure = Γ (LPCVD). By controlling the formation conditions, the stress of the film layer can be adjusted. According to the research, the factors that can control the stress, the pressure or the proportion of the process gas. If the plasma deposition method is used, the factors that can control the stress include plasma Electricity (Plasma Power). Stomach—The plasma-enhanced chemical vapor deposition method is used to form a stress layer 1 丨 8 made of silicon nitride and a good stress, as an example. The required temperature is approximately between 300 ° and 50 ° / The required pressure between C and C is roughly between 〇 Tor (t〇rr) and i · 5 Tor. 'The required plasma power is roughly between 100,000 watts (w) and 2,000. Between 0 watts, the process gas can be NH3: SiH4, the ratio is approximately 4 ~ 10. Taking the rapid thermal process chemical vapor deposition method to form silicon nitride and tensile stress as an example, the required temperature is approximately between 300t and 800t. The required pressure is approximately between Between 150 Torr and 300 Torr, the process gas can be N H3: S i H4, the ratio is approximately 50 ~ 4 0 0; or the process gas

Page 13 200414506

1〜1。 Can be lice silane (dlchl〇r〇silane abbreviated DCS): NH3, the ratio is approximately 0. 1 ~ 1. … If the stress layer 118 has tensile stress, the transistor consisting of the gate electrode 104 and the source / drain S / D under the stress layer 118 may be a pM0s transistor and a NM0S solar cell . In this case, the compressive stress of the channel region 114 of the CMOS device of the present invention will be reduced compared to the conventional structure without the spacer wall removed, thereby increasing the electron and hole carriers in the region. The mobility in the channel region is 0. If the stress layer 118 has compressive stress, the transistor system consisting of the gate electrode 104 and source / drain s / D covering the stress layer 118 is pM0s. In this case, compared with the conventional structure without removing the spacer, the compressive stress of the channel region 14 of the CM-0S element of the present invention will increase by about 93 ~ 128 MPa, thereby increasing the hole carriers in the channel. District mobility. In addition, the above-mentioned stress layer 1 1 8 can also be used as an etch stop layer in a subsequent contact window process. Then, subsequent processes are performed, such as an interconnect process. As shown in FIG. 1E, an inner dielectric layer is formed on the stress layer 118. The material is, for example, silicon oxide, borophosphosilicate glass (BPSG), or other similar properties. After the layer 120 is planarized, a contact window opening 122 is formed in the inner dielectric layer 120 and the stress layer 18 by a lithography etching process. In the step of engraving the contact window, the above-mentioned stress layer 丨 丨 8 is used as an etching stop layer. After etching to expose the stress layer in the contact window opening 122, the engraving conditions are changed, and the contact is removed. The stress layer 8 in the window opening 22 is exposed until the component area to be connected is exposed. j

200414506 V. Description of the invention (ίο) In summary, by using the structure and method provided by the present invention, the mechanical stress can be concentrated in the channel area, thereby forming a transistor having the characteristics of high-speed operation and low energy loss. In the process of manufacturing the transistor, before depositing the stress layer, by adding a process of removing the spacer, the stress of the deposited stress layer can be effectively concentrated in the channel region of the transistor. Therefore, the method can be applied to any process for improving the performance of a transistor by controlling local mechanical stress. In addition, as for the manufacturing of the above-mentioned stress layer, according to the different needs of the P channel and the N channel, a stress layer having compressive stress and tensile stress that meets their needs can be manufactured separately. Therefore, the method for forming the stress layer is not limited to the method described above, and other processes that can improve the performance of the transistor through local mechanical stress control can be applied to the present invention. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

0503-8980TW (N1); TSMC2002-0937; Amy.ptd Page 15 200414506 Brief description of the drawings [Simplified description of the drawings] Figures 1A to 1E show a CMOS device according to an embodiment of the present invention Schematic illustration of the manufacturing method. [Symbol description] Active area · AA shallow trench isolation element: ST I source / drain: S / D substrate: 1 0 0 gate dielectric layer: 1 0 2 gate electrode: 1 0 4 lightly doped region : 1 0 6 Stress buffer liner: 1 0 8 ′ Spacer: 11 0 Heavyly doped region: 11 2 Channel region: 1 14 Metal oxide layer: 1 1 6 Stress layer: 11 8 Inner dielectric layer: 120 Contact window opening: 1 2 2

0503-8980TW (Nl); TSMC2002-0937; Amy.ptd page 16

Claims (1)

200414506 VI. Application Patent Scope 1. A CMOS device comprising: a substrate and a gate electrode provided on the substrate; a source / drain electrode provided in the substrate on both sides of the gate electrode; a stress buffer A liner layer compliantly disposed on both sides of the gate electrode and partially extending to the surface of the substrate; and a stress layer disposed on the gate electrode, the stress buffer liner, and the source / drain electrode, and The stress buffer liner contacts to increase the stress in a channel region in the substrate below the gate electrode. 2. The CMOS device according to item 1 of the patent application scope, wherein the thickness of the stress buffer layer is less than 500 angstroms. 3. The CMOS device according to item 1 of the scope of patent application, wherein the material of the stress buffer liner is oxidized stone. 4. The C M 0 S element described in item 1 of the scope of the patent application, wherein the material of the stress layer is silicon nitride (Si n). 5. The CMOS device according to item 1 of the scope of patent application, wherein the material of the stress layer is silicon oxynitride (Si 0N). 6. The C M 0 S element as described in item 1 of the scope of the patent application, wherein the material of the stress layer is a stack of silicon nitride (S i Ν) and silicon oxynitride (S i 0N) 0503-8980TW (Nl); TSMC2002-0937; Amy.ptd Page 17 200414506 VI. Application for patent scope layer 0 '. As described in the first patent application scope of the CMOS device, the Yuli layer has a stretch The stresses cover the gate electrode and the source electrode below the stress layer, and the transistors formed by the electrodes are PM0S transistors and NMOS transistors. Person 8. The CMOS device described in item 1 of the scope of the patent application, wherein the stress layer has compressive stress, and the transistor formed by the gate electrode and the source / non-electrode under the stress layer is a PM0S transistor. . 9. As described in item 1 of the scope of patent application, the material of the CMOS device, wherein the material of the gate electrode is selected from the group consisting of free polycrystalline stone, metal, germanium and germanium-containing polycrystalline silicon. 10. As described in item 1 of the scope of patent application (CM0S device, which further includes a metal silicide layer, disposed between the stress layer and the source / drain electrode, and between the stress layer and the gate electrode 1 1 · A method of manufacturing a CMOS device 'includes: · Providing a substrate having an active region' to form a gate electrode in the active region; forming the active region in the substrate on both sides of the gate electrode A lightly doped region conformably forms a stress buffer liner on both sides and portions of the gate electrode 0503-8980TW (Nl); TSMC2002-0937; Amy.ptd Page 18 200414506 6. The scope of the patent application extends to the surface of the substrate to form a gap on the stress buffer layer on both sides of the gate electrode; The active region on both sides of the electrode that is not covered by the gate electrode and the gap wall forms a heavily doped region, wherein the lightly doped region and the edge / cage mixed region form a source / drain Area; removing the spacer; and ^ overlaying a stress layer on the delta gate electrode, the stress buffer liner, and the source / drain electrode, and contacting the stress buffer liner to improve the gate pen Stress in one of the channel regions below the substrate. 12. The method for manufacturing a CMOS device according to item 11 of the scope of patent application, wherein the thickness of the stress buffer liner is less than 500 angstroms. 13. The method for manufacturing a C M 0 S element according to item 11 of the scope of the patent application, wherein the material of the stress buffer liner is silicon oxide. 14. The method for manufacturing a CMOS device according to item 11 of the scope of the patent application, wherein the material of the stress layer is selected from free silicon nitride (SiN), silicon oxynitride (SiON), and silicon nitride (SiN) And silicon oxynitride (SiON). 15. The method for manufacturing a CMOS device according to item 14 of the scope of the patent application, wherein the method for forming the stress layer is plasma enhanced chemical vapor deposition (PECVD). 0503-8980T \ V (Nl); TSMC2002-0937: Amy.ptd Page 19 200414506 Patent Application Law Method 16. If the patent application is applied, where the stress layer is formed (RTCVD). The method for manufacturing the CMOS device described in item 14 is rapid thermal process chemical vapor deposition. 17 · As in the patent application method, the stress layer (ALCVD). The method for manufacturing the CMOS device described in the item 14 of the scope is the atomic-level chemical vapor deposition method 1 § & From the "X main method, t ·: f Please manufacture the CMOS device described in the scope of the patent in item 14" The formation method of the square / τ p ^ ^ force layer is a low pressure chemical vapor deposition (LPCVD) method. Method, j ·, the manufacture of the CMOS device described in item No. 11 of the Zhongqing patent scope ^ The stress layer in the 5H has tensile stress, and covers the μ-mm I-pole and the source electrode under the stress layer. /; And the transistor is composed of PM0S transistor and NM0S transistor. · According to the manufacturer of the CMOS device described in item 11 of the scope of the patent application, the stress layer in ii has compressive stress, and the electric voltage formed by the t-pole and the source / drain electrode under the stress layer is covered The crystal was a pMos transistor. 21. The method for manufacturing c Μ 0 S element as described in item 11 of the patent scope of Shenqing ’, wherein the material of the gate electrode is free polycrystalline silicon, metal, silicon germanium Sixth, apply for patents ^ ------ and the group consisting of germanium-containing Xi Yue Xi crystal silicon. 22. Method, of which 23. Method, of which 24. Method, wherein the material of the sigma barrier wall made by the CMOS device described in item 11 of the scope of patent application is silicon nitride. The method for manufacturing the CMOS device described in item 11 of the scope of patent application is to remove the spacer by wet etching. tThe method for manufacturing the CMOS device described in item 11 of the scope of patent application The method of removing the spacer is dry etching. The 2 5 long method, in which U: the manufacturing process of the CMOS device described in item 11 of the patent scope, before removing the spacer, it also includes an automatic alignment silicon " Wang, for the source electrode A metal silicide is formed on the surface of the / drain. 2 6 method, in progress: μ CMOS element manufacturing process as described in the 11th patent scope except for the gap wall 1 includes performing-automatic alignment Shi Xixin the source / non-polar surface formation-metal stone Xi compound. The method is described as follows: = The manufacturer of the CMOS device described in Item 11 of the Patent Law includes the following steps: forming an inner layer dielectric layer on the stress layer; using the stress layer as the money stop layer, A contact window opening; and etching out in the inner dielectric layer 200414506