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TW200401414A - Package for a non-volatile memory device including integrated passive devices and method for making the same - Google Patents

Package for a non-volatile memory device including integrated passive devices and method for making the same Download PDF

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Publication number
TW200401414A
TW200401414A TW091136677A TW91136677A TW200401414A TW 200401414 A TW200401414 A TW 200401414A TW 091136677 A TW091136677 A TW 091136677A TW 91136677 A TW91136677 A TW 91136677A TW 200401414 A TW200401414 A TW 200401414A
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Taiwan
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substrate
volatile memory
passive component
patent application
item
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TW091136677A
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English (en)
Inventor
Eleanor P Rabadam
Michael J Walk
Milan Keser
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Intel Corp
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Publication of TW200401414A publication Critical patent/TW200401414A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

200401414 玖、發明說明： 【發明所屬之技術領域】 本發明係關於記憶體裝置之封裝。 【先前技術】 諸如非揮發性記憶體裝置等 /4, Λ L ^私裝置，伍往涉及到巷
式化/抹除電壓電位的使用，A 雷厭，、係通吊不同於正常作業中的 ik。因此’蔹等記憶體 ， 1』此係連接至頟外電蹲 凰：：生並調節用於對記憶體裝置進行程式化或抹除之電 二：。然而：：額外電路可能增加與該等記憶體裝置相 ^疋、本。m等電路和組件亦可能影#記憶體裝置之可 =性1其涉及到更多組件，此等組件之失效可能導致記 fe體操作的失敗故障。 因此，需要更好的方法以封裝記憶體裝置。 【發明内容】 簡言’根據本發明一項具體實施例，一種記憶體裝置之 対裝包含黏著於-基板上之—具有〜記憶體陣列之積體電 路晶粒及至少.__被重Λ紐株。jt- & '微力件在替代性具體實施例中，可將 一焊球陣列黏著於該被動組件周園。 【實施方式】 在以下的詳細說明中’所提出的許多特定細節係為了提 供對本發明全盤的瞭解。然而，熟悉技術人士將可瞭解， 本發明可不使用這些特定細節來實施。在其他情況下，為 避免混淆本發明，將不再詳細說明已熟知的方法、程序、 組件及電路。 200401414 虚「連接。日θ及令靖專利範圚中’可使用術語「I馬合」 彼此的二及其衍生術語a應明瞭，這些術語並非作為
來指示“二體中’可使用「連接」 。「耦合二貝&或電氣互相接觸的兩個或兩個以上元件 元件。：」可，表：直接以實體或電氣接觸的兩個或兩個以上 '、、、 耦合」也可表示並非直接以實體戋電A 接觸的兩個或兩個以上元件，但仍然互相合作或::㈣ 圖1所不為依據本發明之—項具體#施例⑽。—球 列（BGA)封裝26可包含—基㈣，該隸可制複數個焊球 :電⑼合至外部電路。應明瞭，本發明之涵蓋範園並不 侷限於BGA封t ’亦可選擇其他封裝。 封裝26可包括一積體電路晶粒”，其係(例如)利用 黏、了 ^疋在基板28上。該黏結劑可包含—非傳導性材料 ，：在基板28與積體電路晶粒29之間提供電性絕緣。或者 ，该黏結劑可包含一 1J y,., 至基一下方焊:3::嶋，嶋積體電路- 積體電路晶粒29可包含—非揮發性記憶體陣列，例如一 可抹除可程式化唯讀記憶體（E_M)、電子可抹除 化t讀!!憶體（EEPROM)、單位元快閃記憶體、多位元^ c fe體等，但本發明之涵蓋範圍並不侷限於此。 在-項具體實施例中，—完整之電壓調節器電路或—部 分可在封裝26下方形成。該電壓調節器可用來提供用於 體電路晶粒29作業期間之電壓電位。例如，該電壓調節二 可提供電壓電位以程式化和/或抹除積體電路晶粒29中㈣ 200401414 揮m己Γ，但本發明之涵蓋範圍並不侷限於此。 被動组件60、61可黏著於積體電路晶粒、
上，但本發明之涵蓋範圍並不偈限於此。例如=基板2丨 、6〗可包含諸如電容器' 電感器、電阻::件6C 電栗電路、電壓調節器電路相關聯的積體组件；:= 此等例子並非要窮盡所有，因若兩要^ ' 列舉 動或被動裝置納人封裝26中。'化任意數量的主 被動組件6 0、61 W法丨1 ΐίΐ也ί 其板28之下、/ 黏結劑18以黏著或固定於 土板k下万表面。黏結劑18可包含—非、 =-核乳化物，以在被動组件叫61與基板 = 性絕緣。但本發明之涵蓋範圍並不偈限於此，因 具體實施財，黏結劑18可包含傳導性材料（如烊锡= 將：動組件6。、61電氣搞合至積體電路晶粒29。·二二 乏厚度可按需要而改變，但可 、—1]層 之整體厚度。 …°，1-未以縮減封裝26 可在積體電路晶粒29與基板28之間形成線焊聯、^ 〇nds)2〇，^^ 叫基板28之間形成線烊聯結2〇。線坪聯結2〇可提供务性 連接至積體電路晶粒29、基板28和/或其下方任球Μ。 可將積體電路晶粒29納入—非傳導性密封材料3〇中 —鑄模陣列封裝㈣lde“rraypackage，MAp)，但本發明之 涵盍範圍並不侷限於此。 料圖1中僅顯示少數被動組件’但應明瞭在其他替代性 具體貫施例中’可將單—或所有與積體電路晶粒29之作業 200401414 相關的被動組件黏著於基板28上。此外應明瞭，本發明之 涵盍範圍並不僅侷限於非揮發性記憶體裝置之應用，或僅 侷限於一般記憶體裝置之應用。 如圖2所示，被動组件60、61可黏著在焊球34之陣列中央 3 3仁本喬明之涵盖範圍並不僅侷限於此。此種佈置可滿 足與現存非PSIP封裝之覆蓋區相容的需要，並節省新的測 試硬體和印刷電路板的成本。然而在其他替代性具體實施 例中，被動組件60、61可置於焊球34陣列之外。此外，被 動组件60、61可置於基板28下方表面上任何位置，以顧及 諸如散熱、元件引起的電氣雜訊/干擾等因素。 而且，可按需要選擇被動組件和/或焊球34的大小，使得 被動组件60、61之高度小於焊球34之高度，以使被動組件 ㈣、61不會對將封裝26黏著於其他元件或板上產生影響， 但本發明之涵蓋範圍並不僅偈限於此。在本發明之其他具 體實施例中，例如圖3所示者，被動組件6〇、61之高度可大 於焊球34之高度（即被動组件6〇、61由基板28向外延伸得更 遠)。此-高度可藉由在被動组件6〇所在位置之印刷電路板 處開-凹洞遍或其他凹陷來補償，使得被動組終“不 會影響封裝26之使用和黏著。 圖4顯示係依據本發明之另一項具體實施例。為進一步減 小被動組件60、61可能影封裝％之風險，最好 將被動組件6 0、6 1黏菩*其扣0 ^、 铂耆在基板28:—凹洞4〇〇内。凹洞4〇〇 可以多種方式形成。例如，凹洞4⑽可藉由對基板以進行機 械加工、模壓或触刻而獲得’但本發明之涵蓋範圍並不侷 200401414 限於此。或者，基板28可藉由組合多層基板形成，里且 不同厚度。 八 综上所述，圖示具體實施例表示封裝中的一電源供應 (聰佈置，其中可將電路或组件的至少某些與積體電路晶 担29K乍業相目的部分黏著於基板28)。封裝％基本上可保 持相應之非·封裝（如為記憶體裝置、被動組件、電壓調 節器分別封裝）之形狀因數不辔， 妖4又以使封裝26可與用於相應. 非PSIP封裝（其執行本質上相 u刀此）《板上所分配的空間 相適應。因此’即可實現—較低製造成本，但同時基本上 能保持相應非驗封裝（其較昂貴）之形式不 裝26。 乐承对 本發明的某趣特徵雖p A 1 +二、 *一行攸雖已在此處說明並描述，熟悉技術人 士應知許多修正、取代、改 又及问寺者。因此應明白，隨 附申請專利範圍預定涵蓋屬 柯々、令知明真貫精神内的所有修 正及改變。 I巧u 【圖式簡單說明】 關於本發明的主旨已在太 "己在本忒明書的結論部份特別指出並 清楚地王張。然而，在本菸 *月中，對於組織及操作方法以 及其目的、特徵及優點，畀 又好係參考以下詳細說明並合 附圖加以瞭解，其中： I ^ 口 圖1為根據本發明之一項且蝴^ /、、aa貫她例的封裝斷面圖； 圖2為圖1所示之封裝的另—視圖； 圖3和4為根據本發明乏 ”具體實施例的封裳之斷面 圖。 -10- 200401414 應暸解，為了簡化及清楚起見，圖中所示的元件未必依 比例繪製。舉例而言，為清楚起見，某些元件的尺寸相對 於其他元件故意誇大。 圖式代表符號說明】 18 黏結劑 20 線焊聯結 26 球柵陣列封裝 28 基板 29 積體電路晶粒 30 密封材料 33 焊球陣列之中央 34 焊球 60, 61 被動組件 300 凹洞 400 凹洞

Claims (1)

  1. 200401414 拾、申請專利範圍： 1 · 一種非揮發性記憶體封裝，包冬·· 基板，其具有一第一表面和一第二表面，該第一表 面在該第二表面上方； 知體私路晶粒，叾包含一黏著於該基板之該第一表 面上之記憶體陣列，以及 —被動組件，其係黏著於該基板之該第二表面上。 2. 如申請專利範圍第！項之非揮發性記憶體封裝，其中該 被動组件係電氣耦合至該積體電路晶粒。 3. 如申請專利範圍第丨項之非揮發性記憶體封裝，進一步 包含一黏著於該基板上之焊球陣列。 4. 如申請專利範圍第3項之非揮發性記憶體封裝，其中該被 動组件係位於該等焊球陣列中央。 5·如申請專利範圍第4項之非揮發性記憶體封裝，其中該被 動组件之高度小於該等烊球之高度。 6·如申請專利範圍第1項之非揮發性記憶體封裝，其中該被 動組件係耦合至該積體電路晶粒之一電壓調節器之至 少一部分。 7 ·如申請專利範圍第丨項之非揮發性記憶體封裝，其中該基 板包含一凹洞且該被動组件之至少一部分係位於該凹 洞内。 8·如申請專利範圍第7項之非揮發性記憶體封裝，進一步包 含一黏著於該基板上之焊球陣列，其中該被動組件之高 度係小於該等焊球之高度。 200401414 9 ·如申請專利範1¾第丨項之非揮發性記憶體封裝，其中該被 動、’且件係使用一環氧化物材料以黏著於該基板之該第 —表面上。 10.如申凊專利範圍第9項之非揮發性記憶體封裝，其中該 被動，且件與5亥基板間之該環氧化物材料之厚度小於約 〇. 1毫米。 11 ·如申請專利範圍第丨項之非揮發性記憶體封裝，其中該 被動組件係使用一傳導性材料以黏著於該基板之該第 —表面上^。 12.如申請專利範圍第丨項之非揮發性記憶體封裝，其中該 被動組件包含一電容器或一電感器。 1 3 .如申請專利範圍第1項之記憶體裝置，其中該積體電路 晶粒包含一快閃記憶體陣列。 14.如申請專利範圍第1項之記憶體裝置，進一步包含黏著 於該基板之該第二表面上之複數個被動组件。 1 5 · —種封裝一非揮發性記憶體之方法，包含： 提供一具有一第一表面和一第二表面之基板； 黏著該非揮發性記憶體於該基板之該第一表面上，以 及 黏著一被動組件於該基板之該第二表面上。 16.如申請專利範圍第15項之方法，進—步包含： 於該基板之該第二表面上將一焊球陣列黏著於讀被 動組件周圍。 1 7.如申請專利範圍第1 5項之方法’其中黏著該被動組件包 200401414 含黏著該被動組件於該基板之一凹洞内。 1 8 · —種方法，其包含： 黏著一積體電路於一基板之一第一表面上，該積體電 路包含一非揮發性記憶體陣列，以及 黏著一電壓調節器之至少一部分於該基板之一第二 表面上，該電壓調節器係電氣耦合至該非揮發性記憶體 陣列。 1 9.如申請專利範圍第1 8項之方法，進一步包含黏著一焊球 陣列於該基板之該第二表面上。 20.如申請專利範圍第1 8項之方法，其中黏著該電壓調節器 之至少一部分包含黏著一被動組件於該基板之該第二 表面上。 2 1.如申請專利範圍第20項之方法，其中黏著一被動組件於 該第二表面上包含黏著該被動組件於該基板之一凹洞 内。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080116589A1 (en) * 2006-11-17 2008-05-22 Zong-Fu Li Ball grid array package assembly with integrated voltage regulator
US7675160B2 (en) * 2006-12-29 2010-03-09 Intel Corporation Individual sub-assembly containing a ceramic interposer, silicon voltage regulator, and array capacitor
US20100123215A1 (en) * 2008-11-20 2010-05-20 Qualcomm Incorporated Capacitor Die Design for Small Form Factors
CN103456705A (zh) * 2013-08-21 2013-12-18 三星半导体(中国)研究开发有限公司 堆叠式集成芯片的封装结构及封装方法
KR102157551B1 (ko) 2013-11-08 2020-09-18 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US10446533B2 (en) * 2017-09-29 2019-10-15 Intel Corporation Package on package with integrated passive electronics method and apparatus
CN111128994A (zh) * 2019-12-27 2020-05-08 华为技术有限公司 一种系统级封装结构及其封装方法
KR20220140290A (ko) * 2021-04-09 2022-10-18 삼성전자주식회사 기판을 기준으로 다이의 반대편에 배치되는 캐패시터를 포함하는 패키지 장치

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4885126A (en) * 1986-10-17 1989-12-05 Polonio John D Interconnection mechanisms for electronic components
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
JP3124781B2 (ja) * 1990-03-30 2001-01-15 富士通株式会社 半導体集積回路装置
US5289337A (en) * 1992-02-21 1994-02-22 Intel Corporation Heatspreader for cavity down multi-chip module with flip chip
JPH09501533A (ja) * 1994-04-18 1997-02-10 ガイ フレール バーント エ エクスポルタシオン ソシエテ アノニム 物体用電子メモリ素子
US5434745A (en) * 1994-07-26 1995-07-18 White Microelectronics Div. Of Bowmar Instrument Corp. Stacked silicon die carrier assembly
US5530622A (en) * 1994-12-23 1996-06-25 National Semiconductor Corporation Electronic assembly for connecting to an electronic system and method of manufacture thereof
CN100370602C (zh) * 1997-04-30 2008-02-20 日立化成工业株式会社 半导体元件装配用基板及其制造方法和半导体器件
US5798567A (en) * 1997-08-21 1998-08-25 Hewlett-Packard Company Ball grid array integrated circuit package which employs a flip chip integrated circuit and decoupling capacitors
US6424034B1 (en) * 1998-08-31 2002-07-23 Micron Technology, Inc. High performance packaging for microprocessors and DRAM chips which minimizes timing skews
US6618267B1 (en) * 1998-09-22 2003-09-09 International Business Machines Corporation Multi-level electronic package and method for making same
IT1306963B1 (it) * 1999-01-19 2001-10-11 St Microelectronics Srl Circuito a compensazione capacitativa per la regolazione dellatensione di lettura di riga in memorie non-volatili
US6127726A (en) * 1999-05-27 2000-10-03 Lsi Logic Corporation Cavity down plastic ball grid array multi-chip module
JP3414333B2 (ja) * 1999-10-01 2003-06-09 日本電気株式会社 コンデンサ実装構造および方法
US6362525B1 (en) * 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
US6678167B1 (en) * 2000-02-04 2004-01-13 Agere Systems Inc High performance multi-chip IC package
US6734539B2 (en) * 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package
US6777818B2 (en) * 2001-10-24 2004-08-17 Intel Corporation Mechanical support system for a thin package

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