SU999140A1 - Code converter - Google Patents

Description

(54) CODE CONVERTER

The invention relates to a pulse technique and can be used, ano, in automatic switching systems.

A code converter is known that contains a coding element, for example, performed on key elements with vertical it it command buses, input and output buses 1.

The disadvantage of a code converter is the complexity of its circuitry. This can be achieved by increasing the number of input buses.

Closest to the invention is a code converter containing a subtracting divisor counter; performed, for example, on the basis of a shift register, a binary-decimal counter, an AND element, a decoder, input and output buses 2 / A disadvantage of the known converter is the inability to convert each input code into a sequence of monotonous changes to cix codes. .. The aim of the invention is to enhance the functionality by ensuring the conversion of each input to a sequence.

The monotonous change of the xy xc codes. .

The goal is achieved by the fact that in the code converter, J containing a pulse counter in the shift register, the inputs of which the parallel code is written to the input information buses, the count input of the pulse counter is connected

10 with a clock input of the shift register, the output of the last bit of which is connected to the first inputs of the AND elements, and the PULSE of the clock pulses, the second inputs of the AND elements are connected to the corresponding output of the pulse counter, the output after | its bit. which is connected to the control of the electronic input of the shift register, the serial input of which is connected

20 to constant potential bus, a. the counting input of the pulse counter is connected to the clock pulse bus.

The drawing shows the functional diagram of the Converter codes.

25

The code converter contains a shift register 1, a pulse counter 2, IZ elements, input information buses 4, a constant potential bus 5, a bus 6 clock pulses, and output 7.

Converter codes works as follows.

Shift register 1 operates in two modes; parallel recording mode and shift mode. The setting of the mode of operation of the shift register 1 is carried out from the output of the last digit of the counter 2 pulses. The shift mode is set at the moment of setting the counter 2 to the zero state from the output of its last bit. If in shift register 1, for example, in (p-2) bit, a unit was recorded, then after two such pulses, which are also fed to the counting input of the pulse counter 2, it moves to the last bit of the shift register 1. Logic the unit from the last bit of the shift register 1 is fed to the inputs of the And 3 elements, allowing the information 2 to be copied off, in which the number 2 is written in the binary code. At the same time, the capacity of counter 2 must be greater than the number of input information buses of the shift register 1. When the last bit of the counter 2 is set to one, the parallel writing mode is set and before the counter 2 is set to the zero state, the information from the input buses 4 is copied to the shift register 1, then the cycle repeats.

Thus, the logical unit on the (p-2) input corresponds to code combination 2 in binary code.

It should be noted that in accordance with the type of counter used

in the device you can get the encoding of various types.

Claims (2)

1. USSR author's certificate number 437218, cl. H 03 K 13/252, 1973. 2. Budinsky J. Logic circuits in digital technology. M., Holy, 1977, p. 293, rice, 6.141, and (prototype). gj