SU999020A1 - Program preparation and debugging device - Google Patents

Description

The invention relates to computing and can be used in software control of equipment. A device for preparing and debugging programs is known, comprising control, display and formation units, program I / O, manual input and memory, connected to a switch whose output is connected to a memory block, and a communication adapter with a software control device 11 in the long duration of the preparation and debugging of programs, due to the insufficient information capacity of the memory block and the low degree of automation. Closest to the invention is a device for preparing and debugging programs, comprising a control unit, an information display unit, a switch whose inputs are connected to the outputs of the manual input blocks, a memory and an input / output unit, and an output to the input of the memory block; a communication adapter., with a software control unit and a calculator, the input of which is connected to the output of the memory block and the output to the input of the control unit 1 23 A disadvantage of the known device is the long preparation and debugging time of the programs. This disadvantage is associated with the fact that when preparing a program, the operator must, for each frame of the program being prepared, calculate a control message and write it to the appropriate place in the frame. When debugging, it should be calculated by the operator and recorded instead of the old checksum. When debugging a program, the checksum of the edited frame is changed. The purpose of the invention is to reduce the preparation time for debugging programs by automating the calculations and writing the checksum to the appropriate place in the frame. The goal is achieved by the fact that the device for preparing and debugging programs, which contains a communication adapter and serially connected input / output unit and computing unit, are successively connected to a manual input unit, a switch, a memory unit and a display unit, the first output unit memory connected

with the first input of the computing unit, the switch and with the first input of the communication adapter and the I / O unit, as well as the control unit, the outputs of which are connected to the inputs of the manual input unit, the switch, the memory unit, the I / O unit, the display unit, the computing the unit and the communication adapter, the outputs of each of which, with the exception of the switch, are connected to the inputs of the control unit, the second output of the computing unit is connected to the fourth input of the switchboard.

In addition, the control unit contains a pulse generator, an output connected to a clock distributor and serially connected control panel, a mode generator, an address modification block, a microcommand address register, a fixed memory block, an operator register and a decoder whose outputs are connected to the block outputs, output the clock distributor is connected to the second input of the decoder and to the second input of the block of the Permanent memory, the second output of which is connected to the second input of the microinstruction address register, the third input of the connection nnogo with the second input register operators and yield of the distributor strokes / output operators register coupled to a second input of the address modification unit. ,

FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of the control unit; in fig. 3 - structured memory block diagram; in fig. 4 is a block diagram of a computing unit.

The device (Fig. 1) contains a control unit 1, an information display unit 2, a memory block 3, a switch 4, a manual input unit 5, an I / O block b, a computing unit 7, a communication adapter 8, a second computing output 9 block, a group of inputs 10 of the control unit, a group of outputs 11 of the control unit.

The device operates in the following modes: program input mode} program debugging; mode of preparation of the program; The mode of working out the programm CNC machine.

In the input mode, the program read from the program carrier is fed to the input of the device and entered through the I / O unit 6 and the switch 4 into a series of cells of the memory unit 3. In the process of entering the program consisting of a sequence of frames, it is monitored 10, t that is, the amount modulo 10 numerical equivalents of all the frame symbols, which in a correctly composed and recorded frame must be zero, is controlled.

This amount can be expressed as follows.

mod 10

where n is the number of characters in the frame is the sequence number of the character

frames;

a is the numeric equivalent of a frame character the lower 4 bits of a character).

The checksum of the frame, which is its first character, is determined by the expression

rn -1

AL.J

Cli 10-nwd 10b. ,, I

which for convenience of calculation is converted to

“, -“ ,, j.

where 1) -r-lO-a- is the complement to the ten number equivalent - (- th character. 25) The criterion for the correctness of the reception and recording of a frame is the expression

G n 1

Ts. -0.

mod 10

li - 1 I

Before entering the program, the calculating unit 7 is set to O. For controlling the program in the input mode when recording each frame, the lower 4 bits of all its character codes

: one by one they arrive at the computing unit 7, where they form and sum from the addition to 10. In the first block of the frame in the computing unit 7, the summation accumulates, which in a correctly composed and

this program must be zero. In the case of "alia" in block 7 zero, a signal is received from its first output to input 10 of control unit 1, allowing the recording of a subsequent program frame. Otherwise, the program is stopped.

If the input is made without errors and the program does not require corrections, then in the working mode the program will

the frame is transmitted from the memory unit -3 through the communication adapter 8 to the numerical control device. In the debugging mode, the operator selects the program frame to be corrected using the display unit 2, writes a new line from the keyboard of the manual input unit 5 via switch 4 to the corresponding cell of the storage unit 3 or cancels the line. After each elementary editing act (replacing or discarding a symbol, writing a new symbol Between any neighboring 1, reduced by the operator pressing the corresponding key on the manual input / x 5 block, the control subassembly F1a and recording of the new checksum are automatically included in control block 1. checksum | -1y is performed in the same way as a program modulo 10, however, the summation of the numeric equivalents of the frame symbols starts from the second one. The second computed checksum of the frame remains at block 7, which from the second output 9 of block 7 goes to the fourth input of the switch 4 and then to the cell of the block, memory 3, where it is written in place of the old one. Thus, the entire program is debugged :) . In the program preparation mode, the operator, using the keyboard of the manual input unit 5, writes the program through switch 4 to the memory unit 3, checking for visual accuracy of the input using the information display unit 2. After entering the character, the end of the frame in the block, the control automatically turns on the subroutine calculating the control suyl and recording it on the reserved space of the frame. The calculation and recording of the checksum is performed in the same way as in the debug mode. The prepared and debugged program is stored in blo. Ke memory 3 and through the block input-output can be displayed on the program media for subsequent replication and. storage. The automation of the operation of the device is carried out by the control unit 1 (Fig. 2). The control unit 1 is built on the principle of a microprogrammed automaton and consists of a generator 12, a clock distributor 13, a block of permanent memory 14, an address register of microinstructions 15, a register of operators of an address modification block 17, a decoder 18, a mode generator 19 and a control panel 20. Inputs Control 1 is the group of inputs 10 of the address modification block 17, and the outputs are the group of outputs 11 of the decoder 18 and the output 1 of the clock distributor 13. The control unit 1 operates as follows. The generator 12 through the clock distributor 13 synchronizes the operation of all blocks of the device. The operation algorithm of the device is determined by a program representing a set of micro-instructions stored in block 14. In the initial state, cyclically, from block 14, the sequence of microcommands that control the information display unit 2 and interrogate the driver of modes 19, characterizing the state of the control panel 20 of the device. The operator from the control panel 20 sets the required mode of operation. The block of modification of address 17, written by the driver of work modes 19, changes in register 15 the code of the address selected from block 14 of microxjand. In this case, the first address of the subprogram of the specified mode is formed. The sub-program of each mode consists of a set of chrome commands that are executed or skipped depending on the feedback signals received at the inputs 10 of the address modification block 17 from blocks 2-8. The memory block 3 (FIG. 3) consists of a memory cube 22, a reversible counter 23, two address registers 24 and 25, and decoders 26 to 27. A program is stored in the cells of the memory cube 22. The address of the memory location to which the program symbol code is written or read is determined by the state of the counter 23. Registers 24 and 25 are used to temporarily store the addresses of the program cells (for example, in the correction mode, register 24 stores the address of the cell in which control amount). In order to implement the algorithm of operation of the signal from the control unit 1, they are fed to the input 11 of the memory unit 3. The memory unit 3 performs the following elementary operations: writing to a cube. 22 lines of program memory; reading 22 program lines from the memory cube / changing (+1 or -1) code in counter 23; writing counter code 23 to registers 24 or 25; write code registers 24 or 25 in the counter. The decoder 26 for the control unit 1 analyzes the codes read from the memory cube 22 to identify the contents of the program (for example, the End of Frame feature). The decoder 27 generates a signal to control unit 1, indicating that the code in counter 23 corresponds to the address of the first memory location. Switch 4 (Fig. 1) is intended for connection of the information outputs Oloka 3,5,7 to the information input of the unit 3 by the signals of the control unit 1. The computing unit 7 (Fig. 4) consists of two binary-decimal counters 28 and 29 and a logical element 2I-NOT 30. Input signals to block 7 are fed to inputs 21 and 31 of logic element 30, to input 11 of counters 28 and 29. Signals from memory 3 are received at another input of counter 29. Counters 28 and 29 have counting inputs 32 and 33 respectively. Outputs computing. Block 7 are outputs 9 and 10 of counter 29. The computing unit 7 operates as follows. The initial state in the counter 28 is the code. The overflow signal of the counter 28 on the input 31 of the logic element 30 blocks the flow from the input 21 to the counting inputs 32 and 33 of the counters 28 and 29 clock pulses from the control unit 1. In the counter 29, an arbitrary code is written. Before the calculation, the counter 29 is set to O. During operation, the tetrad of a numerical equivalent of the frame symbol is recorded in the counter 2.8. If the numeric equivalent is non-zero, the overflow signal of the counter 28 locking the logic element 30 is removed, and the input of the counter 28 receives pulses from the clock distributor 13 of the control unit 1 (Fig. 2 The number of incoming pulses is equal to the addition to 10 of the recorded counter code. The counter 28 signal closes the logic element 30 again, and the counter 28 waits for the next line to arrive.The same series of pulses goes to the counting input 33 of the counter 29, in which the modulo sum of 10 additions accumulates to 10 numerical equivalents frame lines, i.e., the control sum of the cadr that goes from the 9th output of the counter 29 to the fourth input of the switch.The use for CNC machines of the Device for preparing and debugging programs with automated testing and recording of checksum allows us the computational block, which operates with the additions up to 10 of the numerical equivalents of the symbols of the ceodra, and the communication that transmits the calculated KOH of the total sum through the auxiliary input of the switch to the input of the memory block, to release the technologist-programmer from aloproizvoditelnoy handmade calculation and record checksum. Thus, the speed of debugging and operational preparation of programs directly from the stack, which take up a significant part of the time and are a bottleneck in the technological process, increases. According to calculations made at the enterprise, the annual economic effect from the introduction of the device is 1.3 thousand rubles. on one machine. Forg-ula inventions 1. A device for preparing and debugging programs comprising a communication adapter and serially connected input / output unit and computing unit, serially connected manual input unit, switch, memory unit and information display unit, first memory unit output connected with the first input of the computing unit, the switch and with the first input of the communication adapter and the I / O unit, as well as the control unit, the outputs of which are connected to the inputs of the manual input unit, the switch, the memory unit, the input-output unit, the Displaying information, a computing unit and a communication adapter, the outputs of each of which, with the exception of the switch, are connected to the inputs of the control unit, characterized in that, in order to shorten the preparation and debugging time of the program by automating the calculations and recording the control signal, with the fourth input of the switch. 2. A device according to claim 1, characterized in that the control unit comprises a pulse generator, an output connected to a clock distributor, and a serially connected control panel, a driver, a mode, an address modification block, an address register of microinstructions, a fixed memory block, an operator register and the decoder, the outputs of which are connected to the outputs of the block, the output of the clock distributor is connected to the second input of the decoder and to the second input of the block of permanent memory, the second output of which is connected to the second input of the address register microc A command, the third input connected to the second input of the register of operators and from the output. the clock allocator house, the output of the register of operators is connected to the second input of the address modification block. Sources of information taken into account in the examination 1. Programming software Pimos Firm Pittler. 2. Installing the control program KP-1 for CNC machines. VIMN, (514), sheet b, 1976 prototype).

I4

II

FIG.

Claims (2)

Claim 1. A device for preparing and debugging programs, containing a communication adapter and series-connected input-output unit and a computing unit, series-connected manual input unit, a switch, a memory unit and an information display unit, the first output of the memory unit is connected to the first input of the computing unit, switch and with the first input of the communication adapter and the input-output unit, as well as a control unit whose outputs are connected to the inputs of the manual input unit, switch, memory unit, input-output unit, information display unit of the computational unit and the communication adapter, the outputs of each of which, except for the switch, are connected to the inputs of the control unit, characterized in that, in order to reduce the time of preparation and debugging of the program by automating calculations and writing the checksum, the second output of the computing unit is connected to the fourth input switchboard. 2. The device according to π. 1, characterized in that the control unit comprises a pulse generator, connected to the clock distributor by an output, and a control panel, a mode former, an address modification unit, a micro-command address register, a read-only memory block, an operator register and a decoder whose outputs are connected to the unit outputs , the output of the clock distributor is connected to the second input of the decoder and to the second input of the read-only memory block, the second output of which is connected to the second input of the micro-command address register, the third input connected to the second input of the register of operators and with the output of the clock distributor, the output of the register of operators is connected to the second input of the address modification block.