SU926784A1 - Frequency-modulated signal detector - Google Patents

Description

one

The invention relates to a kradiotekhnike.

A known detector of frequency-manipulated signals contains a series-connected pulse shaper and a first trigger, as well as a clock generator, the output of which is connected to the First inputs of the first and second estimators whose outputs are connected to the inputs of the OR 1P element.

However, in the known device, the detection accuracy is insufficient.

The purpose of the invention is to increase the reliability of detection.

To achieve this goal, the detector of frequency-manipulated signals, containing a series-connected pulse generator and the first trigger, as well as a clock signal generator, the output of which is connected to the first inputs of the first and second estimators, outputs

2

which are connected to the inputs of the OR element, the second and third triggers and two NAND elements are introduced, the outputs of which are connected to the first, respectively. the second and third trigger inputs, the first inputs of which are connected respectively to the first inputs of the first and second AND-NOT elements, the second inputs of which are connected to the output of the clock signal generator, take the outputs of the first trigger under the third inputs to the third inputs of the second and the third one of the triggers, the second outputs of which are connected respectively to the second inputs of the first and second counters, the third inputs of which are connected respectively to the outputs of the first and second I-NE elements.

The drawing shows a structural electrical circuit of the proposed device.

Claims (1)

The detector contains 1. trigger trigger 2 pulses, the element OR 3, counters and 5 generator 6 clock signals, the elements AND-NOT 7 and 8, triggers 9 and 10.. The detector works as follows: The first branch of the detector, consisting of elements C, and 9), and the second branch, consisting of elements (5 S and 8), are pusher. They are rarely in one of two phases: transitional and steady-state. The phases of branches are switched by trigger 1, controlled by a counting input by an input frequency-manipulated (FM) signal converted by a pulse former 2 into a sequence of rectangular pulses of one of the two frequencies: f, or fa. . While the second branch of the detector is in a transition phase, the first branch is in the steady state. At the same time, the potential input of the logical zero from the direct output of trigger 1 arrives at the second input of the NAND element 7 and the first input of the trigger 9. Triggers E and 10 respond to the potentials of the logical zero on their inputs. Therefore, over setting the shace; the phase at the forward output of trigger 9 is maintained at a potential of logical zero, which acts on the inhibitory input of counter 4. The potential at the output of the last digit of counter 4 remains unchanged and is transmitted through the element OR 3 at the output of the detector. At the moment of transition of the potential at the input input of the element AND-HE 7 from the logical zero to the logical unit, the trigger 9 still remains in the same state, in which the potential of the logical unit arrives at the third input of the AND-HE element 7 from its inverse output. A sequence of rectangular pulses of frequency fj from the output of the generator 6 of such signals is constantly fed to the first input of the NAND 7 element. At the output of the element, AND-HE 7, only one inverted pulse can appear, which acts on the second input of the trigger 9 and translates it into the opposite one:. state, and also affects the installation input of the counter k and sets all its bits to the state of logical zero. From this moment on, the transition phase of the first branch of the detector begins, and the second branch will be in the established phase. In this case, the clock 92 pulses of the frequency fj arriving at the counting counter k are counted in it. The transition phase continues until the next change of sigmal values at the information input of the branch, i.e. until a logical zero signal appears at its input. The state of the last bit of the counter C at the end of the transition phase — a logical zero or a logical one — depends on the duration of the transition phase. If the frequency of the input signal f ,. , where n is the number of binary bits of counter C, then at the output of the branch at the end of the transition phase the potential of the logical unit will be established, and otherwise - the logical zero. The first and second branches of the detector alternately decide on the corresponding inputs of the element OR 3 about each; home Period of the signal arriving at the input, so that the output of the detector maintains the level of a logical unit or logical zero depending on the frequency of the input signal. In order to avoid overflow of the discharge grid of counters t and 5 with the duration of the transition phase, exceeding the total bt fV, they can be implemented, for example, on -K-flip-flops, the R-inputs of which are combined and serve to send a reset signal, 1-K trigger inputs of the first the bit is combined and used to signal the Inhibit signal, the C inputs are used as counting inputs, and the inverse output 1-K of the trigger of the last bit is connected to the I and K inputs of the same bit to prevent overflow (counter). detected The proposed detector is characterized by simplicity of design and high reliability and can be used in information and training information systems, in data transmission equipment, as well as in devices for reproducing binary signals recorded on a magnetic carrier. signals containing a serially connected pulse driver and the first trigger, as well as a clock generator, the output of which is connected to the first input The first and second counters, the outputs of which are connected to the inputs of the element, differing in that, in order to increase the reliability of detection, the second and third triggers and two AND-NOT elements, the outputs of which are connected respectively to the first inputs of the second and third triggers, are introduced, the first the outputs of which are connected to each other, respectively, with the first inputs of the ne | 5th and second EE elements, the second inputs of which are connected to the output of the clock signal generator, and the outputs of the first trigger are connected to the third inputs of the elements AND –NE and II th inputs of the second and third flip-flops, the second outputs of which are connected respectively to the second: inputs of said first and second counters, the third inputs of which are connected respectively to the outputs of the first and second AND-NO elements. Sources of information taken into account in the examination 1. USSR author's certificate ff. cl. H Ok 127/1, 1977 (prototype).  -