SU864512A1 - Pulse generator - Google Patents

Description

The invention relates to a pulse technique and can be used in a communication device, in particular as a device for automatically adjusting the gain in a signal regenerator with pulse code modulation. Pulse regenerators are known that contain an amplifier with a controlled gain factor and a solver. Distorted information pulses and interferences enter the input of the resolver, normalized pulses are generated at the output of the resolver. The presence or absence of a pulse at the output of the resolver is determined by the pulse parameters at its output, in particular, the pulse amplitude at clock points of time 1. The disadvantage of such regenerators is There is insufficient prmekhozshshshennost. The closest to the technical essence of this invention is a regenerator, which contains an amplifier with controlled gain, the input of which is connected to the integrator output, and the output of the pager is connected to the first inputs of the first and second solvers, to the second inputs of which the clock source impulses are connected The outputs of the first and second resolvers are connected to the inputs of a logical memory, the output of which is connected to the input of the integrator 2J. The disadvantage of the aairaoro device is the reduction in the noise immunity of the pulse generator as compared with the optimal variant of the operation of the resolver. The reduction in noise immunity is caused, in particular, by the random nature of the signal. Since the logical memory saves one of two states until the next information pulse appears, the voltage at the integrator output will change to one side in. the flow of time of the entire packet of zeros at a rate determined by the integrator time constant. The purpose of the invention is {increasing the noise immunity of the pulse generator. The goal is achieved by the fact that the pulse regenerator contains an amplifier whose input is connected to the integrator's output, and the output is connected to the first inputs of the first and second resolvers, the second of which are connected to the output of the clock source, and the outputs are connected to the inputs of the memory unit and current sources connected to the integrator input, the output of the memory unit through a single current source soy; wired to the integrator input, and the output of the clock source source is connected to the corresponding input of the memory unit.

The achievement of the set goal is also possible by the fact that the output of the logical memory is connected via a key to the integrator input, and the output of the first resolver is connected to the control input of the key.

The drawing shows a structural diagram of the proposed pulse regenerator, comprising an amplifier t with controlled gain, the input of which is connected to the output of integrator 2, and the output of amplifier 1 is connected to the first inputs of the first and second solvers 3 and 4, to the second inputs of which the source output is connected 5 clock pulses, the outputs of the first and second solving devices 3 and 4 are connected to the inputs of the memory block 6, the output of which is connected to the integrator 2 via the first current source 7, the output of the second current source 8 is connected with an input of the integrator 2, .a clock source 5 output is connected to the corresponding input of the memory unit 6 m.

The device works as follows.

In the absence of informatics pulses at the output of the first resolver 3, memory unit 6 is switched to the division mode into two clock frequencies, coming from the output of the source 5 clock pulses. Thus, when a packet of zeros appears in the information signal at the output of memory block 6, a sequence of units and quenches is forced with a duty cycle equal to two. Moreover, if the magnitude of the discharge current and the charge current of the integrator 2 is chosen, based on the requirement that when the duty cycle of the pulses at the output of memory block 6 is two, the voltage at the output of integrator 2 does not change, then regardless of the length of the packet of zeros, amplitude of information pulses at the input

After deciding the packet of zeros, the decisive devices 3 and 4 will be equal to the amplitude of the information pulses arriving at the packet of zeros, since the voltage at the output of integrator 2, and hence the gain factor of amplifier 1, does not change during the whole time of the packet of zeros.

The positive effect of the invention is to increase the noise immunity of the pulse generator due to the fact that

the operation of the device for automatic gain control is not affected by the random nature of the signal (the voltage at the output of integrator 2 does not depend on the moment of the appearance of information pulses. The presence of charge and discharge current sources 7 and 8 ensures the required ratio of charge and discharge currents on the value of the voltage on the integrator 2); the interference that forms the zero output at the output of the first solver 3 does not change the voltage at the output of the integrator 2, which ensures the optimal reception of information pulses after the interference ends.

Claims (2)

1. USSR author's certificate M 352366, 5 cells. H 03 K 3/00, 1971. 2. Author's testimony USSR N 632064, cl. N. 03 K 3/64, 1977.