SU813404A1 - Information output device - Google Patents

Description

(54) DEVICE FOR INFORMATION OUTPUT

one

The invention relates to information measuring systems and can be used for remote output of alphanumeric text, as well as for building information output systems from the control computer complex ACBT-M-6000 to dispatcher control consoles.

A device for displaying information using third-order matrix displays with a control circuit is known. The display board in this device consists of K identical sectors made on the basis of a two-dimensional matrix board, and the cxeriibi control, into which the K-bit sector select register is entered. Each of these sectors is an independent functionally complete node, so structurally it can be made by a separate sub-frame (pht) familiarity (n is the number of rows, w is the number of columns) 1.

The disadvantage of such devices is the low speed and a large number of switching communication channels.

Closest to the proposed one is a device for controlling a matrix scoreboard containing an information input block connected to one input of a register of columns, another input of which is central to the input of a row selection register and a sector select register, logic block, group of switches, block of gates, interrogation the input of which is connected to the output of the register of columns, and the control inputs to the address outputs of the sector selection register and the inputs of the logic block, the outputs of the valve block are connected to the switch inputs, one output rows are connected to a control input sector selection register and the output register row and the other outputs - to one input of logic block input lines and a register whose output is connected to another input of logic unit, whose output is connected to the input register 2 sector selection.

The disadvantages of this device are also low speed and a large number of switching communication channels.

The purpose of the invention is to increase the speed and simplify the device.

Claims (2)

The goal is achieved in that the address decoder is made of modules. arranged in hierarchical levels, a distinctive feature of each addressable module being that it includes an information storage register and a matrix (linear) decoder. The proposed device is also distinguished by the fact that in it all modules are of the same type and are functionally complete nodes. The output of the buffer register is associated with one of the outputs of the address modules located on the first, second m, and third level. and also with indication cells. The outputs of the module of the first level are connected to the inputs of the modules of the second level, and the outputs of the modules of the second level are connected to the inputs of modules of the third level, the outputs of which are connected to the display cells. Modules of the third level are located in control rooms. If it is necessary to form a large-scale scoreboard, then the modules of the third level and one module of the second level (if the number of outputs of the module of the second level is equal to the number of modules of the third level) are assembled with a single cassette and are constructively executed as a separate sub-table. Such a construction of the address decoder allows, with an increase in the size of the input word, to expand the structure and distribute it to the geographically dispersed dispatcher consoles without increasing the number of communication channels. The use of the register of information storage in the address module allows applying the principle of a common bus and transmitting information in a serial code, which reduces the number of switching communication channels to a minimum. In addition, the information output device is equipped with a remote control unit, which allows manual entry of information in order to correct it on the screens. FIG. 1 is a block diagram of the device; in fig. 2 - time diagram of the device. The device contains a buffer register 1 for receiving a parallel binary code from a computer and converting it into a serial code. The inputs of register 1 are connected to the outputs of the computer, the control panel 2 for maintaining the device in autonomous mode, and the control unit 3, which is used to generate control clock pulses, as well as to generate a device readiness signal (TG-T) confirming permission to enter information. Upon exit, register 1 is associated with the input of the module 4 of the first level of a pyramidal decoder, built according to a modular principle, designed to store the received information and select the second level module 5 in accordance with it with each input of the second level modules 5. with each input of the modules of the third level 6 and with the display cells 7. On the output, the control unit 3 is connected with the inputs of the computer and with the input of the module 4 of the first level. The output of the module 4 of the first level is connected to the input from the module 5 of the second level, the outputs of the modules 5 of the second level are connected to the inputs of the modules of the third level, and the outputs of the modules 6 of the third level are connected to the display cells 7. The display cell 7 is intended for visual display of information. The operation of the proposed output of production information is as follows. From the computer at the entrance to the buffer register receives a parallel binary code. Buffer register 1 stores the received information. The control unit 3 generates a device busy signal () and begins processing the received data. According to the signals K1 from the control unit 3, the parallel code is converted into a serial code in the buffer register 1 and is overwritten by the signals K2 in the module 4 of the first level. In this case, the contents of the highest bits of the buffer register 1 are stored and decoded by the module 4 of the first level. In accordance with the input code, a single resolving potential will be present on one of the output buses of the matrix decoder of the first level module 4. In the presence of this potential, as well as synchronizing signals of the control unit 3, the next group of bits is received from the buffer register into one of the second level modules 5. The functions performed by the second level module 5 are similar to those of the first level module 4. The obtained high potential at one of the output buses of the second level module 5 and the clock signal K4 of the control unit 3 forms the enable potential for receiving the next group of bits of the buffer register 1 to the third level module 6. The obtained control potential at one of the output buses of the third-level module 6 forms the control potential for selecting the indication cell 7. Using the obtained permitting potential and the synchronization signal K5 of the control unit, the code of the displayed character is overwritten and is decoded in the display cell 7. Upon completion of this cycle, the block m. 3 control generates a device readiness signal (), i.e., the device is ready to receive new information. The invention of the device for outputting information containing a buffer register connected with a control unit, and an address decoder, the outputs of which are connected to indication cells, characterized in that, in order to increase speed and simplify the device, the address decoder is made of modules arranged in hierarchical levels, each of the modules consisting of a register of information storage and matrix decoder, the outputs of my / iul of the first level are connected to the inputs of the modules of the second level, the outputs of the modules of the second crop are connected to the inputs of the modules of the third level, the outputs of the modules of the third T КзКг Ц. IH ± I The first level is connected to the indication cells, the output of the buffer register is connected to the input of the first-level module, to the input of the second-level modules, to the input of the third-level modules and to the indication cells. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 401991, cl. G About F 3/14, 1970. 2. USSR author's certificate No. 551636, cl. G 06 F 3/14 1975 (prototype). -fyE & 1