SU794706A1 - Frequency synthesizer - Google Patents

Description

(54) FREQUENCY SYNTHESIZER

The invention relates to radio engineering, can be used to form a grid of frequencies in radio transmitting and receiving devices.

A known frequency synthesizer comprising a series-connected reference oscillator, a phase detector, a first low-pass filter, a controlled oscillator, and a frequency divider with a variable division factor of 1.

However, the known frequency synthesizer has an insufficiently high speed and insufficiently low level of output noise, due to the narrow bandwidth of the phase-locked loop (PLL) and its limited bandwidth.

The purpose of the invention is to increase the speed and decrease the level of the output noise.

To do this, a serially connected adder, a digital-to-analog converter, a second low-pass filter, and a pulse shaper are inserted into the known frequency synthesizer between the output of a frequency divider with a variable division factor and another input of the phase detector, and a newly entered code register is connected to the information inputs of the adder.

FIG. 1 shows the structural scheme of the proposed frequency synthesizer; in fig. 2 - timing charts of the device. Frequency synthesizer contains

reference oscillator 1, phase detector 2, first low-pass filter 3, controlled oscillator, variable frequency division divider 5 (DFD), code register 6, adder 7, digital-to-analog converter (DAP) 8, second low-pass filter 9 and driver 10 pulses.

The frequency synthesizer works as follows.

The generator / is intended for synchronization of the frequency synthesizer. The detector 2 compares the frequency of the generator / with the frequency supplied to the detector 2 via a feedback circuit from the output of the driver 10, and

produces an error signal proportional to the phase difference of the compared signals, filter 3 extracts the constant component of the signal and supplies it to the input of controlled oscillator 4. Generator 4

serves to form a frequency grid: its output is the synthesizer output. PDKD 5 is designed to pre-divide the frequency of the generator 4; division factor DPKD 5 in the proposed

The synthesizer is chosen to be significantly smaller than what is known. Adder 7 is used to sequentially sum up when the pulses from the DCCD 5 are received, the values of the frequency code recorded in the register of code 6.

Converter 8 converts the code of the adder 7 into the corresponding voltage values. Filter 9 is used to form an analog sinusoidal signal from discrete samples.

The shaper 10 serves to generate pulses corresponding to the zero of the sinusoid at the output of the filter 9.

FIG. 2 shows time diagrams explaining the operation of the frequency synthesizer. Here, U, is the signal at the output of the generator 4, Us is the signal at the output of DCDD 5, C is the code recorded in accumulator 7, N is the total capacity of accumulative adder 7, n is the code set in code register 6, tn is the moment overflow cumulative adder 7, C - the rest of the code after overflow cumulative adder 7, Us is the signal at the output of converter 8, UQ is the output signal of filter 9, f / io is the output signal of the driver 10, Dt is the phase shift of the signal at the output of the generator 10 relative to the signal generator 4, U - signal at the output of generator 1, U - sig al at the output of the detector 2.

The output frequency of the generator 4 is preliminarily divided by the coefficient M DPCD 5 to the frequency necessary for the stable operation of devices connected to the output of the PDCD 5 (in Fig. 2 for example M 2). The pulses from the DPKD 5 output go to the synchronizing input of the adder 7, and when the output pulse arrives in the adder 7, the contents of the frequency code register are entered. When the capacity N of the adder 7 is exceeded, it overflows (moment) and the process repeats, but this time Once the summation begins with the value C, the remainder of the code after the overflow.

The output code of the adder 7 enters the DAC INPUT 8, which first performs the conversion of the code of the adder 7 into a sinusoid code, and the output capacitor 7 N is assumed to be equal to one sinusoidal neyrode, i.e. 2, the sinusoid frequency of which will be NIn times lower than the signal frequency the output of the adder 7, therefore, the output frequency of the generator 4 will be reduced in M NIn times. The digital values of the sine wave are then converted to the voltage corresponding to the input code. The voltage from the output of converter 8 is fed to a filter 9, which extracts the analog sinusoidal signal from the output signal. The shaper 10 generates signals corresponding to the moments of the transition of the sinusoid through the zero level; then the phase of the output signal of the driver 10 is compared on the detector 2 with the phase of the generator signal /. At the output of the detector 2, an error signal is generated, which is filtered on the filter 3 and fed to the input of the generator 4 to adjust the frequency.

The frequency of the sinusoid at the output of the filter 9 (/ a) is related to the frequency at the output of the generator 4 (tyr) as follows:

gfll

/ Oj zir / corner d | dg; 1De / I - division ratio

DPKD 5. Thus, the output frequency of the generator 4 will be divided into M NIn. Since in synthesizers with a divider in the feedback circuit, the frequency of the output signal is equal to the frequency of the input multiplied by the division factor in the feedback chain, for the circuit in question, you can write

Mn

P

where / og is the frequency of the reference oscillator /.

Since in the general case the numbers M and n, N and n are not multiples, the resulting multiplication factor is fractional.

The moment of the signal at the output of the imaging unit 10 in the general case does not coincide with the moment of occurrence of the signal at the output of the generator 4 (phase shift At), which corresponds to the repeated division of the frequency of the generator 4 (Fig. 2).

This non-repeated frequency division is performed using digital methods, which ensures high division accuracy, and, in addition, a sinusoid, and output

The second low-pass filter is uniformly distributed with respect to the output of the controlled oscillator.

: As follows from the theory of Kotelnikov,

To form an analog sinusoid from discrete samples, at least two samples per sinusoid period are necessary. In practice, however, to facilitate the requirements of the low-pass filter (block 9 in

This device, FIG. 1), at least four samples are taken. Therefore, the ratio NIn should be less than 4. For example, take M 10, N 2, n -i 116383. In this case, the resulting division factor will be equal to 10 X Хв5636 / 16383 40,00244. If you specify p 16382, the resulting division factor will be 10X65536 / l & 3i82 40.00488. If you select, for example, the oscillator frequency / equal to kcrHz, then these two coefficients will correspond to the following frequencies of the controlled oscillator (and, therefore, synthesizer): 4.000244 MHz and 4.000488 MHz. The frequency step at the output of the synthesizer will be

244 Hz, and the output frequency is about 4 MHz and the frequency of the reference oscillator is 100 kHz. In order to obtain the same frequency ratio at the output of a known device with an integral division ratio of DCPD, the value of this coefficient should be around FOOO, the frequency of the reference oscillator will be equal to the frequency step at the output of the synthesizer and will be 244 Hz, i.e. 400 times the number with the result, they are from here (Disadvantages.

Note that, in the proposed device, the PDCD 5 performs a slightly different role than in the well-known one: it produces a decrease in the frequency of the generator 4 to the values necessary for ensuring the stable operation of the included after 5 devices.

Increasing the frequency of comparison and lowering the division ratio at a constant output frequency step allows for a number of advantages of the proposed device. First, increasing the comparison frequency of the PLL circuit simplifies the design of the first low-pass filter (5) and provides a comparison frequency injection, which reduces the level of harmonic components in the synthesizer output. Secondly, the expansion of the bandwidth of the first lowpass filter (5) allows to increase the speed of the frequency synthesizer, i.e., reduce the time for changing frequencies. Third, the bandwidth extension of the FSH circuit contributes to the improvement of the self-noise suppression of the controlled oscillator, which reduces the noise level at the output of the frequency synthesizer. Finally, reducing the division ratio in the feedback value leads to a decrease in the degree of multiplication of noise coming through the oscillator channel, thereby reducing the noise in the output signal spectrum of the synthesizer during offsets from the carrier not exceeding the bandwidth of the PLL circuit.

In addition, by increasing the bit size of the adder 7 and register 6, it is possible to obtain a further decrease in the step grid of the output signals of the synthesizer frequencies without reducing the frequency of the comparison.

Claims (1)

1. Galin A. S. Band-quartz stabilization GB4, M., “Sv, 1976, p. 77 (prototype). Js 7 .7 BUT / Yu zht w